UDK 621.3:(53+54+621 +66)(05)(497.1 )=00 ISSN 0352-9045 Strokovno društvo za mikroelektroniko elektronske sestavne dele in materiale MIDEM 2008 Strokovna revija za mikroelektroniko, elektronske sestavne dele in materiale Journal of Microelectronics, Electronic Components and Materials INFORMACIJE V TRETJEM DESETLETJU INFORMACIJE MIDEM, LETNIK 38, ŠT. 1(125), LJUBLJANA, marec 2008 SlroKovn» iml|D II mlHjiwfckhonlko, dlllimillU rtnlc In miKgrfjilt Jmirnjl m Mlcmclribamcí Éledronli; Comp«! en I» and MUltfrMc Slroksvna rtrutlvif zn mlkralohlroriko, pteklronske sEíism? dele In meterlale í trueno' díuÉtva ra mikraelpklronikLi. pleldronske mlani« delava I inaterljalp i'rCFUtl.L MIDE» L£TW IT JT. 4ÍIÍ4L UlIBUÍH».*«itl> ¡04' LJUBLJANA. MAREC 1958, ÍETNlK-GOOlNft IS, ŠTEVILH1-BR0J UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 INFORMACIJE MIDEM 1 o 2008 INFORMACIJE MIDEM LETNIK 38, ŠT. 1(125), LJUBLJANA, MAREC 2008 INFORMACIJE MIDEM VOLUME 38, NO. 1(125), LJUBLJANA, MARCH 2008 Revija izhaja trimesečno (marec, junij, september, december). Izdaja strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale - MIDEM. Published quarterly (march, june, september, december) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Glavni in odgovorni urednik Editor in Chief Dr. Iztok Šorli, univ. dipl.inž.fiz., MIKROIKS, d.o.o., Ljubljana Tehnični urednik Executive Editor Dr. Iztok Šorli, univ. dipl.inž.fiz. MIKROIKS, d.o.o., Ljubljana Uredniški odbor Editorial Board Dr. Barbara Malič, univ. dipl.inž. kem., Institut "Jožef Stefan", Ljubljana Prof. dr. Slavko Amon, univ. dipl.inž. el., Fakulteta za elektrotehniko, Ljubljana Prof. dr. Marko Topič, univ. dipl.inž. el., Fakulteta za elektrotehniko, Ljubljana Prof. dr. Rudi Babič, univ. dipl.inž. el., Fakulteta za elektrotehniko, računalništvo in informatiko Maribor Dr. Marko Hrovat, univ. dipl.inž. kem., Institut "Jožef Stefan", Ljubljana Dr. Wolfgang Pribyl, Austria Mikro Systeme Intl. AG, Unterpremstaetten Časopisni svet Prof. dr. Janez Trontelj, univ. dipl.inž. el., Fakulteta za elektrotehniko, Ljubljana, International Advisory Board PREDSEDNIK - PRESIDENT Prof. dr. Cor Claeys, IMEC, Leuven Dr. Jean-Marie Haussonne, EIC-LUSAC, Octeville Darko Belavič, univ. dipl.inž. el., Institut "Jožef Stefan", Ljubljana Prof. dr. Zvonko Fazarinc, univ. dipl.inž., CIS, Stanford University, Stanford Prof. dr. Giorgio Pignatel, University of Padova Prof. dr. Stane Pejovnik, univ. dipl.inž., Fakulteta za kemijo in kemijsko tehnologijo, Ljubljana Dr. Giovanni Soncini, University of Trento, Trento Prof. dr. Anton Zalar, univ. dipl.inž.met., Institut Jožef Stefan, Ljubljana Dr. Peter Weissglas, Swedish Institute of Microelectronics, Stockholm Prof. dr. Leszek J. Golonka, Technical University Wroclaw Naslov uredništva Uredništvo Informacije MIDEM Headquarters MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenija tel.: + 386 (0)1 51 33 768 faks: + 386 (0)1 51 33 771 e-pošta: Iztok.Sorli@guest.arnes.si http://www.midem-drustvo.si/ Letna naročnina je 100 EUR, cena posamezne številke pa 25 EUR. Člani in sponzorji MIDEM prejemajo Informacije MIDEM brezplačno. Annual subscription rate is EUR 100, separate issue is EUR 25. MIDEM members and Society sponsors receive Informacije MIDEM for free. Znanstveni svet za tehnične vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Scientific Council for Technical Sciences of Slovene Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is financed by Slovene Research Agency and by Society sponsors. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™ Scientific and professional papers published in Informacije MIDEM are assessed into COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™ Po mnenju Ministrstva za informiranje št.23/300-92 šteje glasilo Informacije MIDEM med proizvode informativnega značaja. Grafična priprava in tisk BIRO M, Ljubljana Printed by Naklada 1000 izvodov Circulation 1000 issues Poštnina plačana pri pošti 1102 Ljubljana Slovenia Taxe Perçue UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana ZNANSTVENO STROKOVNI PRISPEVKI PROFESSIONAL SCIENTIFIC PAPERS B. Sviličic, V. Jovanovic, T. Suligoj: Vertikalni SONFET; modeliranje podpragovne tokovne karakteristike 1 B. Sviličic, V. Jovanovic, T. Suligoj: Vertical Silicon-on-Nothing FET: Subthreshold Slope Calculation Using Compact Capacitance Model A.Čampa, J.Krč, M.Topič: Dvo-dimenzionalni optični model za simulacijo periodičnih optičnih struktur v tankoplastnih sončnih celicah 5 A.Čampa, J.Krč, M.Topič: Two-dimensional optical model for simulating periodic optical structures in thin-film solar cells A.Levstek, M.Pirc: SMD filmski kondenzatorji za integracijske A/D pretvornike 11 A.Levstek, M.Pirc: SMD Film Capacitors for Integrating A/D Converters K.Gorecki, Witold J. Stepowicz: Primerjava modelov induktivnosti uporabljenih pri analizi DC-DC konverterjev 20 K.Gorecki, Witold J. Stepowicz: Comparison of Inductor Models Used in Analysis of the Buck and Boost Converters Gregor Papa, Tomasz Garbolino: Nov pristop k optimiranju strukture generatorja testnih vzorcev 26 Gregor Papa, Tomasz Garbolino: A New Approach to Optimization of Test Pattern Generator Structure Ž.Čučej, K.Benkič: Komunikacija dvojnega optičnega obroča med gradniki močnostne elektronike: študija primera 31 Ž.Čučej, K.Benkič: Two Optical Ring Communication Between Power Electronic Building Blocks: a Case Study S.Klampfer, B.Curk: Robotizacija proizvodnje - robotsko sestavljanje 36 S.Klampfer, B.Curk: Robotization of manufacture yield - constructing with robot F.Pavlovčič, J.Nastran: Nastanek električnih razelektritvenih oblokov 42 F.Pavlovčič, J.Nastran: The Arising of Electric Discharge Arcs Z.Mezgec, A.Medved, A.Chowdhury, R.Svečko: Mobilno plačevanje - razvoj sodobnega terminala 53 Z.Mezgec, A.Medved, A.Chowdhury, R.Svečko: Mobile Payments-Design of New Terminal M.Smolnikar, A.Hrovat, M.Mohorčič, I.Ozimek, T.Celcer, G.Kandus: Daljinsko merjenje in upravljanje preko omrežja TETRA 61 M.Smolnikar, A.Hrovat, M.Mohorčič, I.Ozimek, T.Celcer, G.Kandus: Telemetry and Telecontrol over TETRA Network Revija Informacije MIDEM je vstopila v tretje desetletje 69 The Journal »Informacije MIDEM« entered its third decade POSEBNA IZDAJA - dvajset letnikov revije Informacije MIDEM na CD ROMu 71 SPECIAL EDITION - Twenty Volumes of Informacije MIDEM on CD ROM MIDEM prijavnica 72 MIDEM Registration Form Slika na naslovnici: Revija Informacije MIDEM je vstopila v tretje desetletje Front page: The Journal »Informacije MIDEM« entered its third decade VSEBINA CONTENT Obnovitev članstva v strokovnem društvu MIDEM in iz tega izhajajoče ugodnosti in obveznosti Spoštovani, V svojem več desetletij dolgem obstoju in delovanju smo si prizadevali narediti društvo privlačno in koristno vsem članom.Z delovanjem društva ste se srečali tudi vi in se odločili, da se v društvo včlanite. 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Kot član strokovnega društva prejemate revijo »Informacije MIDEM«, povabljeni ste na strokovne konference, kjer lahko predstavite svoje raziskovalne in razvojne dosežke ali srečate stare znance in nove, povabljene predavatelje s področja, ki vas zanima. O svojih dosežkih in problemih lahko poročate v strokovni reviji, ki ima ugleden IMPACT faktor.S svojimi predlogi lahko usmerjate delovanje društva. Vaša obveza je plačilo članarine 25 EUR na leto. Članarino lahko plačate na transakcijski račun društva pri A-banki : 051008010631192. Pri nakazilu ne pozabite navesti svojega imena! Upamo, da vas delovanje društva še vedno zanima in da boste članstvo obnovili. Žal pa bomo morali dosedanje člane, ki članstva ne boste obnovili do konca leta 2008, brisati iz seznama članstva. Prijavnice pošljite na naslov: MIDEM pri MIKROIKS Stegne 11 1521 Ljubljana Ljubljana, marec 2008 Izvršilni odbor društva UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana VERTICAL SILICON-ON-NOTHING FET: SUBTHRESHOLD SLOPE CALCULATION USING COMPACT CAPACITANCE MODEL B. Sviličic1, V. Jovanovic2, T. Suligoj3 1Faculty of Maritime Studies, University of Rijeka, Rijeka, Croatia 2ECTM-DIMES, Delft University of Technology, The Netherlands 3Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia Key words: Silicon-on-Nothing, fully-depleted MOSFET, vertical SONFET, subthreshold slope, compact model Abstract: The subthreshold slope model of the Vertical Silicon-on-Nothing FET, extracted from the compact capacitance model, has been developed. For short-channel effects modeling the voltage-doping transformation is used. The analytical model is verified by comparison to the two-dimensional numerical device simulator, MEDICI, over a wide range of different device structures. Good agreement is obtained for channel lengths down to 50 nm. Vertikalni SONFET: modeliranje podpragovne tokovne karakteristike Kjučne besede: SONFET, vertikalni SONFET, naklon podpragovne tokovne karakteristike, modeliranje Izvleček: Razvili smo model podpragovne tokovne karakteristike vertikalnega tranzistorja SONFET ( Silicon-on-nothing FET ). Analitični model smo preverili s primerjavo rezultatov dobljenih z dvodimenzionalno simulacijo s programom MEDICI. Dobili smo dobro ujemanje izračunanih in izmerjenih vrednosti za dolžine kanala navzdol do 50nm. 1 Introduction The scaling of conventional CMOS is approaching technological limits /1/, and the need for replacement device architecture is growing. A possible alternative is the Silicon-on-Nothing (SON) technology /2/, where the epitaxial process is used for the formation of the sacrificial SiGe layer and top Si layer for the active device part. The sacrificial SiGe region is later removed below transistor channel and replaced by an insulating material, resulting in quasi-SOI structure in the active region. However, the SON MOSFET (SONFET) transistors are processed on bulk Si wafers with reverse biased source and drain junctions to the substrate. This eliminates one of the major advantages of standard SOI technologies, which is the reduction of parasitic capacitances. The SON technology can also be transferred to SOI substrate, but with considerable increase in process complexity. The Vertical Fully-Depleted SONFET (VFD SONFET) is developed as a further evolution of the lateral SONFET /3, 4, 5/. The channel length of the vertical SONFET is defined by the molecular-beam epitaxy (MBE), allowing the channel-length reduction into the sub-30 nm region without the need for high-resolution lithography. Furthermore, standard bulk region underneath the buried oxide is eliminated (Fig. 1.). The absence of the transistor bulk is a unique property of the VFD SONFET, not present in either bulk or SOI CMOS. The subthreshold slope value is one of the key issues for deep-submicrometer devices, with the target value of 60 mV/dec at temperature of 300 K. In this paper, we give an analytical solution for the VFD SONFET subthreshold slope based on the compact capacitive model in subthreshold region. The voltage-doping transformation (VDT) is used for short-channel effects modeling and the solutions are verified in comparison to the results of two-dimensional device simulator. 2 Modelling 2.1 Capacitive model in subthreshold region The analytical solution for subthreshold slope is based on the capacitive model in subthreshold region (Fig. 2.). The compact capacitive component model for the VFD SON-FET operating in accumulation, depletion and inversion condition is presented in /6/. Intrinsic capacities include the capacitance of the depleted silicon body Csi,d, gate oxide capacitance CGox=kGoxLeff/tGox, and buried oxide capacitance Cbox: 2k BOX ' BOX In 1 + - Ueff (1) box y 1 Informacije MIDEM 38(2008)1, str. 1-4 B. Svilicic, V. Jovanovic, T. Suligoj: Vertical Silicon-on-nothing Fet: Subthreshold Slope Calculation Using Compact Capacitance Model 1-Si channel D N+ ^ GOX BOX X poly-Si G S N+ ^J P substrate Fig. 1. (a) VFD SONFET structure cross-section, (b) VFD SONFET structure close-up. Fig. 3. Equivalent capacitive circuit of the VFD SONFET in the subthreshold region. relation is given with an approximation by perpendicular planes. For the effective channel lengths that are tBOX < Leff/2 analytical relation is given: 2k i -In 1 + - 4BOX (2) Overlap, fringe and source/drain depletion capacitances are also included in Fig. 2, but do not have significant influence on the subthreshold slope. Equivalent capacitive circuit of the VFD SONFET in the subthreshold region is shown on the Fig. 3. Applying the Ohms law at each node, we calculate the relation between the front-gate surface potential yS1 (interface gate-oxide/Si-film) and the back-gate surface potential YS2 (interface Si-Film/BOX) /Fig. 1 (b)/: ^BOX + CSi4 ^G y FBI + ÍSi.d 2 C + Ca^.2 (3) GOX y = C„ (TD VFB2 (Ks ^FBl}Jr 2C„ (4) Fig. 2. Capacitive model of the VFD SONFET in the subthreshold region. The buried oxide capacitance Cbox of the VFD SONFET has specific, two-dimensional properties and its analytical where QSi,d=-qNAtSi is the depletion charge, VFB1 = VTln(NGNA/ni2) is the top-gate flat-band voltage, VFB2=VTln(NSD>NA/ni2) is the back-gate flat-band voltage, and Vd and Vs are drain and source voltages, respectively. With source voltage being zero (Vs=0), the following relations can be used: Vd+Vs=Vd=Vd-Vs=Vds. From the equivalent capacitive circuit, the analytical solution for the gate voltage VG is extracted: V = v +*p G 'FBI T Til 1 + C 1C Si,d BOX Coox(psi,d + 2CB0X) ' i i ^ —+— y Csi,d CBi c c Sid BOX C C Si 4 BOX (Çsi/i + 2 CBOX ) (5) : + 2V, c c Si,d BOX C-GOX (pSi,d + 2CB0X ) CG0X (cs¡/1 + 2 CB0X ) 2.2 Two-Dimensional Effects: Voltage Doping Transformation An elegant and compact solution for two-dimensional model is offered by the concept of Voltage-Doping Transformation (VDT) /7/. VDT enables to account for 2D-effects into 2 B. Svilicic, V. Jovanovic, T. Suligoj: Vertical Silicon-on-nothing Fet: Subthreshold Slope Calculation Using Compact Capacitance Model Informacije MIDEM 38(2008)1, str. 1-4 quasi ID-analysis of the VFD SONFET. According to this concept, the influence of the lateral field initiated by the junctions is equivalent to a reduction in the effective channel area doping. The effective doping in channel area: e 2V M* =M — Si DS A A _r2 ikf Where V'DS = VDS +2(Vbl +V2-V,)± 2 ^is 1 / (6) (7) where Vds is the drain-source voltage, ybi=VTn(Ns-DNA/ ni2) is the built-in potential. The back-gate surface potential yS2 is given: qNAtSiLeJf (8) The silicon body capacitance with short channel effects (VDT) taken into account is therefore: Cbj — dQ qNjSiLeJ (9) As the subthreshold slope is defined in the regime before the onset of the strong inversion, the silicon body capacitance C*si,d will be evaluated for the front gate surface potential: (10) where yb=V1n(NA/ni) is the difference between Fermi level and intrinsic level. 2.3 Subthreshold slope model Using the definition for the subthreshold slope as the gate voltage variation needed for the change of one decade in the drain current /8/ and applying the gate voltage solution (5) and the VDT approximation (6-10), the subthreshold slope follows as: dVe dlog/D V ' q d¥sl = ln(l0> kT_ 1 1 + ?r* c Si,d Ri - ji,C BOX Cqox (Çst.cl +2Cj box)j (11) The complex influence of the VFD SONFET parameters are combined in a simple form of (11) with second term in the bracket being responsible for the difference from the ideal S value of 60 mV/dec at 300 K. The scaling tendencies are clear from the capacitance ratio, where Cgox should be increased and C*si,d and Cbox decreased to approach the ideal value. 3 Calculation and simulation results In order to verify the accuracy of the analytical model for the subthreshold slope, the calculated results are compared to a two-dimensional numerical device simulator, MEDICI /9/. Concentration dependent model for the low-field carrier mobility and the velocity saturation mobility model at high parallel electric field were used. Band-gap narrowing in silicon and polysilicon, Shockley-Read-Hall recombination and Auger recombination are taken into account. The gate current was modeled by the Lucky-electron gate current model and the simulation temperature was 300 K. The simulator does not include quantum effects. Focus of this paper is the device subthreshold characteristics where the quantum effects are less pronounced and the drift-diffusion model can be considered accurate. The calculated and simulated subthreshold slope values plotted against effective channel-lengths Leff are shown in Fig. 4. for different: (a) gate oxide thickness tGox, (b) gate dielectric kGox, (c) BOX dielectric kBox, and (d) BOX thickness tBox. The examined devices take advantage of the fully-depleted structure and have an effectively undoped channel for higher mobility. The range of effective channel-lengths investigated was between 288 nm - long channel case, and 22 nm - very short-channel. The simulated structures in each plot varied only in the effective channel-length with other dimensions and technological parameters kept the same. For the effective channel lengths down to 100 nm, subthreshold values are close to ideal values of approximately 60 mV/dec. Agreements between the values obtained by the numerical simulations and analytical model are within 2 mV/dec (3%) for the channel lengths down to 50 nm. For shorter channel lengths (<50 nm) the deviation of our model is mainly due to the rough VDT approximation of the effective doping in channel area N*a and thus the calculation of the silicon body capacitance C*si,d. As the channel length is reduced the influence of the last term in relation (11) becomes higher and more accurate modeling of C*si,d is necessarry. The subthreshold slope can be improved by increasing the value of the gate oxide capacitance Cgox, or by decreasing the value of the buried oxide capacitance Cbox. If the gate oxide thickness tGox is scaled down /Fig. 4. (a)/ or the material with higher dielectric constant kGox is used for the gate oxide /Fig. 4. (b)/ the characteristics show expected improvements. The case of material with the lower dielectric constant kBox used for the buried oxide /Fig. 4. (c)/ also improves the subthreshold slope, as well as thinner buried oxide thickness tBox /Fig. 4. (d)/. 4 Conclusions The subthreshold slope model extracted from the compact capacitance model of the VFD SONFET has been demonstrated. It has been shown that the developed model has high accuracy for channel lengths down to 50 nm and can be extended even further with improvement of the voltage-doping transformation, which is used to account for short-channel effects. With the simple processing of the VFD SONFET, devices with very short gates can be fabricated and the presented model used for the prediction of the subthreshold behavior. The specific, two-dimensional 3 informacije MiDEM 38(2008)1, str. 1-4 B. Svilicic, V. Jovanovic, T. Suligoj: Vertical Silicon-on-nothing Fet: Subthreshold Slope Calculation Using Compact Capacitance Model 150 100- 50 t 0 ox = 2.5 nm in20 5 10 cm T - 300 K t = mn Nj= 10 cm N = 10J° cm'3 t BOX = 60 mil K BOX = 3.9 V =50 mV DZ ■ ■ Medici Kaox= 3.9 -Model Kao= 3.9 + Medici K = 7.4 G OX ---Model 7.4 ♦ ■ - 0 50 100 150 200 250 300 Effective Channel Length [nrn] (b) 100 Na = 10 cm Mj = 10" cm5 Ns¡¡ = 102° cm3 7= 300 K Medici ^=35 ■Model^SJ 50 100 150 200 250 300 Effective Channel Length [mn] (c) ID & 100 - t = 5 nm N = 10 cm A Vn= 50 mV N = 10 cm G N =10" cm ' i-ii 7 =300 K ■ Medici t = 200 11111 SOX - Model Íj0jr= 200 mil ♦ Medici t = 20 uni SOX - - Model t =20 11111 çg 0 50 100 150 200 250 300 Effective Channel Length [nm] (d) Fig. 4. Comparison of subthreshold slope values against effective channel lengths obtained by MEDICI simulations and analytical model for different: (a) tGox. (b) kGox (c) keox, (d) tBox. K=k/so. characteristics of the VFD SONFET structure are accurately described in the model and combined in a simple relation for the subthreshold slope. This offers clear insight into influences of different parts of the structure and can be used to estimate the performance of scaled devices. ACKNOWLEDGMENTS The authors would like to thank Petar Biljanovic for support and suggestions. This work was supported in part by the Croatian Ministry of Science, Education and Sports (scientific projects 036-0982904-1642 and 036 -0361566 - 1567). REFERENCES /1/ /2/ /3/ /4/ /5/ /6/ /7/ /8/ /9/ B. Svilicic, A. Kras, "CMOS Technology: Challenges for Future Development", Journal Pomorstvo, November 2006. M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J. L. Regolini, D. Dutartre, P. Ribot, D. Lenoble, R. Pantel, S. Mon-fray, "Silicon-on-Nothing (SON) - an Innovative Process for Advanced CMOS", IEEE Trans. on Electron Devices, vol. 47, p. 2179, 2000. P. E. Thompson, G. Jernigan, J. Schulze, I. Eisele, T. Suligoj, "Vertical SiGe-based Silicon-on-Nothing (SON) technology for sub-30nm MOS devices", Materials Science in Semiconductor Processing 8, pp. 51 -57, 2005. I. Radinkovic, V. Jovanovic, T. Suligoj, J. Schulze, I. Eisele, G. Jernigan, and P.E. Thompson, "Scaling Properties of Vertical Silicon-on-Nothing (SON) MOSFETs", MIPRO, 2004. V. Jovanovic, T. Suligoj, J. Schulze, I. Eisele, G. Jernigan, and P.E. Thompson, "Characteristics of 30 nm Long Vertical Silicon-on-Nothing (SON) MOSFET", MIPRO, 2005. B. Svilicic, V. Jovanovic, T. Suligoj, "Vertical Silicon-on-Nothing FET: Capacitance-Voltage Compact Modeling", MIPRO, 2007. T. Skotnicki, G. Merckel, T. Pedron, "The Voltage-Doping Transformation: A New Approach to the Modeling of MOSFET Short-Channel Effects", IEEE Trans. Electron Devices, vol. 9, no. 3, pp. 109-112, March 1988. B. Svilicic, V. Jovanovic, T. Suligoj, "Vertical Silicon-on-Nothing FET: Analytical Model of Subthreshold Slope", MIDEM 2007, 2007. Synopsys, Inc., Taurus Medici, Two-Dimensional Device Simulation Program, Version X-2005.10-0, 2005. B. Svilicic, Faculty of Maritime Studies, University of Rijeka, Studentska ulica 2, 51000 Rijeka, Croatia Phone: +385 (0)51 338 411, Fax: +385 (0)51 336 755, E mail: svilicic@pfri.hr V. Jovanovic, ECTM-DIMES, Delft University of Technology, The Netherlands T. Suligoj Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia Prispelo (Arrived): 09.10.2007 Sprejeto (Accepted): 28.03.2008 4 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana TWO-DIMENSIONAL OPTICAL MODEL FOR SIMULATING PERIODIC OPTICAL STRUCTURES IN THIN-FILM SOLAR CELLS Andrej Čampa, Janez Krč and Marko Topič University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Key words: optical modelling, thin-film solar cells, periodic structures, light management Abstract: Novel optical concepts based on periodic structures such as diffractive gratings are important for thin-film solar cells since they exhibit high potential of light management. In order to simulate and optimize the periodic structures different approach is needed in comparison to widely used one-dimensional approaches. In this paper a two-dimensional finite element numerical approach is described to solve the Maxwell's differential equations of the propagating light in thin-film structures. The different boundary conditions that can be applied at the borders of the simulation domain are presented. The concepts how to efficiently solve the system and how to obtain the final optical parameters of the solar cells - reflectance, absorptances in the layers, charge carriers generation rates - are described. The model is verified with the measurements of the total reflectance at realistic diffractive gratings. Simulation results of a complete amorphous silicon solar cell with the diffractive gratings are presented. Dvo-dimenzionalni optični model za simulacijo periodičnih optičnih struktur v tankoplastnih sončnih celicah Kjučne besede: optično modeliranje, tankoplastne sončne celice, periodične strukture, vodenje svetlobe Izvleček: Novi optični pristopi osnovani na periodičnih strukturah, kot so uklonske mrežice, so v tankoplastnih sončnih celicah pomembni, saj izkazujejo velik potencial pri vodenju svetlobe v strukturi. Za simulacijo periodičnih struktur ne zadostuje samo uporaba klasičnih eno-dimenzionalnih pristopov pač pa se moramo poslužiti dvo-dimenzionalnih simulacij. V prispevku je predstavljen dvo-dimenzionalen simulator, ki temelji na reševanju valovne Maxwellove enačbe širjenja svetlobe znotraj sončne celice na podlagi metode končnih elementov. Opisani so različni robni pogoji, ki jih uporabimo v simulacijah za zaključitev računskega območja. Podani so načini, kako določiti izhodne optične parametre simuliranih sončnih celic (odbojnost, absorpcija svetlobe v plasteh, profili generacij prostih nosilcev naboja). Rezultati simulacij so ovrednoteni s primerjavo izmerjenih odbojnosti izdelane uklonske mrežice. Na koncu so prikazani rezultati optične simulacije celotne tankoplastne amorfno-silicijev sončne celice. 1. Introduction In thin-film (TF) solar cells light trapping is of great importance, since absorber layers are very thin (from one hundred nanometers to few micrometers). To capture light inside the absorber layer efficiently the scattering of light at internal interfaces is needed. In this way light paths throughout the layers are prolonged and the number of light passes increased due to enhanced back reflectances at internal interfaces. In current state-of-the-art silicon TF solar cells randomly textured substrates are used to introduce interface texture in the cell structures /1-3/. However, to further improve and use the potential of light scattering process, new approaches of light management are becoming important. One of them are periodic structures, such as diffractive gratings, which can be applied to the interfaces to efficiently scatter light only into specific, but very large angles /4/. Large angles can consequently lead to a significant increase of the light paths and to the total internal reflectance of the scattered light rays at the front interfaces of the solar cell structures. The integration of diffractive gratings in thin-film solar cell structures have already been investigated experimentally /5, 6/ and by numerical simulations /7-10/. The results of current structures of solar cells, including the gratings, indicate that the potential of the diffractive gratings has not been exploited fully. Thus, further investigations of diffractive gratings and especially of their integration and optimization in the TF solar cell structures is of great importance. Numerical modelling and simulation present here an important tool. To analyse optical situation at the grating, implemented in the structure of thin-film solar cells, at least a two dimensional simulator is needed. Some two- or three- dimensional (2-D, 3-D) simulators for the analysis of the diffractive gratings in the solar cells have already been reported e.g. /7-10/. However, the simulators have certain drawbacks, since they are mostly developed for general usage in the field of electromagnetic wave propagation and are not adapted and optimized to the specific structures, such as TF solar cells. One of the drawbacks is, for example, that is difficulty to simulate not-rectangular shapes of the grating features (triangles, sine shape etc.). The slopes of the different shapes are usually roughly approximated by rectangular steps, which can not give good representative results especially if only a few steps are used for approximation. Sharp edges of even small rectangles can affect the simulation results noticeably. Another drawback is that the output results are not the quantities that are important for TF solar cells (like optical reflectance, R, absorptance, A, charge carrier generation rate, Gl). 5 Informacije MIDEM 38(2008)1, str. 5-10 A. Campa, J. Krc, M. Topic: Two-dimensional Optical Model for Simulating Periodic Optical Structures in Thin-film Solar Cells In this paper we present our 2-D optical simulator which has been developed for the analysis of TF solar cell structures including diffractive gratings and other periodic structures. The model is based on the finite element numerical method (FEM) /11/. One of the specialities of the model is that the simulation domain is represented by triangular elements rather than rectangular. These way different shapes can be more easily and effectively described. The details of the model and other advantages of the simulator, based on the model are presented. The boundary conditions that can be applied at the borders of the simulation domain are described. The determination of the electric and magnetic field distribution in the structure will be explained. The methods to calculate standard optical quantities used in the field of photovoltaics, such as R, A, Gl will be presented. Mathematical methods and techniques how to manipulate large data matrix and how to calculate out the desired results are briefly described. The verification results of the simulator and the simulations of the complete amorphous silicon solar cell are presented. cate the directional component of the vectors. In Eqs. 2 it is considered that the electromagnetic wave is transversal (electric and magnetic field vectors perpendicular to each other) /11/. The wave is divided into the transverse Electric (TE) and transverse magnetic (TM) wave. In the case of TE wave, the wave is entirely represented by electric field component in z axis, Ez, whereas in the case of TM wave, the wave is entirely represented by the magnetic field in the z axis, Hz. Since the incident light consists both components of polarization (TE and TM), both equations included in Eq. 2 need to be considered. The geometry of the periodic structure was described by choosing the triangular elements as basic building elements of mesh (Fig. 1a and 1b). Eqs. 2 have to be solved for each element in the mesh-grid, where we assume that the properties of material (Ur and £r) are constant within the element. The alignment of the triangular elements in the grid is shown in Fig. 1c. All the elements are of the same size. 2. Optical model 2.1 Electromagnetic background The optical model is based on Maxwell's wave equations in the frequency domain (Eqs. 1). 1 ■> Vx(—VxE)-co eE = -j'coJ Vx(-VxH)-ra2|iH = Vx(-J) Eqs 1 e e where E and H are the complex vectors of the electric and magnetic field of propagating waves, u = UUo = (URe -jUIm)U0 and e = Er So = (SRe- jSIm) S0 are the complex permeability and the complex permittivity of the material (uo = 4nx10-7 H/m, So = 8.854x 10-12 F/m), c is the angular frequency and J is the complex vector of the current density. In a 2-D space problem it is assumed that the field components (E and H) and media (Ur, Er) do not change in the third dimension (axis z in our case). Thus, the Eqs. 1 can be written in the form of differential equations for two dimensions as given in Eqs. 2. dx |Xr dx dy \Lr dy - jk0Z0J2 - TEwave —(--) + —(--) + K\ir dx Er dx dy Er dy E = H = a, 1 _, a, 1 _, = -—(— J ) + — (— Jx)- TM wave dx Er dy Er Eqs 2 where x and y are the spatial directions (x - lateral, y -vertical), ko is the wavenumber in vacuum and is defined as cd-^EoM-o , Zo is the impedance of vacuum (Z0 = ^n.0/e0). The subscripts of the field and current components indi- a) Fig. I.- Basic elements used in our optical model: a) triangular element for linear approximation of unknown function (field), b) triangular elements for quadratic approximation of unknown function and c) discretization of simulation domain with triangular elements (with either linear or quadratic approximation). For each triangular element the unknown function 0 (representing Ez or Hz) at the position of the element has to be determined along the three borders of the element. In our simulator we have implemented two options: a) linear approximation (Fig. 1a, Eq. 3) and b) quadratic approximation (Fig. 1b, Eq. 4) of the unknown function along the borders of the element. §e(x,y) = ae +bex + cey tye(x,y) = ae +bex + cey + dex2 + eexy + fey2 Eq. 3 Eq. 4 In Eq. 3 and 4, x and y are the 2-D spatial directions (see Fig. 1), where the superscript e indicates that the approximation is related to one-element level. The symbols a-f are the constants that have to be determined in the calculation process. In the case of linear approximation the function 0 is determined for the three nodes presenting the corners of the triangle (Fig. 1a). In the case of the quadratic approximation at each border line of the element an additional node is added, resulting in six calculation nodes 6 A. Čampa, J. Krč, M. Topič: Two-dimensional Optical Model for Simulating Periodic Optical Structures in Thin-film Solar Cells Informacije MIDEM 38(2008)1, str. 5-10 Fig. 2: Different boundary conditions for different configurations of simulation domain: a) periodic symmetric configuration, b) general periodic configuration and c) open region configuration - bounded system. (Fig. 1b). The use of quadratic approximation has found to be useful when the abrupt changes in the field or spikes in the field are expected. 2.2 Boundary conditions Determination of the size of the simulation domain and application of the mesh-grid to our periodic structure are crucial steps, which are both related to the boundary conditions applied to the borders of simulation domain. Typically the structures are periodically repeated (infinitely) in lateral direction in our case. Two different types of boundary conditions applicable to the problem will be explained here. One type is related to the periodicity and lateral symmetry (left and right border according to examples in Fig. 2), whereas the other one is related to the incident (radiated) and outgoing field (top and bottom border of the simulation domain). In the case of first type of boundary conditions (left, right border), application of three different boundary conditions is illustrated in Fig. 2a, 2b. In Fig. 2a the example of the application of the homogeneous Neumann condition /11/ is shown. In this case the first derivative of the field at the left and right border is zero (the divergence of field is zero). According to the figure this condition enables that only half of the period (P/2) is included in the simulation domain. Next, taking the whole period of the structure in the simulation domain (Fig. 2b) the field at the left and the right borders should be set to the equal values (virtually connected boundary system). The reason is the periodicity of the structure acquired in the simulation domain. Therefore, this condition is assigned to the periodic boundary condition /11/. The third condition which can be applied to the left and right border is absorbing boundary condition (ABC, Fig. 1c) /11/. This case is assigned to an open-region configuration in the lateral direction (structure with limited lateral dimensions, the whole structure is included in the simulation domain). An ideal boundary condition here would be zero reflectivity of waves at the borders. To approach this ideal case different orders of the ABC conditions can be used /11/. For the second type of the boundary conditions (top, bottom border of the simulation domain) the above mentioned ABC condition is applied at the top and bottom border in all the cases. In Fig. 2a and Fig. 2b for the illumination source the perpendicular plane wave is used, in Fig. 2c, a laterally limited illumination is applied (e.g. Gaussian beam). This enables us to simulate also the laterally limited non-periodic structures with limited area of light illumination. In Figs. 2 the structures consists of only one layer (the diffractive grating below) and the incident medium above. However, in the model more layers (e.g. complete solar cell structures) can be applied with different type of the interface morphology. The vertical and lateral geometry are described with optical properties (e and ¡) for each node in the mesh-grid. 2.3 Solving the system To solve the differential equations (Eqs. 2) for each node of the element the Ritz method is applied /11/. Boundary conditions, linear or quadratic approximation of 3, illumination source (plane wave or Gaussian beam) are considered. In the Ritz method the differential equations are transformed in the mathematical functional. Finding solutions for 3 at each node is based on minimising the functional / 11/. As a final result of the Ritz method the following matrix description is obtained (Eq. 5) KO=b Eq. 5 where K is the matrix of the system coefficients (the size of N x N; N - number of all nodes in the simulation domain), 3 is the vector (the size of N) of the system unknowns (E or H) and b is the vector (the size of N) of the light sources (different than zero only at the nodes at the top border, where the incident field is applied). The matrix K is sparse, symmetric, with complex numbers and it is not positive-definite. Its elements consist information of the material properties (e and ¡i) at the nodes. It has to be noted that N in our case can even be more than a million, depending on the problem. Due to the large 7 Informacije MIDEM 38(2008)1, str. 5-10 A. Campa, J. Krc, M. Topic: Two-dimensional Optical Model for Simulating Periodic Optical Structures in Thin-film Solar Cells size of the matrix K (Nx N) the memory consumption in the computer program can become a problem, especially if the direct methods for solving (e.g. Gauss elimination, LU decomposition /12/) are used, due to generation of new non-zero elements. To solve such a system, iterative methods are recommended /12, 13/. We found out that in our case the solution can be efficiently obtained by using non-stationary gradient iterative methods: the special form of Conjugate Gradient (CG) method /11/, Bi-Conjugate Gradient (Bi-CG) and Quasi-minimal residual (QMR) method / 12/. The CG method was found to be slow, but relatively stable, however the Bi-CG and QMR were found to be fast but less stable. In order to improve the condition of matrix and also to stabilize the method different preconditions were implemented into CG, QMR and Bi-CG algorithms. The easiest precondition used was the Jacobian precondition /13/, leading to a good convergence. However, in some special cases with the Bi-CG method we could still obtain divergence of the method, especially when the sharp metal structures were simulated, where the high spikes in the field might occur. In order to stabilize the method we have implemented the Symmetric Successive Over-Relaxation (SSOR) precondition /13/. The simulations with the SSOR precondition needed less iterations to obtain the result compared to Jacobian precondition. The very large sparse system needed to be efficiently solved in the fastest time as possible and also with using very low memory consumption. Special attention has to be paid on the description of sparse matrixes in order to fasten the computation time when calculating the product of the sparse matrices with vectors in the calculation procedure, since these products have been found as the most time consuming. Another simplification considering the solving of system is to use mesh-grid consisted of the elements of the same size and of same orientation in the grid (pre-defined regular grid, Fig 1c). This way we do not need additional large matrix to describe the mesh. 2.4 Determination of the output parameters of the simulation After the field Ez or Hz has been obtained at each node, the calculation of the final output parameters is performed. In our optical analysis, optoelectronic structures like thin-film solar cells are investigated. The following parameters are defined as the main output parameters: the total reflectance from the structure, Rtot, the absorptance inside individual layers of the structure, Aayer, and the 2-D generation rate across the structure, Gl, of the photo generated electrons and holes in the active layers. The Rtot of the structure is calculated at the top border, where also the incident wave is generated. The basis for the Rtot calculation presents the Poynting vector S = (E x H*)/2 ("*" presents the conjugated value). By considering only its normal direction (y axis) the Rtot can be determined as Rtot = Sy_refl / Sy_inc, where the subscripts "refl" and "inc" correspond to the reflected and the incident component of the Poynting vector. These two components can be obtained from the calculated total and known incident field values at the top border (E refl = Etot - Einc , H refl = Htot -Hinc). This results in the final equation for Rtot (Eq. 6): KATE) = KATM) = Im £ cly Re( m HincH-) £ Eq. 6 Absorption inside the single element in the layer Af and inside entire layer A, can be calculated as (Eq. 7), which is derived from Poynting's theorem. 4 = <^HH.+ J^EE* Eq. 7 where ^ and & are imaginary parts of permeability and permittivity corresponding to the element. To obtain absorption of a layer one has to sum up all the absorptions of the elements which are composing specific layer. Generation rate profile is calculated from the local absorption (absorption of the elements) and is given by Eq. 8 for one element e. Gim = Eq. 8 he dxdy 2 where h is Planck constant, c is speed of light and /inc is illumination power density. 3. Verification results and simulations of the solar cells Based on the presented optical model a computer simulator FEMOS-2D was developed. A user friendly interface enables simple simulation of the multilayer structures, including diffractive gratings, in the entire solar spectrum. The results of simulations were verified by comparing them to the measurements obtained on realistic samples. In Fig. 3 the structure of one of the samples as well as the Atomic Force Microscopy (AFM) scan of its surface is shown. On the polycarbonate substrate, which is typically used for CDs, DVDs or BDs, the periodic grating structure was embossed with the periodicity of P = 700 nm. On the top of the polycarbonate substrate 100 nm thick layer of an aluminium alloy was deposited. By means of AFM the shape of the grating surface was determined. In our case the sine shape was used in simulator to describe the grating shape with the height of h = 40 nm as determined from the AFM measurements. The sine shape agrees with the measured AFM profile very well, however, realistic shape of the profile can be imported in our simulator. The other input pa- 8 A. Čampa, J. Krč, M. Topič: Two-dimensional Optical Model for Simulating Periodic Optical Structures in Thin-film Solar Cells Informacije MIDEM 38(2008)1, str. 5-10 rameters for simulation were realistic wavelength dependent refractive indices of the layers and polarization of light. In simulations we used un-polarized light, 50 % of TE and 50 % of TM polarization, approaching to the realistic illumination in our measurement. In Fig. 4 the measurements and simulation of the Rtot of the grating as a function of light wavelength is shown. All measurements of Rtot were done with Lambda950 spectrophotometer from which unpolarized monochromatic light in the range from 400 to 1000 nm was obtained. 1.0 100 nm of Aluminium / h Polycarbonate / Î Fig. 3: Analysed grating structure with thin film aluminium layer (100 nm) on the top of the polycarbonate substrate. On the right the AFM measurement of the left structure is presented. Good agreement is observed between the measured (dashed curve) and simulated (full curve) Rtot of the grating structure. For comparison also the simulation of the flat structure is shown (dash-dot curve). In this relatively simple structure the effect of the grating is related to the decreasing spike at the wavelength of 700 nm. This spike is due to additional absorption in aluminium alloy at the grating structure in the mentioned wavelength region. In this wavelength region the anti-reflective effect and light scattering in the first diffraction order /4/ occur. In the simulation and measurement (not shown in the figure) of the flat structure no spike is observed. In the next step we simulated the whole thin-film amorphous silicon solar cell deposited on the 2-D grating (substrate configuration). The structure of the cell is as follows: Al/n-a-Si:H(20 nm) / i-a-Si:H(200 nm) / p-a-Si:H(10 nm) / Zn0:Al(500 nm) on the top (see insert in Fig. 5). At all interfaces the sine shape of gratings was used, with the height of 150 nm and with two different periods (300 and 400nm). The wavelength dependent refractive indices, N(k) S Ol 0.7 0.6 - Measurement - grating structure ---Simulation 2D - grating structure - - Simulation 1D - flat structure 400 500 600 700 800 wavelength, X [nm] 900 1000 Fig. 4: Measured and simulated total reflectance of the aluminium grating structure with P=700 nm and h = 40 nm showing in Fig. 3. of the realistic layers were used to determine the s(k) of the materials needed in the simulation. In Fig. 5 the simulated absorptance in the i-a-Si:H layer of the solar cell is plotted for selected grating parameters. The grating should act as an efficient scatterer in the cell, leading to enhanced absorptance in the i-a-Si:H layer. Higher absorptance in the mentioned active layer leads to a higher short-circuit current and quantum efficiency of the solar cell. The 2-D simulations reveal the increase in absorptance is partly due to antireflective effect of the textured front interfaces and partly due to scattering effect of gratings at the interfaces. The simulations showed that by changing the period of the grating (in Fig. 5 shown for the case of P = 300 nm and 400 nm) in this case it is affecting the position of the interferences in the absorptance curve. The presented simulator enables the direct study of the relation between the (periodic) surface morphology and light scattering. This is a very important point in the simulations of photovoltaic devices with textured interfaces (most of them), where the optical situation inside the structure cannot be measured, thus, simulations are needed to optimize the structures. This way the direction towards the optimal texturing can be indicated. Extending the simulator to the randomly textured interfaces it can be used to evaluate and select different TCO substrates from the light scattering point of view. However, analysis of the regularly textured interfaces (such as gratings) can already give useful information about improvements of randomly textured interfaces. Further on, special optical effects in the solar cell structure can be investigated with the simulator, such as plasmon absorption at textured metal back contacts. Minimizing the optical losses in metal, related to this absorption, by possibly optimizing the texture shapes is one of the important issues, other advantage of our simulator is also that it is highly customized for a solar cell application, but can be also used for other EM problem. 9 A. Čampa, J. Krč, M. Topič: Two-dimensional Optical Model for Informacije MIDEM 38(2008)1, str. 5-10 Simulating Periodic Optical Structures in Thin-film Solar Cells Fig. 5: Simulated absorptance of the i-a-Si:H layer in the complete amorphous silicon solar cell structure with the sine grating applied to all interfaces. 4. Conclusions Two-dimensional optical model for solving electromagnetic wave equations at periodical structures - diffractive gratings - was presented. The model is based on robust FEM method and solves differential equation for both (TE and TM) polarizations. Special attention was paid on boundary conditions and how to effectively solve the system discre-tized differential equations. This way we were able to obtain accurate results of simulation in the shortest time. One of the main advantages of the optical model is simulation of arbitrary (periodic) interfaces shapes, where a good approximation of the interface texture can be achieved by using triangular elements instead of rectangular. The simulator based on the developed model is especially dedicated to simulation of optoelectronic structures such as thin-film solar cells. It automatically calculates the main optical output parameters from the field, such as absorption in individual layer of the structure, total reflectance and 2-D generation rate profile at each discrete element. The simulator is optimised for speed of the calculation and for low memory consumption to allow large number of discretization points. Simulation results of Al based grating structure with the period of 700 nm is compared with the measured total reflectance of the sample. Good agreement is observed, indicating the validity of the simulations. The result of optical simulation of a complete amorphous silicon solar cell with different periods of the incorporated grating is presented. The developed optical simulator presents a powerful tool for further investigation of light management in thin-film solar cell with the diffractive gratings and other textures. 5. Acknowledgement The authors thank Miro Zeman from DIMES institute, Delft University of Technology, Netherlands for providing the grating sample and for useful discussions on optical modeling and OM&T B.V., Netherlands for providing polycarbonate substrates. References: /1/ Mueller et al., Solar Energy 77, 2004, p. 917 /2/ Fa' et al., Proceedings of EU PVSEC, Glasgow, 2000, p. 361 /3/ Kambe et al., Proceedings of WCPEC-3, Osaka, 2003, p. 1812 /4/ C. Heine, R. H. Morf, Applied Optics 34, 1995, p. 2476 /5/ S. H. Zaidi, J. M. Gee, D. S. Ruby, Diffraction grating structures in solar cells, IEEE, 2000, pp. 395-398 /6/ N. Senoussaoui, M. Krause, J. Müller, E. Bunte, T. Brammer, H. Stiebig, Thin Solid Film 451-452, 2004, p. 397 /7/ M. Niggemann, B. Bläsi, A. Gombert, A. Hinsch. H. Hoppe, P. Lalanne, D. Meisnner, V. Wittwer, 17th European Photovoltaic Solar Energy Conference Proceedings, 2002, p. 284 /8/ C. Haase, H. Stiebig, Prog. Photovolt: Res. Appl. 14, 2006, p. 629 /9/ R. H. Morf, J. Opt. Soc. Am. A 12, 1995, p. 1043 /10/ C. Haase, D. Knipp, H. Stiebig, Proceedings of the 22nd EU PVSEC, Milano, 2007, p. 2186 /11/ J. Jin, The Finite Element Method in Electromagnetics, 2nd edition, John Wiley & Sons, New York, 2002 /12/ R. Barrett, et al., Templates for the Solution of Linear Systems, 2nd Edition, SIAM, Philadelphia, 1994 /13/ Y. Saad, Iterative Methods for Sparse Linear Systems, 2nd Edition, SIAM, Philadelphia, 2003 Andrej Čampa, univ. dipl. inž. el. Asst. Prof.. Dr. Janez Krč, univ. dipl. inž. el. Prof. Dr. Marko Topič, univ. dipl. inž. el. University of Ljubljana, Faculty of Electrical Engineering, Laboratory of Photovoltaics and Optoelectronics, Tržaška cesta 25, SI-1000 Ljubljana, Slovenia E-mail: andrej.campa@fe.uni-lj.si Prispelo (Arrived): 04.02.2008 Sprejeto (Accepted): 28.03.2008 10 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana SMD FILM CAPACITORS FOR INTEGRATING A/D CONVERTERS Andrej Levstek, Matija Pirc Faculty of Electrical Engineering, University of Ljubljana, Ljubljana, Slovenia Key words: integrating A/D converter, SMD film capacitor, dielectric absorption, humidity, surface resistance, polymer dielectric Abstract: Lead free technology has significantly influenced the choice of commercially available capacitors, especially those intended for surface mount. A case study of the appropriate SMD capacitor selection for a high accuracy integrating A/D converter is presented. The converter is part of a smart sensor that encompasses a simple microcontroller and an analog transducer, which is in this case a platinum resistor. An overview of traditional and new polymer dielectric materials is given with the emphasis on the commercial selection of SMD capacitors. Trends of the film capacitor industry in the recent years are explained through the physical properties of the materials used and the imposed legislative restrictions. The often overlooked pitfalls of capacitor selection are sequentially described. The effect of the dielectric absorption of the charge on the conversion error is theoretically analyzed for the intermittent mode of operation. Inaccuracy due to the recovery of the absorbed charge is eliminated by the use of a polyphenylene sulfide (PPS) film capacitor; however, at high humidity some capacitive sensors exhibit abnormal deviations. Based on some additional experiments, we determine the influence of the capacitor's parallel resistance on the conversion result. The synergic impact of high humidity, temperature, and flux residues on the surface resistance of stacked capacitors is proven by experimental measurements carried out in a climatic chamber. The experimental measurements of SMD capacitor insulation resistance show that naked stacked capacitor construction is not suitable for relative humidity above 80%. In such cases, slightly larger encapsulated SMD capacitors must be used to maintain the desired high accuracy. SMD filmski kondenzatorji za integracijske A/D pretvornike Kjučne besede: integracijski A/D pretvornik, folijski SMD kondenzator, dielektrična absorpcija, površinska upornost, polimerni dielektrik Izvleček: Prepoved uporabe svinca v tehnologiji izdelave tiskanih vezij je pomembno vplivala na tržno ponudbo kondenzatorjev, namenjenih za površinsko montažo. V prispevku je podan potek izbire ustreznega kondenzatorja za integracijski A/D pretvornik z visoko ločljivostjo. Sam D/A pretvornik je del inteligentnega senzorja, ki ga sestavlja mikrokrmilnik in ustrezen analogni merilni pretvornik, v opisanem primeru je to platinski upor. V delu je najprej podan pregled polimernih dielektrikov s poudarkom na njihovi rabi za SMD komponente. Trendi zadnjih let v industriji kondenzatorjev za elektroniko, so opisani s stališča fizikalnih lastnosti dielektričnih filmov in prepovedi rabe svinca v elektronskih napravah. Spregledane pomanjkljivosti izbranega tipa, so podane zaporedno, kot so se pojavljale pri razvoju. Izpeljali smo analitično zvezo med dielektrično absorpcijo kondenzatorja in pogreškom posamične pretvorbe. Merilno napako zaradi sproščanja absorbiranega naboja v času pretvorbe, smo odpravili z uporabo polifenil sulfidnega (PPS) kondenzatorja. Z eksperimenti v klimatski komori smo ugotovili, da imajo nekatera vezja nenormalno velika odstopanja, ki nastanejo zaradi vpliva vlage na gole PPS kondenzatorje. Izpeljali smo analitično zvezo med velikostjo skupne upornosti med sponkama kondenzatorja in merilno napako. Ugotovili smo sinergični vpliv vlage, temperature in ostankov fluksa na površinsko upornost nezaščitenih kondenzatorjev, ki so izdelani z zlaganjem metaliziranega filma. Meritve izolacijske upornosti so pokazale, da takšni kondenzatorji niso primerni za vlažnosti zraka nad 80 %. Za precizni integrator so primernejši dimenzijsko nekoliko večji SMD kondenzatorji v plastičnem ohišju. 1. Introduction Electronic integrators offer a simple solution for achieving an accurate A/D conversion of low voltage levels whenever the speed of conversion doesn't play a significant role. Dual slope integrating A/D converters can be implemented by low cost digital microcontroller and a simple additional analog circuit. Such A/D converters can be used for accurate conversion voltages that are proportional to slowly varying physical quantities like temperature or atmospheric humidity. Conversion errors due to the non-idealities of the analog components, i.e., the input offset voltage of the operational amplifier (opamp), are minimized by a simple solution, so that low-cost analog components can be used. The choice of utilized capacitor seems unimportant since the value of capacitance does not appear in the conversion equations at all/1/. Such an approach is over-simplified but this fact does not become obvious until experimental measurements of prototypes under various climat- ic conditions are performed. The physical dimensions of electronic circuits are steadily decreasing, which is a consequence of the growing demand for hand-held devices. The introduction of surface-mount technology (SMT), which became widely used around the year 1990, engendered important changes in the field of high performance metallized film capacitors. The small size of SMD capacitors has raised many problems in their construction, because of the intense heat transfer from the metallized soldering pads to the plastic dielectric film during the reflow soldering process. The first widely used SMD capacitors were multilayer ceramic chips (MLCC). This construction and the high relative dielectric constant of the ceramics result in such capacitors having a high capacitance packing density and relatively low equivalent serial resistance (ESR). The inorganic nature of the dielectric used in MLCCs minimizes the impact of the thermal stress during soldering. Polymer film capacitors are much more affected by the raised tem- 11 Informacije MIDEM 38(2008)1, str. 11-19 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters perature levels because of the thermoplastic nature of the dielectric film. The choice of SMD polymer film capacitors on the electronic components market is predominated by trough-hole film types and by ceramic SMD chips. As a consequence, film capacitors are rather expensive, therefore cheaper alternatives are used wherever it is possible. In the next chapter an overview of the important polymer dielectric materials is given, followed by a case study of the capacitor selection for an integrating A/D converter. Finally, the results of practical experiments are presented. The comments on the outcomes and some practical hints for the selection of appropriate SMD polymer film capacitors conclude the paper. 2. Materials for film capacitors The traditionally used plastic materials for dielectric films in capacitors are polystyrene (PS), polyester (PE), polycarbonate (PC) and polypropylene (PP). These materials are used for film capacitors with low loss and stable capacitance in the range from 1 nF up to 10 mF. Film capacitors below 1 nF are offered only by a small number of producers; and especially SMD types are very rare. The range of capacitances below 100 pF is almost exclusively covered by C0G ceramic capacitors, which are featured with a low capacitance temperature coefficient aC and the dissipation factor tand . 2.1 Polystyrene capacitors For years, polystyrene (PS) capacitors were the best choice for critical analog applications. In the middle of the 1990s the production of PS capacitors slowly ceased. There were several reasons that caused polystyrene capacitors to disappear from production. The maximal operating temperature of PS film and capacitors is very low, only 85°C (see Table 2). Additionally, the low heat resistance of PS film allows neither the construction of SMD components nor the vacuum-deposition of aluminum, hence only film/foil capacitors were (are) produced. This construction lacks the self-healing capability, i.e., the ability to clear faults (such as pores or impurities in the film) under the influence of voltage. Although PS capacitors have low absorption of moisture, they can be easily damaged by printed board cleaning solvents. PS capacitors that are still available from old stocks are not intended for new designs. New materials like polyphenylene sulfide (PPS) should be used instead of PS. 2.2 Polycarbonate capacitors Polycarbonate (PC) metallized film and film/foil capacitors were traditionally the logical choice in high performance applications for operation at elevated temperatures. This material is featured with a negligible temperature coefficient aC for temperatures in the range of 20°C + 40°C, which is the common operating temperature range of precision electronic equipment. In spite of the higher operat- ing temperatures of this film, commercially available PC capacitors for surface mount were never produced. In the year 2000, the major producer of PC capacitors WIMA from Germany /2/, ceased their production after finding it unprofitable. This decision caused the major producer of capacitor grade PC film, Bayer AG, to stop its production upon completion of the final order. Nevertheless, PC film capacitors are still available and produced at least by Electronic Concepts Inc. from USA with its own in-house produced dielectric film /3/. Polycarbonate film is almost the perfect material for high performance capacitors but is very sensitive to moisture absorption, thus good encapsulation is required to protect the dielectric film against humidity. Hermetically sealed PC capacitors are available only with wired trough-hole terminals and are primarily intended for military applications. 2.3 Polyester capacitors Polyester films have become the standard dielectric for capacitors in electronic applications. Polyester film for capacitors is biaxially oriented polyethylene terephthalate (PET) developed by DuPont in the mid-1950s and is well-known under the trade name Mylar. This material has good mechanical and electrical properties for temperatures in the range from -55°C to +125°C. Their high dielectric strength, and the highest dielectric constant among commercially used dielectric films, make PET capacitors low-cost and volume-effective. Metallized PET film capacitors are produced in any combination of the construction alternatives given in Table 1. Table 1: Manufacturing and construction alternatives of PET capacitors Parameter Alternative Environmental protection Naked Protected Mounting terminals SMD Trough hole Construction Stacked Wound RoHS compliance Yes No These capacitors are the most frequently used type of plastic film capacitors in electronic circuits - primarily for DC or low frequency purposes - because the dissipation factor tand of polyester is the highest among contemporary film materials. Even though it is not a high quality material, in many respects, PET films perform much better than multilayer ceramic capacitors (MLCC) using X7R or Z5U dielectric ceramics. Some producers, e.g., AVX /4/, offer PET-HT capacitors with an improved temperature range of up to +125°C with a nominal voltage derating factor of 1.25 %/°C above Tr = 105°C, which represents an increase of 20°C with respect to the standard types. 12 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters Informacije MIDEM 38(2008)1, str. 11-19 2.4 Polypropylene capacitors Polypropylene (PP) film has, for many years, been used for high performance applications, especially for medium and high power electronic circuits where high impulse current capability is required. This material has very low dielectric absorption DA making a PP capacitor the best choice for the charge-storing device in precision integrators, sample and hold amplifiers and other electronic circuits that retain analog signals in the form of electric charge. Additionally, PP capacitors are characterized by a constant temperature coefficient a = -200 ppm/°C and the second highest volume resistivity among dielectric film materials (Table 2). The main deficiency of PP is its somewhat limited temperature range, which prevents the construction of PP as an SMD component. Standard PP capacitors use metallized film and film/metal foil construction for self-healing and high impulse current capability, respectively. 2.5 Polyphenylene sulfide capacitors Polyphenylene sulfide (PPS), a dielectric material with excellent electrical and thermal properties, was invented by Toray/Japan. This chemical company started the production of capacitor grade PPS film in 1988 under the trade name of Torelina®, and is still the only producer. In the same year PPS capacitors were made commercially available by WIMA/Germany, but their production was plagued with many difficulties. In 2001 WIMA /2/ temporarily ceased their production due to problems connected with inconsistent film quality and availability. A detailed examination of self-healing of different metallized polymer films by Walgenwitz et. al. /5/ has shown only insignificant distinctions among PET, PEN and PPS. In any case, achieving self-healing in PPS film is not a particular problem. The problematic availability of PC capacitors, the European Council Directive on the Restriction of Hazardous Substances (RoHS Directive, 2002/95/EC) /6/, and good mechanical properties of biaxially oriented PPS film at higher temperatures have prompted numerous activities for the reliable production of PPS capacitors. The construction of SMD film capacitors has become very demanding due to the elevated melting point of leadless soldering compounds. After the break in 2000 WIMA restored the production of PPS capacitors, encouraged by a mixture of technological and commercial factors. After 2001 both trough hole and SMD types of PPS metallized capacitors were made generally available by several manufacturers. PPS has excellent electrical properties that exceed PC in many aspects. Almost no sensitivity to humidity and a far higher operating temperature range are the most important attributes of PPS when compared to PC. Despite the advantages of PPS film (expressed by the figures in Table 2), this material has two shortcomings. Firstly, it is expensive and secondly, it is produced only by Toray/Japan, which may cause hitches in its supply. 2.6 Polyethylene naphtalate capacitors Polyethylene naphtalate (PEN) was not used for film capacitors until 2000. The RoHS directive adopted by the EC in 2003 caused producers of electronic components to utilize substitutes for the existing materials as these could not stand the thermal stress generated by elevated soldering temperatures without significant degradation. The electrical properties of PEN film are very similar to those of PET, but the overall performance of PEN is inferior - provided that the maximum operating temperature is not taken into account /7/. PEN capacitors are larger than the corresponding PET types because the dielectric constant £r and the dielectric strength Eb of PEN are lower. The ratio of PEN capacitor size to the corresponding PET capacitor is between 1.5 and 2. PEN film SMD capacitors are in compliance with the RoHS directive, and are suitable for IR or vapor phase reflow processes. PEN capacitors are Table 2: Properties of capacitor dielectric materials Parameter Unit Dielectric PS PC PET PEN PP PPS PTFE COG X7R Dielectric constanter 2.2 2.9 3.3 3.0 2.2 3.0 2.0 12...40 700...2000 Dielectric strength V/|im 100 200 400 300 600 250 150 200 C temperature coefficientac Ppm/°C -120 ±80 +600 +200 -300 -150 -80 ±30 ±1000 Dissipation factor tarô (1 kHz) 10"4 5 15 80 80 5 20 1 15 350 Volume resistivity p Qcm 1018 1016 1017 1017 1018 1017 1019 1017 1016 Dielectric absorption DA % 0.01 0.1 0.5 1.2 0.02 0.05 0.01 0.6 2.5 Operating temperature TmJTmax °C -55 125 -55 100 -55 105 -55 125 -55 100 -55 140 -55 200 -55 125 -55 125 Self-healing no yes yes yes yes yes no no no SMD configuration no no yes yes no yes no yes yes 13 Informacije MIDEM 38(2008)1, str. 11-19 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters also featured with improved temperature stability with respect to PET. The capacitance temperature coefficient aC of PEN is approximately only one third of the ao of PET. The dielectric absorption DA of PEN is the biggest among the polymer film dielectrics. Its value of approximately 1 % is the order of magnitude of DA specified for MLCCs using X7R ceramics. tion in the final stage of production and consequently stored in the nonvolatile portion of memory. The pitfalls of capacitor selection are illustrated by the case of the small resistive temperature sensor. The important, i.e., the analog part of the smart sensor is shown by the simplified schematic diagram in Figure 1. 2.7 Other dielectric materials Three types of dielectric materials, that have not been mentioned previously, are also listed in Table 2. Poly-tetrafluoroethylene (PTFE) better known under DuPont Company's trade name Teflon®, is an excellent insulating material, but PTFE film capacitors are very rare. Proper metallization of PTFE film is very difficult, this material is very expensive and films of a thickness < 6 |im are not commercially available /7/. PTFE capacitors are used in high power applications where their high operating temperature range and low dissipation factor justify their high price. The data on ceramic dielectric materials in Table 2 are given for comparison, since MLCC chips are very popular and cheap. In fact only C0G ceramics, also known as NP0, are a real match for polymer films as far as stable high performance capacitors go. In addition to the materials discussed, X7R ceramics offer a cost and room efficient solution when large capacitances in small packages with low equivalent serial resistance (ESR) are required. 3. Capacitor for integrating A/D converter 3.1 Four slope integration Dual slope integration is a well-known method for accurate A/D conversion /1/. Accuracy and resolution are two distinctive features of such A/D converters. The resolution of integrating converters is determined by the ratio between the period of the clock that is used for counting and the time of integration, which is measured in clock periods. Arbitrary resolution can be achieved by appropriate selection of these two parameters, but at high resolutions conversion times can become unacceptably long, since maximal counter frequencies are limited. On the other hand, the accuracy of the result is determined by the used reference, if everything else is done ideally. Integrating A/D conversion is very useful for measuring slowly varying quantities, e.g., strain, temperature, humidity, illumination etc. Furthermore, smart sensors with digital output can be designed as a combination of a standard microcontroller, an integrating A/D converter, and an analog sensor of a physical quantity. Low cost uncalibrated sensor devices may be used, without compromising the accuracy of the final result because the deficiencies of the analog sensing device are compensated numerically. The required signal conditioning data are obtained by calibra- Fig. 1: Integrating A/D converter The conversion is initiated by closing switch Si for fixed time to determined by a certain number of clock periods. The integrator output voltage Ui ramps up, reaching a maximum value that is proportional to the voltage across the sensor resistance Rx. At the end Si is opened and S2 is closed. The output ramps down with a slope that is proportional to the voltage of a very stable resistor Rref. When the integrator voltage becomes negative with respect to analog ground, the timer inside the microcontroller is stopped by the negative edge of the comparator output E. The plots of main converter signals are shown in Figure 2. Ui(t) Um y to tx s, S2 E Fig. 2: Time diagram: Ui integrator output, E comparator output The peak integrator voltage can be expressed by Um=ImRx J^ = ImRREF-j^; (1) where Im represents the measuring current through the sensor Rx and reference resistor Rref, respectively. From the unknown resistance of the sensor is given by = rref -r (2) 'o meaning that only the stability of Rref has influence on the result accuracy. This would be true if the opamp and comparator were ideal. The dual slope principle is not sensitive to the instability of the integrator time constant RC as 14 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters Informacije MIDEM 38(2008)1, str. 11-19 long as the constant remains unaltered during conversion time to + tx. The integrator peak voltage Um given by remains unaffected by the comparator input offset voltage, since the counting of both times, charging to and discharging tx, are started and stopped at the same integrator voltage, respectively. The actual conversion is started by closing S2 until the integrator output ui becomes negative then both switches (Si and S2) are toggled. The charging time to counter is not triggered until the rising edge of the comparator output E. The input offset voltage Uo of the opamp in the integrator induces an error that can be expressed as ARx = _2£/Q (3) with Im denoting the measuring current (Figure i). As it is shown in /8/ this error is compensated by reversing the polarity of the measuring current Im, which is done by negation of the logic outputs Pi an P2 (Figure 1). The accurate result is the mean of the results obtained with both polarities of the current Im (xl + lx2 Rr=R ■KEF 2 t. 0 (4) The procedure with four slopes of integration, shown in Figure 3, doubles the required conversion time, but low cost opamps with offset voltages |Uo| < 1 mV may be used. Fig. 3: Plot of the integrator output u(t) in the four slope A/D converter 3.2 Dielectric absorption The analyzed integrator is part of an intelligent resistive sensor of small physical dimensions (25 x 9 mm), therefore small passive components are used. The long integration time, which is necessary to achieve the prescribed resolution, and the low supply voltage require relatively large capacitance C = 100 nF that prevents the integrator output from reaching saturation. The first logical choice was an X7R ceramic chip capacitor, characterized by its small dimensions and SMD package. The value of capacitance appears neither in eqn. nor in , therefore the temperature coefficient and tolerance are not important for this purpose. Experimental tests have shown poor accuracy in the intermittent mode of operation. The sensor was designed for battery powered systems, so the analog part of the circuit is powered only when the conversion takes place. Dielectric absorption of the capacitor has been overlooked, and the effect of the absorbed charge has not been noticed in continuous mode since the capacitor mean voltage is zero. For the great majority of capacitor applications the dielectric absorption coefficient DA is not an important parameter. It matters only in some sample and hold circuits, and obviously in integrators that operate once in a while and have long integrating times. This phenomenon can be measured as a small voltage that reappears across the open capacitor terminals after a charged capacitor has been thoroughly discharged /10/. When voltage is applied to the capacitor plates a certain small part of the stored charge becomes bound on the surface of the dielectric. The process of charge recovery is governed by pretty long time constants that depend merely on the used dielectric material. Measurement of the absorption coefficient DA according to the standard MIL-C-19978 D /9/ is depicted in Figure 4. Uc(t) i U, UN xDA + -15min 0 10s 15min J t Fig. 4: Timing and definition of voltages associated with the measuring of the dielectric absorption (UN denotes nominal voltage). The effects of dielectric absorption in electric circuits are studied by suitable models that replace the capacitor in question. These models /11/, /12/ can be quite complex but in most cases a simple model shown in Figure 5 is sufficient for basic understanding. For commonly used dielectrics, 50% of the final voltage is recovered in 1 to 10 seconds, whereas it can take as much as 15 minutes to reach within 5% of the final value. R CxDA Fig. 5: The basic model of the dielectric absorption in capacitors The resistance in the model of Figure 6 is given by x R = - DAC (5) where Tdenotes the dominant recovery time constant and DA is the absorption coefficient (Table 2). The values of t for particular materials are usually not specified and have to be determined by experimental measurements if a greater accuracy than the generally presumed range from 1 to 10 s is desired. Detailed analysis has shown that the integrating capacitor was charged almost to supply voltage (Ucc = 3.3 V) when 15 Informacije MIDEM 38(2008)1, str. 11-19 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters the negative supply pin of the amplifier chip was not tied to ground to reduce supply current. The error caused by recovered charge is drastically reduced by the four slope integration method. The error of n-th successive measurement after the amplifier is turned on is given by ARx UcoDA R> 2Um T 1 - K 2t -"Un-1) (6) where Uco is the integrating capacitor initial voltage, T = to + tX is the conversion time of one polarity, t is the dominant time constant of the absorbed charge recovery, and Um is the peak voltage of the integrator (Figure 2). The used ceramic chip capacitor has turned out to be completely inadequate for accurate temperature measurements on the basis of platinum resistors. Errors due to the dielectric absorption of the consecutive resistance measurements of the platinum resistor Rx (Pt 1000) are shown in Table 3. The results are expressed as temperature errors in °C using the temperature coefficient of platinum 3850 ppm/°C. The values in Table 3 are calculated using for two different absorption coefficients, whereas the other parameters are the same: Uco = 3.3 V, Um = 1V, t = 3s, T = 1s. The errors calculated for X7R ceramics are in good agreement with the measurements, which have initiated more detailed analyses. Table 3: Error of consecutive A/D conversions expressed in temperature Consecutive measurement no. A7~[°C] DA = 2.5% (X7R) DA = 0.05% (PPS) 1 0.860 17X10"3 2 0.442 8.84x10 3 3 0.227 4.54X10"3 4 0.116 2.33X10"3 5 0.059 1.19*10"3 The theoretical error caused by the absorption of PPS film SMD capacitor is smaller than the desired resolution of the design, therefore raw conversion data, i.e., timer counts that measure time tx, have been observed. The raw results of consecutive conversions (after power up) are within plus minus one count, provided that the temperature is constant. 4. Tests in climatic chamber 4.1 Naked PPS SMD capacitor Encouraged by the theoretical results (Table 3) an adequate substitution for the X7R MLCC has been found in the form of the stacked PPS film capacitor. These capacitors are almost a perfect choice and feature a very low absorption coefficient DA and very low dissipation tan5 < 510-4 in the temperature range from -25°C to 80°C. The data for PPS shown in Table 2 are rather misleading because the worst values over the whole temperature range are given. In addition, PPS capacitors are available as small SMD components that save space on the PCB and fit on solder pads provided for the former ceramic capacitor. The construction of naked stacked film capacitors is shown in Figure 7. The lateral side is usually left without any coating /4/. Fig. 6: Production and construction of stacked naked PPS film chip capacitors In stacked-film production technology, large rings of metallized film are wound onto core wheels with diameters up to 60 cm. Then the rings are sawed apart obtaining well defined width (dimension W in Figure 6). In this way, capacitances with very low tolerances are obtained, since the active body is very homogenous, without the air pockets which are typical of flattened wound bodies. Actual measurements have proved that PPS capacitors have negligible dielectric absorption; hence no differences have been detected between the results of the first and immediately repeated measurements. Upon the verification of the calibrated sensors, some of them returned values that were up to 2°C lower than the actual temperature in the chamber, which was 12°C. Among the 120 devices under test, about 10% were bad, i.e., | AT|> 0.1°C. It turned out that humidity inside the chamber had run out of control. At temperatures around 12°C the humidity had exceeded 90%. The deviation of certain circuits was obviously influenced by humidity, so protection against moisture should improve the performance of the PCB in humid environments. Polyurethane coating applied to the assembled PCBs did not help. The deviations of the bad circuits remained unacceptable. Since it was not clear which part of the circuit was affected by humidity, several experiments were carried out. The results in Figure 8 show that high humidity and temperature affect the four slope A/D converter. In this experiment the temperature dependent resistors (Pt1000) of three sensors were kept outside the climatic chamber at a constant temperature, while the PCBs were exposed to temperatures increasing in increments at high humidity and decreasing at low humidity, respectively. As one can note from the plots in Figure 7, the impact of the temperature increments in the presence of high humidity is not the same 16 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters Informacije MIDEM 38(2008)1, str. 11-19 for all circuits, but when humidity is low the circuits are left virtually unaffected. Fig. 7: Measurement results of three sensors with naked PPS capacitors: at high humidity RH = 90% the chamber temperature was increased in 5°C increments from 15°C to 45°C, then the air was dried to RH = 30% and the temperature was decreased to 15°C, again in decrements of 5°C. Each step of this temperature reduction lasted Ihour. Next, the integrating PPS chip capacitors of the three tested samples were replaced by encapsulated PET capacitors with wire terminals and then the same experiment was repeated. The plots that are shown in Figure 8 reliably indicate that certain PPS chip capacitors were affected by high humidity and not the PCB itself. The results registered by the third sensor are meaningless since a fault occurred during the replacement of the capacitor. The steps in the upper and middle plot are a consequence of the temperature coefficients of each reference resistor Rref, because the sensors were kept at different, i.e., constant temperatures during the test. Fig. 8: Measurement results of three sensors with encapsulated PET capacitors: at RH=90% the chamber temperature was increased in increments of 5°C from 15°C to 45°C (the left half of the diagram), then the air was dried to RH=30% and the temperature was decrementally reduced down to 15°C. 4.2 The influence of humidity on insulation resistance Obviously, some of the used PPS capacitors were influenced by moisture. The influence of absorbed moisture on capacitance was excluded by empirical immersion tests, so only the surface resistance between capacitor terminals Rp remains as the possible cause of inaccurate conversion, if this resistance is decreased due to air humidity. First, we have to estimate the order of magnitude of such a decrease of resistance that could cause the observed inaccuracies. As is shown in Figure 9, the parallel resistance represents a leak for the charge stored in the integrating capacitor. The sensitivity can either be derived from the exact analytic solution, or a few simple approximations can be used. The latter alternative is presented as follows. Fig. 9: Integrator with insulation resistance Rp (above), plot of integrator output voltage ui with (—) and without Rp (- - -) (bellow) At the end of the first step of conversion the peak integrator output is reduced by <+<0 C C J Rp 2 Rp k (7) with Aq denoting the charge that leaks through Rp and Um is the voltage that would be reached if there were no leakage, i.e., RpThe shape of u/(t) in is considered straight and Au/1 = Um is neglected in the integral. During the second step of conversion, ui(t) decreases faster than in the ideal case (Figure 9) and after discharging for to it would become negative. The relative error of the conversion Ah tr Auji + Am,-2 _ 2Aua Um U„ _Jo_ RPC (8) where tx is approximated by to, hence Au/2 = Au/i. In our special case where the actual input voltage is proportional to the resistance of the platinum temperature sensor it is convenient to express the difference between the measured and the actual temperature 17 Informacije MIDEM 38(2008)1, str. 11-19 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters A T = = - R. 1_ aR to RpC mO,R (9) Table 4: Mean values of insulation resistance at Udc=1V and T= 25°C, where aR denotes temperature coefficient of platinum. The plot of this temperature deviation for C = 100 nF, t0 = 0.5 s and aR = 3850 ppm/°C is shown in Figure 10. -0.5 u 0 1 RP [Gii] Fig. 10: Deviation of measured temperature vs. insulation resistance RP The derivation of eqn. is carried out only for the first phase of A/D conversion because both phases of the actually implemented four slope conversion are equally influenced by the charge leak. According to capacitor producer AVX /4/ the insulation resistance of a 100 nF capacitor is > 60 GO for T < 75 °C. Under normal conditions such values of Rp cannot engender noticeable deviations. Moreover, the constant resistance that appears between the capacitor terminals is taken into account during calibration, so that the conversion results in operation are influenced only if this resistance is decreased owing to environmental influences. The theoretical plot in Figure 10 shows that the parallel resistance has to decrease to about 1 GO when the result fails for approximately -1.5 °C. Such errors can be noted in the experimental results shown in Figure 7, where it is obvious that in the presence of damp air the parallel resistance of some capacitors is reduced to 50% or less by rising the temperature for 5°C. 4.3 Insulation resistance measurements Both our theoretical and experimental findings have been verified by measurements of two sets of PPS film capacitors (100 nF/16 V), i.e., brand new capacitors and the desoldered ones, which were removed from the assembled PCBs that turned out as bad. The new capacitors were immersed for 24h in a 20% isopropyl alcohol (IPA) water solution. The immersion caused no measurable differences in the capacitance and dissipation factors. The measured capacitance tolerance of all samples was les than 1%. Furthermore, the insulation resistance of the devices was measured at different air humidities. The leakage current at the applied voltage 1V was measured by a precise picoampermeter. The results are summarized by mean values in Table 4. Relative Humidity [%] R, new desoldered 35% 100 GQ 100 GQ 60% 40 GQ 100 MQ 90% 10 GQ 30 MQ The results in Table 4 clearly indicate that the origin of the noticed inaccuracies lies in the resistance between the capacitor terminals. PPS capacitors have very low moisture absorption, but the naked types are affected by the side effects of PCB assembly, because the new devices perform much better when leakage is involved. The work of Hunt and Zou /13/ has shown the importance of appropriate selection of the flux in the soldering paste. The residues of soldering fluxes contribute to the surface conductivity as the humidity is increased. This effect is especially pronounced for weak organic acid (WOA) based fluxes at high humidity (> 85%). It has been already mentioned that the PCB's were protected against moisture but that these efforts turned out to be unsuccessful. The tested sensors were washed in deionized water, dried and protected with a thin polyurethane coating (Urethane 71) but the surface of some PPS chip capacitors remained contaminated by flux residues. The applied coating should be substantially thicker, which is a rather unpractical solution. The weak point of the naked chips is the exposed lateral sides (Figure 7) on which the metal atoms that form the capacitor plates can be found. These lateral sides are additionally vulnerable due to the small gaps between the clusters of stacked dielectric film. It is almost impossible to clean these gaps once they get contaminated. The first prototypes were soldered by hand using ordinary soldering wire filled with resin. In this case, increasing the humidity does not reduce the surface resistivity /13/, therefore the high humidity effects were not noticed until a different technology of PCB assembly was used. It is important to note the fast response of the observed leakage current to the changes in humidity, which obviously points to the fact that only the surface of the capacitor is involved in this process. 5. Conclusion The choice of SMD film capacitors on the market has gone through significant changes that were initiated by the EC RoHS directive. New high temperature dielectric materials have been introduced in production. PET, PEN and PPS films are used for plastic film SMD capacitors. Special attention must be paid during the assembly of PET capacitors with regard to the reflow soldering process. PEN and PPS capacitors tolerate slightly higher temperatures in the reflow soldering process which in turn is beneficial for the reliability and quality of the leadless solder contacts. PEN 18 A. Levstek, M. Pirc: SMD Film Capacitors for Integrating A/D Converters Informacije MIDEM 38(2008)1, str. 11-19 capacitors should be avoided if dielectric absorption is important. PPS capacitors are now commonly available from various producers, but are the most expensive. The construction of the capacitor should be carefully selected for each particular application. Stacked film capacitors have tight tolerances and require the least space on the PCB. As described in this paper, their naked construction is vulnerable to humidity, which reduces the parallel resistance due to surface conductivity. Wound capacitors are made by individually rolling the metallized film ribbons into cylindrical rolls which are then flattened to a prismatic shape. Wound capacitors are less sensitive to humidity, since the outer layers of the roll protect the capacitor core inside. Wound types are available naked or encapsulated in plastic boxes that provide additional protection against the environmental influences. Both variants of wound capacitors require more space on the PCB than the stacked one. The described case study shows the importance of careful component selection from amongst the variety that is offered on the market. Besides choosing the right dielectric material, it is equally important to consider the construction of the capacitor. Of course, it is almost impossible to anticipate the behavior and interactions of real components that are exposed to harsh climatic conditions. In addition, accurate integrating ADCs that require high insulation resistances (R > 50 GO) are suitable only for applications that are well protected against humidity. If such protection cannot be provided in a simple and cost-effective way other ADCs should be used. In any case, intensive computer-controlled testing of prototypes in climatic chambers is an important step in the good design of demanding electronic products. 6. References /4/ http://www.avx.com, AVX Film chip capacitors, Product's master catalog version 7.1, /5/ B. Walgenwitz, J-H. Tortai, N. Bonifaci, A. Denat, Self healing of metallized polymer films of different nature, Proc. of 2004 IEEE Int. Conf. on Solid Dielectrics, Toulouse, France, 5-9 July 2004, Vol.1, pp. 29- 32, ISBN 0-7803-8348-6 /6/ http://eur-lex.europa.eu/LexUriServ/LexUriServ.do?uri = CELEX:32002L0095:EN:HTML /7/ K.Saarinen, M. Niskala, E. Matero, J. Peràlà, SMD plastic film capacitors for high temperature applications, http:// www.evoxrifa.com /8/ A. Levstek, Pretvornik s štirikratno integracijo za mikrokrmilniški senzor temperature, Proc. of 16th ERK 2007, Portorož, Slovenija,September 24-26, 2007, Vol. A, pp. 42-45 /9/ http://www.wima.de/EN/absorption.htm /10/ S. Amon, Elektronske komponente, Založba fakultete za elektrotehniko in računalništvo, Ljubljana, 1992, ISBN 86-7739049-9 /11/ C. lorga, Compartmental analysis of dielectric absorption in capacitors, IEEE Transactions on Dielectrics and Electrical Insulation, vol. 7, no. 2, Apr. 2000, pp. 187-192 /12/ K. Kundert, Modeling dielectric absorption in capacitors, The designer's guide 2006, http://www.designers-guide.org/Mod-eling/ /13/ C. Hunt, L. Zou, The impact of temperature and humidity conditions on surface insulation resistance values for various fluxes, Soldering and surface mount technology, Vol. 11, No. 1, 1999 MCB University Press, pp 36-43 Dr. Andrej Levstek, univ. dipl.ing.el. Asst. Matija Pirc, univ.dipl. ing. el. University of Ljubljana Faculty of Electrical Engineering Laboratory of Microsensor Structures and Electronics Tržaška cesta 25, SI-1000 Ljubljana, Slovenia E-mail: andrej.levstek@fe.uni-lj.si /1/ S. Tumanski, Principles of electrical measurement, CRC Press, New York, 2006, ISBN 9780750310383. /2/ WIMA Main Catalog 2001 Edition, accompanying notice, /3/ http://www.ecicaps.com Prispelo (Arrived): 07.03.2007 Sprejeto (Accepted): 28.03.2008 19 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana COMPARISON OF INDUCTOR MODELS USED IN ANALYSIS OF THE BUCK AND BOOST CONVERTERS Krzysztof Gorecki, Witold J. Stepowicz Gdynia Maritime University, Department of Marine Electronics, Poland Key words: dc-dc converters, SPICE, inductor models Abstract: The inductive devices with the ferromagnetic core are widely used in many electronic circuits, for example in the buck and boost converters, to store magnetic energy. They should be treated as nonlinear devices, and the nonlinearity of their characteristics arises from the dependence of inductance on current. In the paper the influence of the nonlinear and linear inductor models on some selected characteristics of the above-mentioned converters is compared. As a tool to compute these characteristics SPICE was used. Primerjava modelov induktivnosti uporabljenih pri analizi konverterjev Kjučne besede: DC-DC konverterji, SPICE, modeli induktivnih komponent Izvleček: Induktivne komponente na feromagnetnih jedrih pogosto uporabljamo v mnogih elektronskih vezjih, npr. v DC-DC konverterjih, za shranjevanje magnetne energije. Potrebno jih je obravnavati kot nelinearne elemente , saj njihova nelinearna karakteristika izhaja iz tokovne odvisnosti induktivnosti. V prispevku primerjamo vpliv linearnih in nelinearnih modelov induktivnosti na delovanje konverterjev. Pri analizi smo uporabili program SPICE. 1. Introduction In the dc-dc converters, which are the basic part of switched voltage regulators, the inductors with ferromagnetic core are used to store magnetic energy /1, 2/. These inductors should by characterized by the high value of the permeability and the high value of the saturation induction. The inductor with the ferromagnetic core is a nonlinear device, what results from the dependence of its inductance on current. The inductance decreases strongly with current, when the operation point of the core is moved to the saturation range of the magnetic induction, and it can cause the limitation of the allowable output current (or the load resistance) of a voltage regulator. To design the dc-dc converters and other electronic circuits computer programs are used, and nowadays SPICE belongs to the most popular computer tools /3, 4/. In SPICE the models of many electronic devices are built-in, and to obtain reliable results of analysis, they should be simple, accurate and with credible values of their parameters. As far as inductors are concerned their linear and nonlinear SPICE models are described in /5/. In Sec. 2 the nonlinear model of inductor is presented, and the basic characteristics and parameters of the selected inductor under consideration are given. As the main purpose of this paper is to show the influence of the nonlinear model of the inductor on some important characteristics of the typical buck and boost converters, therefore the basic characteristics of these circuits with the linear and nonlinear inductor models taken into account were computed to this end, and they are shown and discussed in Sec. 3. By comparing the characteristics obtained on the nonlinear model with the characteristics obtained on the linear one some remarks concerning the usefulness of the nonlinear model in the analysis of the converters are given in Sec. 4. 2. Nonlinear model of inductor In SPICE two nonlinear models of the inductors with the ferromagnetic core are attainable: Jiles-Atherton model (JA model) /6/ and SPICE Plus model. On the models the hysteresis curve B(H) causing this nonlinearity can be calculated. In the paper /9/ the results of the computations obtained on SPICE, showing the sensitivity of the nonlinear dependence L(i) on the parameters of the JA model, are given. In SPICE the isothermal analysis, which is the analysis at any constant ambient temperature, is possible, without taking into account the temperature rise caused by energy losses (the self-heating phenomenon) in the inductor. The electrothermal model of the inductor allowing the electrothermal analysis with the self-heating taken into consideration is proposed in /7/. The essential dependences of the JA model needed to compute the curve B(H) are as follows b = \i.0(h + m) (1) MSH (2) (3) M„, / H /+ A dM dH 1 M -M C dM 1 + C k 1 + C dH 20 K. Gorecki, W. J. Stepowicz: Comparison of Inductor Models Used in Analysis of the Buck and Boost Converters Informacije MIDEM 38(2008)1, str. 20-25 where: B - magnetic induction, |o - permeability of vacuum, H - magnetic field, M - magnetisation, Man - initial magnetisation, and the parameters of the model are: MS - saturation magnetisation, A - thermal energy parameter, K - domain anisotropy parameter, C - domain flexing parameter. On the computed dependence B(H) the incremental permeability | can be obtained, which is needed to calculate the inductance L. To compute the dependence L(i), at first the magnetic field H is calculated at any assumed current i according to a) H=- 1 (4) where: z - number of coils, l - length of the magnetic path (core model parameter PATH). When H is given, the hysteresis curve B(H) can be computed on the basis of the formulae (1-3), then the incremental permeability | at the assumed current can be calculated, and the inductance L is given as follows /8/ z^vs.ds (5) I dH where S - the cross-section of the core (core model parameter AREA). In the computations presented below the following values of the parameters of the considered core were assumed /9/: MS = 412.2 A/m, A = 44.82 A/m, K = 25.74 A/m, C = 0.411 A/m (taken from SPICE library MAGNETIC.LIB for K528T500_3C8 core). The magnetic path was l = 3.84 cm, the coil number z = 10 and the cross-section area of the core S = 0.63 cm2. The hysteresis curve at the frequency f = 10 kHz and the dependence L(i) of the inductor computed with the above given parameters values are shown in Fig. 1a, b, respectively. As seen from Fig. 1a, the saturation induction of the considered core amounts about 430 mT (after converting units of measure, as in SPICE the magnetic field is denominated in oersted (Oe) and the magnetic induction in gauss (Ga)). The derivative dB/dH attains its maximum value at the inductor current equal to about 100 mA . As seen from Fig. 1b, for the inductor under consideration the inductance L decreases with current increase from L = 590 |H in low and medium current range to L = 35 |H at 1 A, what corresponds to the start of the saturation range of the B(H) curve, and next up to L = 0.2 |H at the high current equal to about 100 A, when the operation point is placed in the deep saturation range of the dependence B(H). 0,5 0,4 0,3 0,2 _ 0,1 & 0 " -0,1 -0,2 -0,3 -0,4 -0,5 -300 -200 -100 0 100 H [A/m] 200 300 b) looo 100 10 0,1 0,001 0,01 0,1 10 100 i[A] Fig. 1. The hysteresis curve B(H) of the core (a), and the dependence of the inductance on the inductor current (b) efficiency n on the load resistance Ro, on the duty factor d and on the input voltage Vi. Additionally, the dependence of the peak-to-peak output voltage (ripples) Vpp on the load resistance was computed as well. These dependences were computed with the nonlinear model of the inductance L, which characteristics (Fig. 1) and parameters values are given in Sec. 2, and, for comparison, with the linear model at three values of the inductance L equal to 590 |H (corresponding to the low and medium current range), with 35 |H (corresponding to i = 1 A) and with 0.2 |H (corresponding to i = 100 A). The computations were carried out by SPICE at the ambient temperature T = 300 K. In these computations the SPICE built-in models of the diode and MOS transistor were used with their parameters values taken from library EVAL.LIB for diode 1N4148 and transistor IRF150. For two considered converters R2 = 10 Q and C= 470 |F were assumed. The voltage source V2 supplies the trapezoidal pulse run with the low and high levels of the transistor input voltage vgs equal to 0 and 10 V, respectively; the period of this run is equal 10 |is (Fig. 2). 3. Influence of inductor models on the characteristics of converters The computations of the selected characteristics were carried out for the buck (Fig. 2a) and boost (Fig. 2b) converters. The following basic characteristics were considered: the dependence of the output voltage Vo and the 3.1 The buck converter For the buck converter (Fig. 2a), the dependences Vo(Ro) and n(Ro) with the duty factor d = 0.5 and the input voltage Vi = -20 V, next the dependences Vo(d) and n(d) with Ro = 100 Q and Vi = -20 V were computed, while the dependences Vo(Vi) and n(Vi) with d = 0.5 and Ro = 0.5 Q, respectively. These all characteristics were calculated at three 21 Informacije MIDEM 38(2008)1, str. 20-25 K. Gorecki, W. J. Stepowicz: Comparison of Inductor Models Used in Analysis of the Buck and Boost Converters V¡ © It IRF150 R2 D1N4148 V SV V2 0 =C1 v0 b) © V L -AW- D1N4148 IRF150 D"- Fig. 2. The schemes of the buck (a), and boost (b) converters values of the linear inductance taken from the different current ranges of the dependence L(i) and with the nonlinear model of L(i) described in Sec. 2. In Figs 3a, b the characteristics Vo(Ro), and n(Ro) are shown, respectively. As seen from Fig. 3a, at low load resistances (high currents), when the core saturates, the dependences Vo(Ro) do not differ considerably for the nonlinear model, the linear model with at L = 590 |H and at L = 35 |H, while at high resistances (low currents), without core saturation, only the results obtained on the nonlinear model of L(i) and on the linear model at L = 590 |H are similar to each other. In the whole resistance range the characteristic with L = 0.2 |H differs from other characteristics considerably. As it results from computations (Fig. 3a), the converter operates in the current continuous mode (CCM) at Ro < 200 Q as the nonlinear model L(i) was used, while on the linear model the lower values of this resistance are obtained: R0 = 10 Q at L = 35 |H and Ro = 0.2 Q at L = 0.2 |H, what, in turn, leads to high differences in the computed values of the output voltage obtained on the considered models in the discontinuous current mode (DCM) especially. From Fig. 3b it results that the computed efficiency n obtained on the nonlinear model of L(i) is lower than n resulting from the linear model in the whole range of the assumed values of Ro. These divergences result from the energy losses in the core taken into account in the nonlin- a) o -2 -4 -6 ► -12 -14 -16 -18 -20 BUCK Vi = -20 V d = 0.5 the nonlinear model \ L = 590 |iH L= 35 - .. 10 Rol"! 100 1000 b) 100 90 80 70 60 50 40 30 20 10 0 -----L=590 HH L = 220 nH 10 R„["J 100 1000 Fig. 3. The dependences of the output voltage (a), and the efficiency (b) on the load resistance for the buck converter a) > o > BUCK Vi = -20 V \ ^ the nonlinear model R„=100£i \ ^\L = 590 HH L = 35 HH L = 200nH -... 0,2 0,4 0,6 d b) 120 100 80 60 p- 40 20 0 . . k=. M-H _ _ ['{. = 200 nil------____ L = 590 -----the nonlinear model BUCK Vi=-20 V Ro= 100 £i 0,2 0,4 0,6 d Fig. 4. The dependence of the output voltage (a), and the efficiency (b) on the duty factor for the buck converter 22 K. Gorecki, W. J. Stepowicz: Comparison of Inductor Models Used in Analysis of the Buck and Boost Converters Informacije MIDEM 38(2008)1, str. 20-25 ear model. With the decreasing inductance the efficiency increases. In Figs 4a, b the characteristics Vo(d) and n(d) are shown, and as seen from Figs 4a the essential difference is observed between the dependence Vo(d) with L = 200 nH and L = 35 |H in relation to other curves. As stated before, at Ro = 100 Q the core does not saturate. From Fig. 4b it results that, as before, the computed efficiency n obtained on the nonlinear model is lower than n resulting from linear model in the whole range of the assumed duty factor d practically, what is caused by the energy losses taken into account in the nonlinear model. In Figs 5a, b the characteristics Vo(Vi) and n(Vi) are shown with Ro = 0.5 Q and d = 0.5 assumed. In this case these characteristics computed with L = 35 |H and L = 590 |H are practically identical. The voltage transfer characteristic with L = 200 nH (Fig. 5a) differs from the curves with other values of the inductance considerably. The efficiency n (Fig.5b) obtained on the nonlinear model is lower about 20% than n obtained on the linear model. The dependence of the ripples of the output voltage on the load resistance Vpp(Ro) is shown in Fig. 6. As it could be expected /1/, the ripples decrease with the increase of the inductance. The highest ripples are at low values of Ro - for the nonlinear model they amount above 100 mV, and at L = 590 |H they amount about 100 |V. a) o -2 -A -6 ."10 > -12 -14 -16 -18 -20 BUCK d = 0.5 ■ - *' Ro = 0,5 ii the nonlinear ' model , ' * T^^L^iS jiH L= 590 (iH L= 200 nH ____- •*---- -40 -35 -30 b) 80 70 60 50 2 40 30 20 10 0 BUCK d = 0.5 Ro = 0.5 £2 -25 -20 -15 -10 Vta[V] L = 200 nH ....... the nonlinear model -40 -35 -30 -25 -20 -15 -10 -5 0 VM [VI Fig. 5. The dependence of the output voltage (a), and the efficiency (b) on the input voltage for the buck converter 0,1 0,01 0,001 0,0001 BUCK Vin = -20 V d = 0.5 the nonlinear model ' -L = 200nH - L = 35 M-H N. \ " ' * •■------ L = 590 HH 10 Ro[q1 100 1000 Fig. 6. The dependence of the ripples of the output voltage on the load resistance for the buck converter a) ioo 60 " 50 40 30 20 BOOST Vi = 12 V L = 200nH.--J " d = 0.5 L = 35HH . the nonlinear model . y L=590 HH 1000 b) 100 n 90 BOOST SO Vi= 12 V 70 d = 0.5 _ 60 L= 586 M-H 1000 Fig. 7. The dependences of the output voltage (a), and the efficiency (b) on the load resistance for the boost converter 3.2 The boost converter For the boost converter (Fig. 2 b) the characteristics Vo(Ro) and n(Ro) were computed with d = 0.5 and Vi = 12 V, next Vo(d) and n(d) with Ro = 3 Q and V = 12 V, and Vo(Vi) and n(Vi) with d = 0.5 and Ro = 3 Q. In Figs 7a, b the characteristics Vo(Ro) and n(Ro) are shown. As seen from Fig. 7a, the noticeable differences between the curves for all inductances assumed are at higher values of the load resistance, when the core does not saturate. At L = 590 |H and at the nonlinear model of the inductance the converter operates in CCM in the whole considered range of the load resistance. At the lower induct- 23 Informacije MIDEM 38(2008)1, str. 20-25 K. Gorecki, W. J. Stepowicz: Comparison of Inductor Models Used in Analysis of the Buck and Boost Converters ances this mode is limited to Ro = 70 Q (at L = 35 |H) and Ro = 10 Q (at L = 0.2 |H). The dependences n(Ro) (Fig.7b) obtained at four inductances differ from each other considerably, at higher values of the load resistance especially, and the highest differences - even 80%, are visible at L = 200 nH with respect to other curves. In Figs 8a, b the characteristics Vo(d) and n(d) are shown. As seen form Fig. 8a the differences between the obtained dependences Vo(d) for the nonlinear model L(i) and at L = 0.2 |H are similar, while at L = 35 |H and at L = 590 |H the values of Vo are about 100 % higher than those for the nonlinear model. From Fig. 8b it results that the dependences n(d) obtained on the linear model of L differ from the dependence obtained on the nonlinear model considerably. For all considered inductor models the efficiency decrease with increasing duty factor. a) 40 a) 30 BOOST 25 Vi = 12 V 20 Ro = 3 ii > 10 5 0 L= 35 HH L= 590 HH the nonlinear model 0,2 0,4 0,6 0,8 b) 80 70 60 50 40 30 20 10 0 BOOST V,= 12 V \ \ L = 35tlH Ro = 3£i *N "\L = 200nH nonlinear model '>£=590 ra 0 0,2 0,4 0,6 0,8 1 d Fig. 8. The dependence of the output voltage (a), and the efficiency (b) on the duty factor for the boost converter In Figs 9a, b the dependences Vo(Vi) and n(Vi) are shown. As seen from Fig. 9a, at low values of Vi there are no essential differences between the curves with the considered values of L, while at higher values of the input voltage they become visible. As seen from Fig. 9b, the lowest values of the efficiency n are at L = 200 |H - they amount about 10% only. For the nonlinear model the dependence n(Vi) has the maximum at Vi = 4 V. 35 30 25 , 20 15 10 5 0 BOOST L.= 35 HH d = 0.5 ..•X=590 (1H Ro=3 £i ' the nonlinear models " L = 200 nH V, [VJ a) 80 70 60 50 N® 40 P" 30 20 10 0 BOOST d = 0.5 L = 590 HH L = 35 HH Ro =3 í2 ... • ■■'-------- y ^^ the nonlinear model ......... L = 200 nH ____ ------ 10 15 20 v,m 25 30 Fig. 9. The dependence of the output voltage (a), and the efficiency (b) on the input voltage of the boost converter For the boost converter the dependence of the ripples of the output voltage on the load resistance Vpp(Ro) is shown in Fig. 10. The ripples decrease with increasing the load resistance, and the increase of the inductance causes decreasing the ripples as well. BOOST a, a > 0,1 0,01 0,001 0,0001 L = 590 HH 10 100 M"] 1000 Fig. 10. The dependence of the ripples of the output voltage on the load resistance for the boost converter 4. Conclusions In this paper the influence of the inductor model form on the selected characteristics of the buck and boost converters are discussed. The computations results are given for two models of inductance: the nonlinear JA model and 24 K. Gorecki, W. J. Stepowicz: Comparison of Inductor Models Used in Analysis of the Buck and Boost Converters Informacije MIDEM 38(2008)1, str. 20-25 the linear one with the different values of L assumed. On these results one can estimate if the nonlinear model of the inductance is needed in the computer analysis of the converter to obtain reliable results. To this end the inductor current range should be evaluated in the first place. If the core operates without saturation, then the divergences between the computations of the output voltage on the nonlinear model of L and on the linear one with the value of the inductance taken from the low current range are not essential. As the energy losses in the core are included in the nonlinear model of L, then the efficiency obtained on this model is typical lower than on the linear model, and the differences between these computations results of g can even amount some tens of percents. It is worth-mentioning to compare the computation times of the characteristics presented in Sec. 3. Owing to the use of the linear model of the inductor the time needed to analyse any converter circuit is shortened up to 50%. 5. Acknowledgments This work is supported by the Polish Ministry of Science and Higher Education in 2007-2008, as a research project No. N515 064 32/4331. Refrences /1/ R. Ericson, D. Maksimovic: Fundamentals of Power Electronics. Kluwer Academic Publisher, Norwell, 2001. /2/ Mohan N., Undeland T.M., Robbins W.P.: Power Electronics: Converters, Applications, and Design. John Wiley &Sons, New York, 1995. /3/ Vladimirescu A.: The SPICE Book. John Wiley & Sons, New York, 1994. /4/ Wilamowski B.M., Jaeger R.C.: Computerized Circuit Analysis Using SPICE Programs. McGraw-Hill, New York, 1997. /5/ Gorecki K., Zar^bski J.: Modelling of Inductors and Transformers in SPICE. Elektronika - konstrukcje, technologie, zastosow-ania, Not-Sigma, No. 1, 2004, pp. 40 - 43, in Polish. /6/ D.C. Jiles, D.L. Atherton: Theory of Ferromagnetic Hysteresis. Journal of Magnetism and Magnetic Materials, Vol. 61, 1986, p. 48. /7/ Gorecki K.: SPICE-aided Modelling of Coils with the Ferrite Core with Selfheating Taken into Account. Kwartalnik Elektroniki i Tel-ekomunikacji, No. 3, 2003, pp. 389 - 404, in Polish. /8/ W. D^browski, J. Krol, M. Sobon: Magnetic Materials for Ferromagnetic Ferroxyd Cores. Warszawa, Wydawnictwa Przemyslu Maszynowego "Wema", 1976, in Polish. /9/ Gorecki K., Stepowicz W.J.: Influence of Inductor Models on the Characteristics of the Buck and Boost Converters. XXX International Conference on Fundamentals of Electrotechnics and Circuit Theory IC-SPETO 2007, Ustron, 2007, p. 71. Dr. Krzysztof Gorecki Prof. Witold J. Stepowicz Gdynia Maritime University Department of Marine Electronics Morska 83, 81-225 Gdynia, POLAND, Tel. ++48 58 6901448, ++48 58 6901247, fax ++48 58 6217353 E-mail: gorecki@am.gdynia.pl, wjs@am.gdynia.pl Prispelo (Arrived): 27.06.2007 Sprejeto (Accepted): 28.03.2008 25 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana A NEW APPROACH TO OPTIMIZATION OF TEST PATTERN GENERATOR STRUCTURE Gregor Papa1, Tomasz Garbolino2 1Computer Systems Department, Jožef Stefan Institute, Ljubljana, Slovenia institute of electronics, Silesian University of Technology, Gliwice, Poland Key words: test pattern generator, design, optimization, genetic algorithm. Abstract: This paper presents a new approach to design and structure optimization of a deterministic test pattern generator (TPG). The TPG is composed of a linear register and a non-linear combinational function that can invert any bit in the generated patterns. Consequently, any arbitrary test sequence can be produced. Such a TPG is suitable for on-line built-in self-test (BIST) implementations where functional units are tested in their idle cycles. To reduce the gate count of the BIST structure a genetic algorithm (GA) is employed. This approach and its multi-objective nature allows concurrent optimization of multiple parameters within multiple design aspects (register cells type, patterns order in the generated test sequence, bit order of a test pattern), which influence the final solution. Experimental results on combinational ISCAS benchmarks demonstrate the efficiency of the proposed evolutionary approach. Nov pristop k optimiranju strukture generatorja testnih vzorcev Kjučne besede: generator testni vzorcev, načrtovanje, optimiranje, genetski algoritem. Izvleček: V članku je predstavljen nov pristop k načrtovanju in optimiranju strukture generatorja testnih vzorcev (TPG). TPG je sestavljen iz linearnega registra in nelinearne kombinacijske funkcije, ki lahko invertira katerikoli bit generiranega vzorca. Tako lahko dobimo poljubno testno sekvenco. Takšen TPG je primeren za on-line built-in self-test (BIST) izvedbe, kjer se funkcijske enote testirajo v njihovih prostih ciklih. Za zmanjšanje števila logičnih vrat strukture BIST, je uporabljen genetski algoritem (GA). Večkriterijska narava tega pristopa omogoča sočasno optimiranje več parametrov na več načrtovalnih nivojih (tip pomnilnih registrov, vrstni red vzorcev, vrstni red bitov v vzorcih), kar vse vpliva na končno rešitev. Rezultati testiranja s kombinacijskimi testnimi vezji ISCAS so pokazali uspešnost uporabljenega pristopa. 1 Introduction The complexity of modern integrated circuits and rapid changes in technology pose an ever-increasing number of challenges in testing electronic products. With the introduction of surface mounted devices, small pitch packaging becomes prevalent, which makes the access to the test points on a board either impossible or at least very costly. Traditional in-circuit test techniques that utilize a bed-of-nails to make contact to individual leads on a printed circuit board have become inadequate. To cope with this problem, boundary-scan approach has been developed and is now widely adopted in practice /3//25/. Another problem originates from the fact that the number of transistors in a chip increases faster than the pin count and consequently internal chip modules become more and more difficult to access. Limited number of I/O pins represents a bottleneck in testing of complex embedded cores where transfers of large amounts of test patterns and test results between the automatic test equipment (ATE) and the unit-under-test (UUT) are required, /4/. One of the alternative solutions is to implement a built-in self-test (BIST) of the UUT, /28/, with on-chip test pattern generation (TPG) and on-chip output response analysis logic. In this way, the test circuitry is incorporated on-chip and communication with external ATE is reduced to test initiation and transfer of test results /22/. Besides, self-test can be performed at the circuit's normal clock rate. This may increase the coverage of faults that could otherwise be detected only during normal system operation. In addition, BIST can be used for periodic testing and/or to diagnose system failures in system maintenance. On the other hand, BIST implementation inevitably leads to area overhead, which typically results in performance penalties due to longer signal routing paths resulting from the inclusion of the BIST circuitry in the design. Minimization of the BIST logic is one of the commonly addressed problems in practice. Different TPG approaches have been proposed. They can be classified as ROM-based deterministic, algorithmic, exhaustive and pseudo-random. In the first approach, deterministic patterns are stored in a ROM and a counter is used for their addressing, /10/. This simple approach is limited to small test pattern sets. Algorithmic TPG are mostly used for testing regular structures such as RAMs /30/. Exhaustive TPG is counter-based approach which suffers from the fact that it is not able to generate specific sequence of test vectors. With some modifications, however, counter-based solutions are able to generate deterministic test patterns, /5//16//18/. Pseudo-random TPG is most commonly applied technique in practice. In this approach Linear Feedback Shift Register (LFSR) or Cellular Automata (CA) are employed to generate pseudo-random test patterns. In order to decrease the complexity of a TPG, de- 26 G. Papa, T. Garbolino: A new Approach to Optimization of Test Pattern Generator Structure Informacije MIDEM 38(2008)1, str. 26-30 signers usually try to embed deterministic test patterns into the vector sequence generated by some linear register. Such embedding can be done either by re-seeding a TPG or modifying its feedback function /17/. There are also solutions that modify or transform the vector sequence produced by a LFSR in such a way that it contains deterministic test patterns /29//2/. Most proposed LFSR structures are based on D-type flip-flops. In recent years, LFSR composed of D-type and T-type flip-flops is gaining popularity due to its low area overhead and high operating speed /13//14/. In the paper an approach for the generation of deterministic TPG logic based on a Linear Feedback Shift Register (LFSR) composed of D-type and T-type flip-flops is described. The use of LFSR for TPG eliminates the need of a ROM for storing the seeds since the LFSR itself jumps from a state to the next required state (seed) by inverting the logic value of some of the bits of its next state. The approach for constructing the proper LFSR employs a genetic algorithm (GA) to find an acceptable practical solution in a large space of possible LFSR implementations. In the area of TPG, genetic algorithms have mainly been used for the derivation of test pattern sets for target UUTs /8//26/. As for the synthesis of the TPG logic for actual generation of the derived test patters, GA approach has been used for the solutions based on cellular automata /9/. This work was motivated by the need of deterministic test pattern generation for the on line BIST of structure composed of idle function units and registers, originally proposed in /27/. In this approach, functional units and registers that are not used for the computations of the target application during individual time slots are organized into a structure that is continuously tested in parallel with normal system operation. Normally, pseudo-random test vectors can be employed for such on-line self-test. In critical applications, where low fault latency is required, test pattern generators (TPG) that generate deterministic test sequence are needed. Deterministic test sequences (i.e., in which non-useful test vectors are eliminated) may also considerably reduce diagnosis time in fault localization /19/. 2 Test pattern generator structure A TPG can be regarded as an autonomous finite-state machine that is typically configured as a shift register with additional feedback connections. A TPG is said to be linear if its feedback logic is composed exclusively of XOR gates, otherwise it is said to be non-linear. A TPG is initialized to a known initial state, and the contents of its flipflops in the initial state are called the seed. The flip-flops are clocked to cause the transitions, whose exact nature depends on the feedback connections. The values of the state variables in subsequent transitions are used as test patterns. Most reported TPGs are D flip-flop based linear feedback shift registers (LFSRs). In a typical scenario, a TPG is initialized with a given deterministic seed and run until the desired fault coverage is achieved. The test application time using an LFSR is significantly larger than what is required for applying the test set generated using a deterministic TPG. This is due to the fact that vector set generated by a LFSR includes besides useful vectors also many other vectors that do not contribute to the fault coverage. In order to reduce test application time, current non-useful vectors should be replaced by useful vectors appearing later in the test sequence. This can be done in a number of ways. Most commonly used techniques are reseeding and weighted-random pattern generation. In our approach, the goal is to develop a TPG that would generate only the required test vectors (i.e., with no intermittent non-useful vectors). The overall structure of the proposed n bit test pattern generator is presented in Fig. 1. It is composed of a Multiple-Input Signature Register (MISR) and a modification logic. The MISR has a form of a ring that is composed of n flip-flops with either active high or active low inputs. Any flip-flop of the MISR can be of T type or D type. Each flip-flop (D or T) can also have inverter on their input (denoted as d or T). Thus, the register may have one of 4n different structures. The inputs of the MISR are controlled by the modification logic. The outputs of the MISR are fed back to the modification logic which is a simple combinational logic and acts like a decoder. circuit under test KO» X Q fe» x# ÎET _ X Q 0 1 CLR Q cm Q X^ Q n-1 > Q modification logic Fig. 1: Xe{D, D, T, T} Test pattern generator structure In our case, MISR and the modification logic are application specific: they are synthesized according to the required test pattern set. The modification logic allows that in the subsequent clock cycles the contents of the MISR assume the values specified by the target test pattern set. One of the parameters that are important for practical implementations of TPGs is area overhead. It is influenced by the structure of each MISR stage, the order of the test patterns in a test sequence and the bit-order of the test patterns. While the first property influences the complexity of both the MISR and the modification logic, the remaining two impact only the area of the modification logic. 27 G. Papa, T. Garbolino: Informacije MIDEM 38(2008)1, str. 26-30 A new Approach to Optimization of Test Pattern Generator Structure 3 Genetic algorithm The population-based evolutionary approach - employed through GA /1//7//15/ was used for optimization because of its intrinsic parallelism that allows searching within a broad database of solutions in the search space simultaneously, climbing many peaks in parallel. Therefore, the risk of converging to a local optimum is low. Besides, promising results of our research work obtained in other optimization problem areas /20//21//23//24/ encouraged us to consider GA approach as one of the possible alternatives in TPG synthesis optimization. The implementation of genetic operators is described with more details in /24/. 4 Structure evaluation Operation of the y-th cell of the TPG register during one clock cycle can be expressed by the following equation: Qi = tj qj ® q-i- ® ij ® fj Qi = ti qi ® qn- ® ii ® fi (1) where qj-i is the current state of the cell number j-i, qj is the current state of the j-th cell, Qj is the next state of the j-th cell, tj is the coefficient determining type of the flip-flop in the j-th cell , i.e., 0 for D-type flip-flop, and i for T-type flip-flop, ij is the coefficient determining whether there is an inverter at the input of the flip-flop in the j-th cell , i.e., 0 for absence of inverter, and i for presence of inverter, and fj is the value of the j-th output of the modification logic. Thus, the value of the j-th output of the modification logic is: fj, = tj qj ® q-i- ® ij ® Qj fi = ti qi ® qn- ® ii ® Qi (2) On the basis of these equations one can derive values of the outputs of the modification logic for each vector but last in the test sequence. In that way ON-set and OFF-set of the modification logic are defined. Further, Espresso software /11/ was used for Boolean minimization of the modification logic and its approximate cost evaluation. This software takes a two-level representation of a two-valued (or multiple-valued) Boolean function as input, and produces a minimal equivalent representation (number of equivalent gates). It automatically verifies that the minimized function is equivalent to the original function. The algorithms used represent an advance in both speed and optimality of solution in heuristic Boolean minimization. 5 Results The optimization process is shown in Figure 2, where the initialization phase determines the initial TPG structure through the desired sequence of test patterns. The GA tries to optimize the circuit (make new configuration) while checking the allowed TPG structure and using the external structure evaluation tool. The evaluation tool calculates the cost of a given structure through the input test patterns and TPG configuration. After a number of iterations the best structure is chosen and implemented through the hardware description language. Parameters of the GA used in our experiments are; a) for first three circuits: number of generations is 50, population size is 10, probability of crossover is 0.8, and probability of mutation is 0.01, and b) for the next three circuits: number of generations is 100, population size is 50, probability of crossover is 0.7, and probability of mutation is 0.05. The final solution for each circuit was the best one found after a few repetitions of optimization. There were few repetitions due to the non-deterministic nature of the genetic algorithm. In Table 1 the results of the evaluation of the optimization process with the ISCAS test-benchmark combinational circuits are presented. The widely accepted ISCAS benchmark suite has been in use since being introduced in simple netlist format at the International Symposium of Circuits and Systems in 1985. In 1989 ISCAS symposium a set of sequential circuits was introduced, similar to the 1985 circuits, but with the addition of a D-type flip-flop element. These simple combinatorial circuits are used to benchmark various test pattern generation systems. (CT test patterns initialization evaluation genetic algorithm tpg configuration postprocessing Fig. 2: The optimization process All test circuits used in our evaluation were transformed by the input reduction procedure proposed in /6/. The test pattern width (denotes the number of the inputs) and the number of test patterns (number of different input test vectors to cover all possible faults) are presented in the second and the third column, respectively, for each benchmark. The next two columns present the total cost (number of equivalent gates) of the modification logic reported by Espresso for the initial and optimized TPG structure. The last column shows the achieved improvement between in- 28 G. Papa, T. Garbolino: A new Approach to Optimization of Test Pattern Generator Structure Informacije MIDEM 38(2008)1, str. 26-30 itial and optimized structure. The execution time of the GA algorithm itself was always below a second, while the evaluation phase, performed by the external structure evaluation tool, took couple of seconds per evaluation. There is no report on total execution time, which in fact was measured in minutes, but since this is off-line optimization procedure, optimization effectiveness was considered more important as optimization time. Table 1. Results of modification logic size (in total cost) test pattern width number of test patterns initial TPG optimized TPG improvement in% c432 36 27 348 280 19.5 c499 41 52 312 164 47.4 c880 60 16 536 402 25.0 cl355 41 84 584 488 16.4 cl908 33 106 2077 1840 11.4 c6288 11 12 74 49 33.8 Since the bit-order of the test patterns and the order of the test patterns in a test sequence influence the area of the modification logic, it might be interesting to compare the results also with the results of column matching algorithm /12/. Both approaches use MISR of similar complexity, while the main differences are in the design of the modification logic. Table 2 shows the results of the comparison of the two approaches for the same benchmark circuits. The complexity figures in the 2nd and 3rd columns of Table 2 are expressed in terms of a total cost reported by Espresso per bit of the produced test pattern: complexity= total cost test pattern_ width*number of test_ patterns (3) Such a measure was applied because in experiments different test pattern sets were used than those reported in /12/. Table 2. Comparison with results achieved in /12/ complexity of TPG obtained by column matching complexity of the proposed TPG obtimized by GA approach c432 0.33 0.29 c499 0.13 0.08 c880 0.38 0.35 cl355 0.19 0.14 cl908 0.29 0.53 C6288 - 0.44 The comparison presented in Table 2 indicates that the proposed approach has a higher potential to provide solutions of TPG generating deterministic test patterns than column matching. Another big difference is also in testing time; in column matching solution all deterministic test patterns are embedded in a long test sequence composed of 5000 test vectors, which contains a lot of patterns not contributing to the fault coverage in the CUT. On the other hand, the GA based solution produces all deterministic test patterns as a one short test sequence that does not contain any superfluous vectors. In Table 3 the comparison of the area of TPG logic for AMS 0.35 |im technology for the implementations reported in /2/ and the GA based solutions is presented. The area is expressed in terms of equivalent two input NAND gates. As in Table 2, a specific measure of the area overhead of the TPGs was applied due to the fact that different deterministic patterns sets have been used for TPG synthesis. The proposed measure is expressed by the following formula: area _per _bit - test_ pattern _ width * number _ of test _ patterns (4) Table 3. Comparison with results achieved in /2/ area_per bit of the TPG in ~ [2] area_per_bit of the proposed TPG obtimized by GA approach c432 0.22 0.11 c499 0.21 0.10 c880 0.19 0.29 cl355 0.20 0.09 C1908 0.19 0.32 c6288 0.24 0.54 Experimental results in Table 3 indicate that for some benchmarks the proposed TPG and the GA optimization procedure provide solutions with lower area overhead than the TPG presented in /2/ while for some other benchmarks the TPG in /2/ are better. This may be due to the fact that we used Espresso as a fast evaluation tool in the TPG optimization process and Synopsys as a tool for synthesizing the final solution. Therefore, applying Synopsys as both the evaluation tool and the final synthesis tool is likely to improve the results. The above examples are good for illustrating the advantages of the proposed approach in comparison with the existing solutions. However, one should be aware that the employed benchmark circuits are relatively small. Realistic assessment of techniques for automatic deterministic test pattern generation requires more complex circuits. Since such examples are not reported in the referred papers, we performed GA optimization approach on some larger benchmark circuits. While the results regarding the complexity and the area per bit are in average comparable to the GA examples reported above, the computation time for larger circuits considerably increases and may represent a bottleneck in practical implementations. For example, the computation time for circuit s38417 was 140 times larger than for c880. 6 Conclusion In many cases, pseudo random pattern generators provide reasonable fault coverage for different circuits-under-test. However, if a TPG fails to provide the desired fault coverage within the given test length, application specific deterministic TPGs are employed. Deterministic TPGs are by default more complex since they employ additional logic to prevent the generation of non-useful test patterns. 29 Informacije MIDEM 38(2008)1, str. 26-30 G. Papa, T. Garbolino: A new Approach to Optimization of Test Pattern Generator Structure Area overhead is one of the important issues of the design of deterministic TPGs. In this paper, a new type of deterministic TPG is presented based on a feedback shift register composed of D- and T-type flip-flops and inverters. It is also equipped with a modification logic that can invert any bit in any pattern generated by the register. The search for the optimal structure of the TPG is performed by a genetic algorithm and some illustrative case studies were performed on ISCAS test-benchmark circuits. Promising initial results have been obtained on small and medium benchmark circuits. The computation time for larger circuits considerably increases and may represent a bottleneck in practical implementations. Acknowledgment This work was supported by the Slovenian Research Agency program Computing structures and systems and the bilateral Slovenian-Polish project Development of on-line built-in self-test structures (BI-PL/03-04-012). References /1/ T. Bäck, Evolutionary Algorithms in Theory and Practice, Oxford University Press, 1996. /2/ M. Bellos, D. Kagaris, D. Nikolos, Test set embedding based on phase shifters, in Proc. Fourth European Dependable Computing Conference, EDCC-4, 2002, pages 90-101. /3/ H. Bleeker, P. van den Eijnden, F.de Jong, Boundary-scan test, A practical approach, Kluwer Academic Publishers, 1993. /4/ M. Bushnell, V. Agrawal, Essentials of electronic testing for digital, memory and mixed-signal circuits, Kluwer Academic Publishers, 2000. /5/ K. Chakrabarty, B. Muray, V. Iyengar, Deterministic built in test pattern generation for high performance circuits using twisted ring counters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, 2000, pp. 633-636. /6/ C.-A. Chen, K. Gupta, Efficient bist tpg design and test set compaction via input reduction, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, 1998, pp. 692-705. /7/ C.C. Coello, A comprehensive survey of evolutionary-based multiobjective optimization techniques, Knowledge and Information Systems, Vol. 1, 1999, pp. 269-308. /8/ F. Corno, P. Prinetto, M. Rebaudengo, M.S. Reorda, Gatto: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits, IEEE Transactions on Com-puter-AidedDesign, Vol. 15, 1996, pp. 943-951. /9/ F. Corno, P. Prinetto, M.S. Reorda, A genetic algorithmfor automatic generation of test logic for digital circuits, in Proc. IEEE International Conference On Tools with Artificial Intelligence, 1996, pp. 10-16. /10/ G. Edirisooriya, J. Robinson, Design of low cost ROM based test generators, in Proc. IEEE VLSI Test Symposium, 1992, pp. 61-66. /11/ Espresso, UC Berkeley, 1988, http://www- cad.eecs.berkeley.edu:80/software/software.html. /12/ P. Fiser, J. Hlavicka, Column matching based bist design method, in Proc. IEEE European Test Workshop, 2002, pp. 15-16. /13/ T. Garbolino, A. Hlawiczka, A new LFSR with D and T flip flops as an effective test pattern generator for VLSI circuits, Vol. 1667 of Lecture Notes in Computer Science, 1999, pp. 321-338. /14/ T. Garbolino, A. Hlawiczka, A. Kristof, Fast and low area TPG based on T-type flip flops can be easily integrated to the scan path, in Proc. IEEE European TestWorkshop, 2000, pp. 161166. /15/ D. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Addison-Wesley, 1989. /16/ Hellebrand, S., Liang, H., and Wunderlich, H. (2000). A mixed mode bist scheme based on reseeding of folding counters. In Proc. International Test Conference 2000, pages 778-784. /17/ S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers, IEEE Transaction on Computers, Vol. 44, 1995, pp. 223-233. /18/ D. Kagaris, S. Tragoudas, Generating deterministic unordered test patterns with counters, in Proc. 14th VLSI Test Symposium, 1996, pp. 374-379. /19/ M. Khalil, C. Robach, F. Novak, Diagnosis strategies for hardware or software systems, Journal of electronic testing: Theory and Applications, Vol. 18, 2002, pp. 241-251. /20/ B. Koroušic-Seljak, Timetable construction using general heuristic techniques, Journal of Electrical Engineering, Vol. 53, 2002, pp. 61-69. /21/ P. Korošec, J. Šilc, B. Robič, Population-based methods as a form of metaheuristic combinatorial optimization, Electrotechni-calReview, Vol. 72, 2005, pp. 214-219. /22/ B. Nadeau-Dostie, Design for at-speed test, diagnosis and measurement, Kluwer Academic Publishers, 2000. /23/ G. Papa, B. Koroušic-Seljak, An artificial intelligence approach to the efficiency improvement of a universal motor, Engineering applications of artificial intelligence, Vol. 18, 2005, pp. 4755. /24/ G. Papa, An evolutionary approach to chip design: an empirical evaluation, Informacije MIDEM, Vol. 33, 2003, pp. 142-148. /25/ K. Parker, The boundary-scan handbook, Third edition, Kluw-er Academic Publishers, 2003. /26/ P. Prinetto, M. Rebaudengo, M.S. Reorda, An automatic test pattern generator for large sequential circuits based on genetic algorithms, in Proc. IEEE International Test Conference, 1994, pp. 240-249. /27/ R. Singh, J. Knight, Concurrent testing in high level synthesis, in Proc. 7th International Symposium on High-Level Synthesis, 1994, pp. 96-103. /28/ C. Stroud, A designer's guide to built-in self-test, Kluwer Academic Publishers, 2002. /29/ N. Touba, E. McCluskey, Bit-fixing in pseudorandom sequences for scan BIST, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol. 20, 2001, pp. 545-555. /30/ A. van de Goor, Testing semiconductor memories: theory and practice, John Wiley & Sons, 1991. Gregor Papa Jožef Stefan Institute Computer Systems Department Jamova c. 39, 1000 Ljubljana, Slovenia tel. +386 1 4773 514 fax. +386 1 4773 882 Email: gregor.papa@ijs.si Prispelo (Arrived): 28.06.2007 Sprejeto (Accepted): 28.03.2008 30 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana TWO OPTICAL RING COMMUNICATION BETWEEN POWER ELECTRONIC BUILDING BLOCKS: A CASE STUDY Žarko Čučej, Karl Benkič Univerza v Mariboru, FERI fakulteta, Maribor, Slovenia Key words: communication, power electronic building block, control Abstract: Power electronic building blocks initiated and sponsored by the Office of Naval Research, are based on the integration of power semiconductor elements with some degree of intelligence and data communication capability in compact form. This article addresses the communication issues of power electronic building blocks. After brief overview of common used topologies in power electronic building blocks there is an analysis of requirements of communication between power electronic building block and detailed description of case of the two-optical ring communication topology with schemas for of complete implementation of slave nodes in a single FPGA circuit. Komunikacija dvojnega optičnega obroča med gradniki močnostne elektronike: študija primera Kjučne besede: Komunikacije, gradniki močnostne elektronike, vodenje Izvleček: Gradniki močnostne elektronike, ki jih je vpeljala in sponzorirala ameriška vojna mornarica (Naval Research Office) temeljijo na integraciji močnostnih polprevodnikov z določeno stopnjo inteligence in sposobnostjo prenosa podatkov v kompaktni obliki. Članek se osredotoča na komunikacijo med gradniki močnostne elektronike . Po kratkem pregledu najbolj pogosto uporabljenih topologij v gradnikih močnostne elektronike naredimo analizo komunikacijskih zahtev med gradniki močnostne elektronike. Nadaljujemo z detajlnim opisom primera topologije dvojnega optičnega obroča in podamo sheme za implementacijo enot tipa suženj v FPGA vezju. 1. Introduction Recently the development of the electric power supply systems as well as power supply equipment are directed toward miniaturization (doable with new semiconductor materials and use higher switching frequencies) and distribution/integration of supply sources with their loads enabling optimization of their joint features or achieve other desirable features as reliability, survivability, low cost production etc. This new design paradigm, the first time clearly exposed by of the Office of Naval Research initiation for development of power electronic building block (PEBB), anticipate that each PEBB will have standardized input/output connections, some smartness enabling safe control, state observation with power electronics hardware managing, and software determination of their function/behavior. Further, introduction of digital communication ability between PEBBs and master or distributed control system open new bunch of operabilities for new developments, research and sophisticated solutions yet not imaginable /1/, /2/, /3/, /4/, /5/. 1.1 The most common PEBB topologies Basic switching element in PEBB is half power switching bridge usually schematically presented independently of used switch technology by symbol for switch (Fig. 1). The PEBB also can be consisted from main power half bridge switch and auxiliary half bridge for so call zero-voltage or zero-current switches. 'out (a) half bridge 'OUt (b) ZCS switch Vb Vr (c) bridge (d) 3-phase bridge Fig. 1: The most common topologies of switches in PEBB 31 Z. Cucej, K. Benkic: Two Optical Ring Communication Informacije MIDEM 38(2008)1, str. 31-35 Between Power Electronic Building Blocks: A Case Study 1.2 Universal PEBB Controller Replacing control signals with digital communications lead to use of digital controller. This now can be universal and can be easily adapted to application with adequate algorithm software /1/, /3/, /4/. The switching frequencies of today's medium power converters already cross a switching frequency of over 100 kHz and the recent development of fast semiconductor switches and converters' topologies shows that, in the near future medium power PEBBs will cross at a class higher switching frequency, consequently the controller as well communications connecting them to power switches should be capable to perform their tasks in 10 ^s sample intervals. To copy with this it is sensible to use cascade control structure and divide task on high speed inner control loop and lower speed outer loop (Fig. 2). PEBB data acquisition in PEBB high rate cyclic data acyclic and slow rate cyclic data exchange exchange UPC inner loop control fraction of outer loop control sample interval Ts Fig. 2: Sample interval sharing between inner control algorithm, data acquisition and cyclical data communication. The outer control algorithm can be distributed over a number of cyclical data communication intervals. Determining sample interval share for fast cyclic communication depends on the number of PEBB's linked by IPC, the kind of PEBB (for example direct controlled, PWM controlled) and a reasonable cost for communication hardware. Similarly, the duration of inner loop algorithm execution should be longer than data acquisition in PEBB. 1.3 Communication issues The systems and equipment built-up with PEBBs, according to control and design strategy requires up to three levels of communication: 1. PEBB internal high speed serial communications connecting local Hardware Management Logic (HML) with PEBB components as analog-digital converters, timers, protection logic circuits etc, 2. fast local network linking PEBB's and central controllers, i.e. Inter-PEBB Communication (IPC), and 3. a local area network connecting equipment or systems based on PEBB to some central supervisor and monitoring system. The major requirement for the first two communication levels is hard real-time /8/, /9/, /10/. This means that the data has to be correct in time, as well as in content. Any failure in both demands can lead to catastrophic events hazardous to devices, systems or even users. Therefore the requirements for IPC are: 1. deterministic, 2. immune to the disturbance, crosstalk, and interference as much as possible on the physical level already, 3. capable of allowing the diverse IPC traffic needed for normal PEBB functioning, support reconfiguration of PEBB, monitoring of PEBB states by boundary scan, etc, 4. capable to adopt to different control strategies of PEBB output voltage strategies (using pulse-width modulation or use of variable structure control approach with direct switch state control) 5. reliable, scalable, and survivable. Analysis of enumerated requirements shows that the communication on one hand should be implemented in hardware and used optical fiber(s) for transmission media and on another hand to be adaptable to different control strategies and with this to be adaptable to different data formats. 2. A case study The starting point of the case study was an existing IPC based on MACRO protocol /5/. From it the master/slave concept was preserved. The physical layer was enriched with the second optical ring with traffic direction opposite to the direction in the first ring (Fig. 3). Function of TAXI chips with the latter described extensions was implemented in FPGA (consequently achieved data rate on one ring due to speed limitation of used FPGA was reduced to 25 Mbit/s). New synchronizer was developed, as well as a function for topology reconfiguration. Besides this the new frame organization, forward error coding scheme, and the simplification of those protocols implemented in slave node, i.e. in a PEBB, were tested. ■ ring 1 ■ ring 2 UPC master node • ring 2 ■ ring 1 slave node 1 PEBB 1 slave node 2 PEBB 2 slave node n 1 slave node n PEBB n -1 PEBB n Fig. 3: IPC with two active optical ring topology. Two optical rings topology gives opportunities as doubling the maximal number of PEBBs, or halving the sampling interval, and thus doubling the total switching frequency or halving the one ring IPC bit rate and not on the end gives very desirable reliability, scalability, and survivability. From the aforementioned possibilities, the following are consid- 32 Z. Cucej, K. Benkic: Two Optical Ring Communication Between Power Electronic Building Blocks: A Case Study Informacije MIDEM 38(2008)1, str. 31-35 ered in the case study: - reconfiguration of two-ring topology in one sample interval, - doubling the number of PEBBs in an IPC, - locally performed synchronization, which is based on measurements of the frames' propagation times. Besides the aforementioned, the structure of all frames was revised in comparison to known solutions /7/ for better utilizations of sampling intervals. 2.1 Frames All frames have fixed length and are in the cyclic traffic send in convoys (Fig. 5). Data (i.e. information) frames (Fig. 4a), in short I-frames, contain two 16-bit long slots, which enables UPC to send two words of switch on/off occurrence data and, at the same time, to collect the same amount of fast changing measured data in PEBB. Two slots follow FEC which contain Bose-Chodhuri-Hasquenghen parity code generated by generator polynomial x8+x2+x+1, the same as used in ATM /6/. Parity bit gives enough redundancy for correction 1-bit error and discovering any 2bit error and 8-bit burst error. The second slot also contains the address of PEBB, which is superimposed on the data. This additional PEBB address serves many purposes, as described later. convoy of frames for cyclic data 16 16 data 1 data 2 + address FEC (a) data frame 8 8 16 8 flag n data + address FEC (b) supervise frames Fig. 4: Formats of frames (before 4B/5B encoding). Supervise frames (Fig. 4b), in short S-frames, have the same size as I-frames. Instead of the first data slot they have an 8-bit long flag with repeated 4-bit code with a type of S-frame (Table I). The 8-bit field is followed by the number of I-frames. Table I: S-frames. from UPC to PEBB from PEBB to UPC Start of Convoy Sample Instant Synchronization Master Reset Initialization Discover node Acknowledge Switching Error Synchronization Mismatch Broken Ring During the cyclical data exchange, the data frames are sent in a convoys started with S-frame Start of Convoy as head and followed by I-frames in opposite order to PEBBs down the ring and with S-frame Sample Instant Synchronization as a trailer. The gap between the trailer and the end of sample interval is padded with padding bits (Fig. 5). sampling instant data frames SoC LRI n/2 SIS pad Fig. 5: Structure of convoy. SoC: S-frame Start of Convoy, LRI: low rate I-frame, SIS: Sample Instant Synchronization, pad: padding bits. The data frame numbers are equal to the position of slave nodes in the direction of the convoy propagation down the optical ring. 2.2 Transceiver circuit in the slave nodes The core of IPC is transceiver circuit (Fig. 6). It is the same in slave and in the master nodes. Designed is FPGA and it enables wire speed detection of S-frames. Since the data frames travel in convoy with the SoC frame as header and the SIS frame as trailer, it is easy to determine those time slots in when ADM in particular PEBB's nodes copy data on the ring into the receiver shift register, and simultaneously, replace this data with their own. Slots are determined by the cyclical data frame counter and slot decoder, which is configured during the initialization phase using S-frame Discover node. CDFC socî 40 bit data frame, Rx SRi MR, INT, Discover I sisj. decoder: - 5B -> 4B - S-frames ring 1 time slot dekoder I Tx pass , S R q q Rx: 5-bit SR Tx: 5-bit SR encoder 4B -» 5B 40 bit data frame, Tx SR slow rate cyclic data requested L ADM <1 ring 1 out Fig. 6: Principle of innovative transceiver circuit in the first ring. CDFC: Cyclic Data Frame Counter, ADM: Add Drop-a-way Multiplexer. 2.3 Synchronization The key problem in IPC is determining and maintaining sampling instants' synchronization in each PEBB. Synchronization is based on the measurement of time difference between SIS frame recognition instant in frame convoys which are simultaneously transmitted, each on its own ring. Since convoys propagate in opposite directions down the ring, both SIS frames pass each other close to midway. At this point the time difference between them is zero. At each other slave node this difference is twice the offset gap between the SIS frame recognition instant, and the sampling instant. This gap is padded with padding bits (Fig. 5). 33 Informacije MIDEM 38(2008)1, str. 31-35 Z. Cucej, K. Benkic: Two Optical Ring Communication Between Power Electronic Building Blocks: A Case Study Synchronization is performed by two counters, one buffer, a comparator, and two pre-scaler counters (Fig. 7). Counter 1 serves for determining the gap between the occurrence of synchronization frame detection and sampling instant, the second counter serves for measuring frame propagation time. It has a complex structure, because, for the sake of generality, it can determine half and full differences between both frames' convoys, and also supervise if a ring is broken. The measured difference is stored in a buffer since it is used for the next sampling interval. The buffer also stores data from this SIS frame, which determines ratio VCO clock/bit rate (*2,x4,x8,x16) and the ratio between the measured time difference of SIS frames, and the gap to sampling instant (can be 1:1 or 2:1). Blocks "pad" and "pre-scaler" PS2 serves for adjusting padding bits. When resetting PS2 the first padding bit width is adjusted such that any jitter of sampling instants is minimized. The amount of jitter depends on the accuracy of the difference measurement, i.e. from ratio VCO clock/ bit rate. If this ratio is 2:1, then the jitter is less than ± 0.0005 %, in the case of 16:1 it is improved to ±0.00006 %. Since only the length of the first padding bit in the sample interval can vary, this does not disturb the bit synchronization very much. data to sync ^rame_ data from sync frame VCO counter 1 I comparator PS n n/2 buffer select n- 1 counter 2 reset —t sample instant n/ 2 »/2 alert • ring broken , nng broken stop, SIS 2 start, SIS 1 PS * pad padding bits Fig. 7: Scheme of synchronizer. For meaning of label see text below. 3. Traffic IPC traffic constitute: - Connectionless cyclic data exchange, which in regular sample intervals deliver switching commands to the PEBB and collect data in acquired in them. - Connectionless acyclic data with confirmation for irregular events and starting initialization. Both traffic flows are in transmitter handled on the same way. In wire-speed the data ere exchanged between rings and PEBBs' nodes. 3.1 Acyclic traffic Acyclic traffic is used on two occasions: 1. during the initialization phase, 2. When an irregular event in PEBB happens. During the initialization phase, the traffic is initiated and controlled in a master/slave fashion by UPC. Among the S-frames used for initialization are master reset, Initialization, Discover node, Acknowledge and Sample Instant Synchronization. When collecting irregular events, UPC, in the sample subin-terval intended for acyclic traffic, successively sends empty frames Switching Error (SE) and Synchronization Mismatch (SM). These frames in the data field carry a set of 16 flags, each assigned to one PEBB. If the PEBB experiences this failure, PEBB's nodes set-up an assigned flag to it. If there are more than 16 PEBBs connected in one ring, they are segmented into groups of 16 PEBBs and the groups are assigned within the field n. A broken ring is signaled by S-frame Broken Ring (BR) on the second ring, immediately after detecting ring breakdown. Apparently, the broken ring is detected successively in all nodes after failure (in the second ring direction) on the ring. For resolving possible collision and for detecting the place of failure, BR frames are sent successively as long as that slave nodes from the master node receive: - ACK frame with instructions/confirmation for reconfiguration two-ring network into two one-ring networks, or - MR frame with request to shutdown the PEBB (all switches go to the off-state) A collision arises if the next node detects a broken ring before it detects the arrival of a BR frame from a node closer to failure. In this case the signal alert rings broken in nodes activate sending their BR frames, which is discontinued by detection of the incoming BR frame. With detection of an incoming BR frame, the flag ring is broken before previous node, is set. This flag after momentarily sending of BR frame heading prevents any further sending from this node (Fig. 8). Consequently, the master node rich least one complete BR frame header, which on its way to the master node set in the all passed slave nodes the flag ring is broken before previous node. This procedure cleanup the ring for the BR frame from node which is closest to the ring failure. BR frame header, which on its way to the master node set in the all passed slave nodes the flag ring is broken before previous node. This procedure clean-up the ring for the BR frame from node which is closest to the ring failure. Frames received without errors or with one error corrected by FEC, are acknowledged by the ACK frame in a packet of up to 16 data frames, following the initialization frame. Under normal circumstances the IPC is set-up during the design of PED/PES. For the sake of reliability at the fault 34 Z. Cucej, K. Benkic: Two Optical Ring Communication Between Power Electronic Building Blocks: A Case Study Informacije MIDEM 38(2008)1, str. 31-35 received RB frame stop, SIS 2 S R Q Q RiBBPN iZ alert ring broken <1 S R Q Q decoder ring 1 |—>T Rx: 5-bit SR | 8-bit delay 50 bit SR with 4B/5B encoded RB frame < 1 ring 2 out Fig. 8: Block scheme of transceiver circuit parts in the second ring involved in physical protocol "Broken Ring". RiBBPN: flag "Ring is Broken Before Previous Node", SR: Shift Register, E: enable. tolerant design of PED/PES, the PEBB's nodes support reconfiguration, in the case of ring break as described in section 3-A, as well as the auto- configuration of IPC at the initialization of the communication system. 3.2 Initialization Initialization has two parts: 1. initialization of PEBB 2. auto-configuration of communication system Slave nodes executes initialization of equipment or system consist of PEBBs by delivering the received initialization data into the PEBB control registers, reading PEBBs' status registers, and supporting acknowledged connectionless services of the acyclic data transfer. The main goal for the auto-configurations of PEBB's nodes is the determination of the nodes' serial order in the optical ring. This procedure has two steps. In the first step, the master node in the UPC sends S-frame "Discover node", which activates the automaton for setting-up the decoder for read or setting the flags in the S-frames (in accordance with a node place in the ring), in the second step the master node successively sends the logical addresses of the nodes by frame pairs 'Discover node" and I-frame. In the S-frame's data field node is assigned by its place in the ring, and in the followed data frame the data slots contain the nodes' logical addresses, determined by the master node. Two-ring topology compensates for the double cost of transmission media and the necessary electro-optical couplers with high value benefits such as: - enabling independent self synchronization in each node on IPC - higher reliability and survivability of PED/PES From the performed simulations in VHDL and the implemented parts of IPC, it can be concluded that, today, FPGA enables the building up of compact IPC slave nodes with integrated HML functions, in a single chip. References /1/ D. Borojevic: "Some Control, communications, and modeling issues for PEBB-based power distribution systems", white paper, presented as part of the Control and Intelligent Systems Control Panel, 1995 /2/ J. Borraccini, R. Cooley, M. Cannell, D. McLaughlin, D. Flamm, T. Duong, S. Lane, D. Borojevic: "PEBB Controller Interface". http:/ /www.pebb.onr.navy.mil/techpapr.nsf /3/ I. Milosavljevic: "Power electronic system communications" MSc. thesis, 1999, Virginia Tech, Blacksburg, http:// scholar.lib.vt.edu/theses/available/etd-021299-141947/unre-stricted/IMTHESIS.PDF /4/ Z. CUCEJ: Power electronic building blocks: a survey. Inf. MIDEM, 2001, letn. 31, st. 2, str. 94-101. /5/ Z. Cucej: "Power electronic building blocks: communication issue". Proceedings of Int. conference Elmar 2003, Zadar, 2003 /6/ W. Stalings: Network standards, Addison-Wesley, 1996 /7/ G. Francis, R. Burgos, F. Wang, D. Boroyevich: "A Universal Controller for Distributed Control of Power Electronics Conversion Systems, Proceedengs IEEE COMPEL 2006. /8/ Rodd: "Communications for real-time Industrial Control: The Design Issues". Dept. of Electrical & Electronic Engineering, University College of Swansea, UK /9/ I. Torngren, U. Backman: "Evaluation of Realtime Communication Systems for Machine Control", DAMEK mechatronic group, Dept. of Machine design, The Royal Institute of Technology, Stockholm, Sweden /10/ D. Decotignie, P. Plaeinevaux: "A survey of industrial communication networks", Swiss Federal Institute of Technology (EPFL), Lausanne, CH, in Ann. Telecommun., 48, no.9-10, 1993 /11/ Delta-Tau Data Systems, Inc.: Motion and Control Ring Optical, Specification. http://www.macro.org,May 1998. /12/ Taxi chip: CY7C9689A Datasheet, Cypress, 2003. http:// www.cypress.com / products/ datasheet.cfm?partnum=CY7C9689A-AC 4. Conclusions IPC is very demanding at function execution times, consequently communication protocols have to be executed at so-called wire-speed at a bit rate of a least 100 Mbit/s. Therefore, all functions are simplified as much as possible and implemented by automaton, counters and registers like to physical protocols in ISO/OSI model. It can be easy implemented in FPGA. Žarko Čučej, Karl Benkič Univerza v Mariboru, FERI fakulteta, Smetanova 17, 2000 Maribor zarko.cucej@uni-mb.si karl.benkic@uni-mb.si Prispelo (Arrived): 26.09.2007 Sprejeto (Accepted): 28.03.2008 35 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana ROBOTIZACIJA PROIZVODNJE - ROBOTSKO SESTAVLJANJE Saša Klampfer, Boris Curk Fakulteta za elektrotehniko, računalništvo in informatiko Kjučne besede: robotizacija, sezor Banner T18, prijemalo, model lesene hiške, tekoči trak, robotski krmilnik, vodenje po položaju in sili, robotsko pobiranje, robotsko sestavljanje. Izvleček: V članku predstavljamo princip prepoznavanja, pobiranja, odlaganja in sestavljanja elementov lesene otroške hiške. Na kratko želimo predstaviti vzroke problematike robotskega sestavljanja in uporabljene rešitve, ki so pripomogle k rešitev problematike sestavljanja. Za lažjo predstavo smo izvedli primerjavo uporabljenih rešitev s tistimi, ki se v industriji uporabljajo kot profesionalne rešitve. Robotization of manufacture yield - constructing with robot Key words: robotization, sensor, grasper, wood house model, microcontroller, servofloat. Abstract: Robotics is fast growing area, which achieves full bloom in last teen years. Now days, manipulators are indispensable part in industry. We use them for weld chassis, for steel and wood cultivation, for disperse coloring, steel cutting and so on. Since 1992, for each year, number of robots rapidly increases. Reason for that is their universality, but because of that property, people start initiates them into farms, agricultures, green houses, warehouses, into electronics production for composing electronic components... Today, robots using area expands wide around, specially to our homes. Basically view, represent robot as movement machine or automatic machine with more free programmable axels, in some cases in combination with sensors or computer vision. Our system consists with seven basic parts: the first one is operator and then follows programming device, microcontroller, robot hand, grasper, sensor and round movement ribbon. The main goal of this project is to incorporate all basic parts in to working process for composing elements of woody children house. Second section in this article represents components, which are extremely important when we initiate robotization into industry. Here belong criteria, like choosing real and successful first application, choosing right robot, production speed, time requirements for implement equipment, and complexity of automation. In third section we made case study of hold comparison between human and robot, which is very important for understanding, how servofloat function work. Fig. 1 shows round movement riboon, with basic parts on taking away place. Servofloat function is described in session six. Fig. 3 represent barrier on trajectory between step 1 and step 2. With servofloat function can robot avoid this barrier and jump directly over shortest path to step 3. Chapter four give us some information about IR sensor, and basic work principle for light and dark places recognition. Table 1 shows possible combination, when we recognized parts of house, and Fig.2 shows basic principle of component recognition. Section five describes constructing algorithm procedure, where table 2 and their indicators illustrates course of construction phase. Chapters seven and eight are purposed for discussion about picking up elements from moving round ribbon and taking off the same elements on composing place. In this two sections we try to find answers on our problems, and solve them completely with suggest simple solutions. Fig. 4 under seven section illustrates left side element on round ribbon palette. Fig. 5 is placed in eight section, where illustrates decreasing tolerance between both big side elements. Under same section, Fig.6 illustrates cultivated bottom side of the smallest side element. Section 9 concludes the paper. 1 Uvod Robotika se je v zadnjih desetletjih pojavila in utrdila v številnih industrijskih procesih v obliki moderne, ekonomične in človeku prijazne tehnologije. Robotski manipulatorji so nepogrešljivi del pri varjenju avtomobilskih ohišij, vstavljanju obdelovancev v stiskalnice, razpršilnem barvanju, služijo pa lahko tudi kot paletirni pripomoček oziroma kot manipulatorji za razrez, sestavljanje itd. Prav nobeno izjemo ne predstavljajo kirurški roboti ali servisni mobilni roboti, kateri so dandanes v veliko pomoč pri raznoraznih opravilih. Cilj je usmerjen v postavitev in zagon proizvodne linije za sestavo lesenih hišk, kjer sestavni deli prihajajo na paletah, po tekočem traku, do mesta odjema, kjer se vrši prepoznava sestavnih delov s pomočjo infra-rdečega tipala. V navezi z logiko prepoznavanja se ustrezni element prenese na površino sestavljanja, v kolikor slednji ne ustreza zaporedju, se odpelje po traku naprej. Osnovna tematika projekta temelji na prepoznavanju in prijemanju objektov, kjer igrajo pomembno vlogo tolerance. Sestavni gradniki hiše so oblikovani z obdelovalnimi stroji, ki imajo natančnost do enega milimetra, včasih celo več. Na drugi strani pa pri sestavljanju uporabljamo manipulator, ki je natančen do desetinke milimetra. To pomeni, da moramo najti most med dvema svetovoma z različnimi natančnostmi. Takšen most ponazarjajo predstavljene možne rešitve v tretjem poglavju, s katerimi lahko delno ali v celoti rešimo omenjeno problematiko. S tem smo želeli pokazati, na kakšen način lahko združimo povsem različna svetova, ob enem pa prejmemo rezultate, ki smo si jih na začetku le želeli. Razlog združevanja dveh povsem različnih svetov gre pripisati obstoječi opremi, ki je v laboratoriju na razpolago, s čimer lahko damo poudarek področjem, ki marsikateremu v začetku izvajanja podobnega projekta niso opazna. Drugo poglavje je namenjeno predstavitvi najpomembnejših komponent, katere upoštevamo pri uvajanju robotizac- 36 S. Klampfer, B. Curk: Robotizacija proizvodnje - robotsko sestavljanje Informacije MIDEM 38(2008)1, str. 36-41 ije. V četrtem poglavju predstavljamo študijo prijema pri človeku in stroju, v petem princip snovanja algoritma in v šestem način vodenja po položaju in sili. Sedmo in osmo poglavje ponazarjata metodologijo pobiranja in odlaganja elementov modela lesene hiške. Sklepi, spoznanja in zaključne misli, podane v devetem poglavju, zaključujejo raziskovalno delo. 2 Komponente, ki vplivajo na uvajanje robotizacije V primeru odločitve o robotizaciji posamezne delovne naloge, ali že obstoječega ročnega delovnega mesta, moramo biti pozorni na naslednje pomembne komponente: - Izbira prave in uspešne prve aplikacije. Ne smemo izbrati prezahtevno nalogo, saj morda tehnično in kadrovsko ne bomo kos reševanju naloge. Izogibaj-mo se aplikacij, ki so zahtevne že same po sebi. - Izbira in določitev robota (manipulatorja), ki bo najbolje zadostil našim zahtevam. Ko imamo enkrat določeno nalogo, moramo izbrati optimalni tip manipulatorja. Ne smemo pozabiti na zahtevano število prostostnih stopenj, obliko delovnega prostora, obliko in lastnosti nameščenega orodja ali prijemala, nosilnost ("bruto" teža). - Kompleksnost avtomatizacije (enostavnejša kot je realizacija večji je zaslužek). Ne pozabimo na dejstvo, da preproste rešitve vodijo k lažjemu obvladovanju situacije in s tem posredno k manjšim stroškom zagona in vzdrževanja. - Hitrost proizvodnje (roboti delajo načeloma počasneje kot človek, vendar bolj enakomerno). V praksi obstajajo različne metode za ocenjevanje potrebnega časa posameznih operacij. Pozorni moramo biti na ozka grla, ki nam kasneje omejujejo proizvodne sposobnosti. - Eden izmed pomembnejših ciljev (ni potrebno, da je ravno glavni) je ekonomska upravičenost. Z robotizacijo seveda pričakujemo pozitivne učinke v smislu večje produktivnosti, manjšega izmeta, kvalitetnejših izdelkov itd. - Časovno trajanje uvedbe (menjava proizvodnega programa). V fazi študije je potrebno predvideti, kolikšna bo delovna doba delovanja. To obdobje igra ključno vlogo pri amortizacijo vloženih sredstev. - Prva namestitev (izkaže se, da je najboljši strokovnjak najcenejši). Brez ustreznega kadra se je težko lotiti takšnega projekta. Tudi če kupimo robotsko celico od dobavitelja na ključ, bomo potrebovali domači tehnični kader za vzdrževanje in odpravo napak. Robot, ki ne opravlja svoje funkcije, je nekoristen. - (Ne)naklonjenost okolja (ljudje se pritožujejo in sabotirajo robote). Posebej v okoljih, kjer niso vajeni delati skupaj z roboti, lahko pride do pritožb in strahu pred njimi. Pomembno je, da pri uvajanju robotov ne zanemarimo ta psihološki vidik. 3 Prijem pri človeku in stroju Ker se pri robotizaciji v veliki meri ukavarjamo z prijemi, Vam želimo v okviru tega poglavja predstaviti študijo prijema. Študija prijemanja z roko pri človeku, in neposredna primerjava z robotskimi prijemali je pomembna na številnih področjih. Tipičen primer je rehabilitacija roke, kjer nas zanima ocenjevanje funkcionalnosti le-te, ter povrnitev gibov ohromele roke. Ključno področje predstavlja interakcija človeka z računalnikom, kjer se uporabljajo namenski uporabniški vmesniki (haptične naprave) za delo v navideznem okolju. V industrijskem okolju se srečujemo z robotskimi mehanizmi, ki za prijemanje predmetov uporabljajo različna robotska prijemala. Slednja so lahko enostavna dvo-prstna, katero tudi sami uporabljamo, pa vse tja do spret-nejših in kompleksnejših več-prstnih prijemal. Slika 1. Krožni tekoči trak s pozicionirnim čepom, čepom za ustavljanje palet in senzorjem prisotnosti palete na odjemalnem mestu Fig. 1. Round movement ribbon with position bung, presence sensor and blockade for stopping paletts 4 Opis uporabljenega tipala in princip prepoznavanja objektov Način prepoznavanja objektov temelji na infrardečem tipalu Banner T18. Tipalo je nameščeno na nosilec, ki se nahaja na koncu robotske roke (manipulatorja). Tipalo je sposobno zaznavati svetla in temna področja. To pomeni, da svetlo območje ovrednoti z logično vrednostjo 1, temno območje pa z logično vrednostjo 0. Razločevanje med svetlim in temnim področjem temelji na principu količine odbite svetlobe. Kot primer vzamimo beli in črni list in ga primaknimo pod tipalo. Beli list veliko močneje odbija (sipa) svetlobo v primerjavi s črnim, ki velikšen del IR-žarka vpije, preostali del pa odbije nazaj v smeri proti tipalu. Del žarka, ki se odbije od površine moramo ponovno s površino tipala ujeti, kar pomeni, da mora površina tipala pri odčitavanju ležati vzporedno z odbojno ploskvijo. S tem zagotovimo, da žarek vpada na površino pod pravim kotom (popolni odboj). Ker moramo s slednjim prepoznati vsaj pet osnovnih elementov, v resnici jih je šest, le da sta srednji stranici identični, bo potrebno uporabiti za prepoznavo enega elementa vsaj tri bite oziroma logične vrednosti. 37 Informacije MIDEM 38(2008)1, str. 36-41 S. Klampfer, B. Curk: Robotizacija proizvodnje - robotsko sestavljanje Uporabljeni deli so ovrednoteni z barvnimi kombinacijami, ki hkrati predstavljajo ekvivalentne kombinacije logičnih nivojev. Vrednotenje je ponazorjeno v tabeli 1: Tabela 1: Prepoznane barve ovrednotene z logičnimi vrednostmi Prepoznane barve ovrednotene z logičnimi vrednostmi 0 0 0 Prazna paleta 0 0 1 Desna velika stranica 0 1 0 Majhna stranica 0 1 1 Napaka 1 0 0 Leva velika stranica 1 0 1 Dno hiške 1 1 0 Napaka 1 1 1 Streha Tretja točka Druga točka Prva točka odčitavanja odčitavanja odčitavanja (primer-temno) (primer-temno) (primer-svetlo) Slika 2. Postopek prepoznave sestavnh elementov Fig. 2. Basic principle of component recognition Na sliki 2 je prikazan osnovni princip prepoznave elementov s pomočjo infrardečega tipala. Glede na to, da je tipalo nameščeno na manipulator, je potrebno definirati tri točke, ki so znotraj območja nosilne palete, v katerih tipalo odčita vrednost. Na osnovi dobljene bitne kombinacije, ki jo sestavljajo trije biti, dobimo informacijo za kateri element v resnici gre. Točke se definirajo na trajektoriji giba manipula-torja, ki poteka nad paleto (pravokotno na postavljen element), tipalo pa odčita vrednost v definiranih točkah brez ustavljanja. Vrednosti, ki jih navaja Tabela 1 ponazarjajo kombinacijo za vsak posamezen sestavni element, razen dveh kombinacij, ki vsebujeta po dve enici. Takšni kombinaciji sta nedovoljeni, saj nimamo nikdar na eni paleti tekočega traku po dva elementa. Če se povrnemo na sliko 2, bi kombinacija (1, 1, 0) pomenila, da se na paleti nahajata leva velika stranica in majhna stranica na sredini palete. 5 Snovanje algoritma Pri izdelavi algoritma robotskega krmilnika NX100 si pomagamo z diagramom poteka, ki nam pomaga grafično ponazoriti posamezen korak. Diagram poteka nam predstavlja temelj, iz katerega začnemo snovati algoritem po metodi »top-down« (od zgoraj navzdol).Algoritem mora biti čimbolj enostaven, hiter in razumljiv, saj lahko le na ta način zagotovimo brezhibno delovanje, in se hkrati izognemo nepotrebnim pogojnim stavkom. Program smo gradili modularno, kar pomeni, da smo najprej zapisali strojno kodo za prepoznavanje in prijemanje elementov, ter šele nato, ko je ta delovala brezhibno, prešli na snovanje drugega dela algoritma, ki je namenjen sestavljanju elementov. Za izvajanje naloge sestavljanja moramo imeti na voljo povratne informacije o prisotnih elementih na mestu sestavljanja. To pomeni, da moramo v pomnilniške lokacije krmilnika NX-100 shraniti informacijo o stanju na gradbišču (mestu sestavljanja), saj lahko le na takšen način robotu povemo, katere manjkajoče elemente še lahko vzame na odje-malnem mestu iz tekočega traku. Da bi bila zadeva čimbolj preprosta smo postavili pet spremenljivk z oznakami D001, D002, D003, D004, D005 katerim se bodo prirejali indikatorji. Stanja spremenljivk prikazuje tabela 2. Tabela 2: Pomen indikatorjev, ki jih lahko posamezne spremenljivke zavzamejo ID0001 0 Prazno aradbišče 1 postavljeno dno 2 Dostavljeno dno + obe veliki stranici 3 postavljeno dno + obe veliki stranici + obe mali stranici 4 postavljeni vsi deli ID0002 0 ni nobene velike stranice 1 Dostavliena LEVA velika stranica ID0003 0 ni nobene velike stranice 1 Dostavliena DESNA velika stranica ID0004 0 ni nobene male stranica 1 Dostavliena ZADNJA mala stranica Pomen spremenljivk je naslednji; v kolikor je D0001 na vrednosti 0, je gradbišče prazno. To izda povelje, da mora manipulator poiskati dno hiše, kajti brez njega gradnje ne more pričeti. V trenutku, ko slednjega najde, poveča indikator na vrednost 1, s čimer sporoči da ima dno, hkrati pa takšna vrednost predstavlja pogoj za izvedbo drugega koraka v algoritmu. Ta korak je iskanje leve in desne velike stranice, za kateri ima rezervirani spremenljivki D0002 in D0003. V kolikor sta obe spremenljivki na vrednosti 0, bo manipulator začel iskati eno izmed njih (prvo, ki pride). Predpostavimo da je najprej našel levo in postavil indikator D0002 na vrednost 1, kar izda pogoj za iskanje desne velike stranice. Ko najde še to, postavi spremenljivko D0003 na vrednost 1, in ker sta sedaj obe spremenljivki na 1, se lahko vrednost D0001 poveča na 2. Podobno kot prej predstavlja to pogoj za izvedbo koraka iskanja malih stranic. Ko manipulator najde obe, in jih seveda uspešno postavi na svojo lokacijo, lahko ponovno inkrementira spremenljivko 38 S. Klampfer, B. Curk: Robotizacija proizvodnje - robotsko sestavljanje Informacije MIDEM 38(2008)1, str. 36-41 D0001. Ko je slednji enak 3, se izvrši funkcija za iskanje zadnjega elementa (streha). V trenutku, ko je zadnji element uspešno postavljen na gradbišče, se D0001 postavi na vrednost 4, kar pomeni da je hiša sestavljena. Po izteku časa časovnika dveh sekund, se vsi indikatorji postavijo na vrednost 0, postopek sestavljanja nove hiše pa se lahko prične. Časovno obdobje dveh sekund je potrebno zagotoviti iz dveh razlogov, kjer prvi predstavlja varnostni razlog, drugi pa čas, ki je potreben, da se gradbišče sprazni. 6 Vodenje manipulatorja po položaju in sili (ang. servofloat) Robotski mikrokrmilnik NX-100 nam omogoča vključitev funkcije vodenja robota po položaju in sili na dva načina. Sem spadata »link servofloat function« in »linear servofloat function«, kjer prva možnost nudi nadzorovanje navora nad vsako posamezno osjo posebej, medtem ko druga možnost nudi nadzorovanje navora nad trenutnimi koordinatami. Glede na potrebe pri izvajanju posamezne aplikacije izberemo ustrezno možnost. »Link servofloat function« omogoča vodenje po položaju, in vodenje po navoru (sili). V kolikor posamezna zunanja sila prepreči operiranje manipulatorja po vnaprej predvideni poti, slednji ne bo dosegel zadanega položaja. To velja za primere kjer je vključeno vodenje po položaju in sili. Kadar manipulator ne more doseči predvidene pozicije zaradi delovanja zunanje sile (ovire ipd.), slednji izvrši naslednjo instrukcijo. Takšen primer nam prikazuje slika 3, kjer je manipulator med obratovanjem naletel na nepredvideno oviro. Slika 3. Ovira na poti trajektorije od koraka 1 do koraka 2, ki spremeni smer gibanja do končnega cilja Fig. 3. Barier on trajectory between step 1 and step 2. With servofloat function can robot avoid this barier and jump directly over shortest path to step 3 Na preprostem primeru, ki je prikazan na sliki 3 uporabljamo zgolj linearne gibe med določenimi točkami, kjer imamo vključeno funkcijo vodenja manipulatorja po položaju in sili. Manipulator se začne premikati v smeri iz točke 1 v točko dva, kjer po treh sekundah naleti na oviro. V istem trenutku se ob nasprotno delujoči sili ustavi, ter ostane v zaustavljenem položaju preostali dve sekundi. Po izteku skupnega časa petih sekund se manipulator sam prestavi v korak 3, vendar zaobide korak 2, ki ga zaradi nameščene ovire ne mora doseči (izvede naslednjo instrukcijo). Naslednjo instrukcijo lahko izvede samo v primeru vključene funkcije vodenja po položaju in sili. 7 Pobiranje sestavnih elementov hiše Sestavni elementi hiše prihajajo na tekočem traku po naključnem zaporedju. Kot smo že omenili uvodoma, uporabljamo za prepoznavo elementov, infrardeče tipalo, ki deluje na količino odbite svetlobe od podlage. Preden začnemo vršiti postopek prepoznave elementov moramo izvesti postopek kalibracije tipala. Slednje postavimo v horizontalini položaj, kjer po empiričnem postopku določimo primerno višino za najboljšo možno prepoznavo elementov. Kalibracijo smo izvedli zaradi razlike v višini med paleto in elementi (streha je bližje tipalu, kot stranice oziroma dno, katero je najbolj oddaljeno). Iz tega razloga poiščemo optimalno točko, ki je rezultat empiričnih poizkusov, kjer dobimo najboljši vzorec pravilno prepoznanih elementov. Razliko v višini med stranico in paleto prikazuje slika 4. Slika 4. Element »leva stranica« na paleti tekočega traku Fig. 4. Left side element on round ribbon palette Po uspešni prepoznavi elementa sledi pobiranje le tega. Za prijem elementov uporabljamo dvo-prstno prijemalo, katerega prožimo in vzdržujemo pritisk s pnevmatskim signalom. Prijemalo je izvedeno tako, da ima na notranji strani »prstov«, kjer element primemo, nalepljeni 5 milimetrov debeli elastični gobici. Takšna izvedba nam pri prijemu zelo koristi (preprečuje zdrs elementa iz prijemala), vendar ima slabo lastnost, da nase »prilepi« pobrani element, kar predstavlja težave pri odlaganju. Za stisk prijemala je potrebno modificirati čeljusti v smislu, da ne stiskajo elementa premočno. Pomagali smo si s plastičnimi podlogami, s čimer povečamo ali zmanjšamo razmak med čeljustima prijemala. V kolikor je stisk še vedno premočan, lahko jakost uravnavamo še s pomočjo regulacije dovedenega pnevmatskega signala, ki je v optimalni rešitvi znašal dve atmosferi. 39 Informacije MIDEM 38(2008)1, str. 36-41 S. Klampfer, B. Curk: Robotizacija proizvodnje - robotsko sestavljanje Sestavni deli, ki jih pobiramo iz strežnega mesta, so naloženi na lesene palete. Le te imajo različne tolerance, kar pomeni, da se lahko dve paleti medsebojno razlikujeta po višini, kakor tudi razmiku zatičev. Do razlik prihaja zaradi nenatančne izdelave, in uporabljenih lesenih neimpregniranih materialov, ki s časom spreminjajo strukturo, obliko in dimenzijo. To je razlog, da moramo dodeliti točno določeno paleto k točno določenemu elementu (gradniku hiše). Paleto in njen pripadni element moramo pri sestavljanju striktno uporabljati v navezi, saj se le tako definirani točki prijema in odlaganja ujemata. Da se izognemu omenjenemu problemu, je potrebno majhne stranice ustrezno oblikovat. Spodnji del, ki pri sestavljanju najprej preide v utor, preoblikujemo v polkrožno obliko (slika 6). To nam omogoča, da se bosta obe veliki stranici postavljeni po scenariju prikazanem na sliki 5, pri vstavljanju majhnih stranic razmaknili na ustrezno razdaljo. Problem je moč rešiti še z uporabo funkcije vodenja po položaju in sili, ki naredi manipulator podajen. To pomeni, da se slednji podaja po prednastavljeni sili v definiranih smereh. S tem dosežemo kopijo obnašanja zapestja človeške roke. 8 Odlaganje sestavnih elementov hiše Pri odlaganju elementov imata najpomembnejši vlogi toleranca in natančnost določitve točk odlaganja. Pomembna je orientiranost elementov na prijemalnem mestu v vseh treh dimenzijah (roll, pitch, yaw), saj mora imeti element enako orientiranost, kot je bila v primeru določanja točke prijema in točke odlaganja. Takšen način je v nasprotju z načeli robotizacije proizvodnje. Pri robotskem sestavljanju, se v praksi uporabljajo identične odjemalne palete, in identični gradniki. Ker tega nimamo na voljo moramo poiskati kompromis in ustrezno rešitev za preizkus delovanja. Osnovna gradnika (leva velika in desna velika stranica) sta bila zasnovana z zračnostjo lukenj enega milimetra, kar je omogočalo lažje sestavljanje. Gledano iz vidika sestavljanja je to dobrodošla lastnost, s katero se izognemo zatikanju, vendar se takšnim tolerancam v praksi poizkušamo izogniti. Slabo lastnost vpliva velikih toleranc lahko opišemo na praktičnem primeru: ob postavitvi obeh velikih stranic s toleranco lukenj enega milimetra na vogalnike dna hiše, se lahko zgodi, da se obe stranici prislonita k notranjosti (slika 4), kar posledično zmanjša razdaljo med obema stranicama. Slika 5. Tolerance zračnosti v reži za majhne stranice praktično ni Fig. 5. Decreaseing tolerance between both big side elements. Distance between both side elements is under allowed level Ob vstavljanju majhnih stranic (slika 5) nastopi težava, saj je razdalja manjša oziroma enaka dolžini majhne stranice. Obdelava stičnega dela v polkrožno obliko na spodnji strani majhne stranice (rdeč^ Slika 6. Obdelan spodnji del utora majhne stranice Fig. 6. Cultivated bottom side of the smallest side element To lahko opišemo na primeru vstavljanja zatiča v luknjo, ki ima majhno zračnost. Človek bo pri vstavljanju zatiča izvajal akcije kroženja zapestja, s čimer bo zatič spravil v luknjo. Z uporabo vodenja po položaju in sili dosežemo ravno takšen učinek, s katerim si pomagamo pri sestavljanju elementov z majhnimi zračnostmi. Beseda vodenje po položaju in sili pomeni, da naredimo manipulator podajen v želeni smeri. Podajnost lahko nastavimo v vseh smereh gibanja vključno s podajnostjo vrha orodja. V empiričnem poizkusu smo iskali ustrezne nastavitve posameznih parametrov, ki predstavljajo maksimalno uporabnost za izvajanje naše aplikacije. Zadovoljive rezultate je dajalo linearno vodenje po položaju in sili, kjer lahko podajnost manipulatorja nastavljamo v vseh smereh (X, Y, Z, R, B, T), oziroma samo v tisti smeri, ki deluje nasproti smeri odlaganja (smer X). Tovarniško pred-nastavljeni parametri za vodenju po položaju in sili niso določeni, zato moramo le te ugotoviti s pomočjo metode poizkušanja. Parametre izberemo po metodi najboljšega poizkusa. Vrednosti, ki jih nastavimo ne smejo biti premajhne, saj manipulator v takšnem primeru preveč niha. Vzrok nihanja gre pripisati delovanju sile težnosti na konec manipulatorja, kjer svoj delež doprinese še gradnik v prijemalu. Manipulator se skuša temu upirati in popravljati smer gibanja, kar se odraža v obliki nihanja. To nas prisili, da procentualne vrednosti povečamo, s tem pa izgubimo na dobri podajnosti, kar pomeni, da se manipulator že močneje upira postavljeni oviri. Vodenje po položaju in sili torej deluje na principu tokovnih omejevalnikov, ki omejujejo tok v sklepnih servo-motorjih v skladu z nastavljenimi procentualnimi vrednostmi. Zaradi relativno visokih procentualnih vrednosti parametrov vodenja po položaju in sili, s katerimi odpravimo 40 S. Klampfer, B. Curk: Robotizacija proizvodnje - robotsko sestavljanje Informacije MIDEM 38(2008)1, str. 36-41 nihanje manipulatorja, posledično pa ga napravimo manj podajnega, uporabili dodaten varnostni ukrep. Na mesto sestavljanja položimo elastično podlogo, ki predstavlja dodatno podajnost v navezi z manipulatorjem. Elastična podloga predstavlja tudi varovalni element, v kolikor bi pri sestavljanju šlo kaj narobe. S tem obvaruje delovno površino, sestavne gradnike, kot tudi sam manipulator. Elastična podloga je fiksno pritrjena na delovno površino, kar pomeni, da se njena lokacija glede na referenčni koordinatni sistem manipulatorja ne spreminja. Eno izmed težav smo že omenili v predhodnjih poglavjih, ki se nanaša na lepljenje elementov k elastični oblogi prijemala. Ker goba (elastična podajna podlaga) nima na vrhu utora, z minimalnimi tolerancami, kamor bi dno hiše pričvrstili. Tako je ob vsakem odlaganju dno hiše obležalo na drugačni lokaciji. Vzrok za to, je lepljenje elementa na gumijasto podlogo prijemala, kar posledično pri neenakomernem odpiranju čeljusti postavi element venomer na drugačno pozicijo na odlagalnem mestu, glede na izhodiščni (referenčni koordinatni sistem). Neenakomernost odpiranja čeljusti prispeva k potiskanju dna hiše levo ali desno od želenega središčnega položaja. Tega si nikakor ne smemo privoščiti. Problematika je rešljiva na več načinov: prvi je ta, da izdelamo togi podstavek, ki se popolnoma ujema z dnom hiše (gradnikom), hkrati pa ima minimalne tolerance zračnosti. Takšni podstavek bi pritrdili na elastično podlogo, ter od tam naprej gradili skupek sestavnih elementov v celoto. Druga možnost, ki smo jo izbrali mi, je ta, da na vrh elastične podloge pritrdimo obojestranski lepilni trak, kjer pri odlaganju dna hiše, le tega najprej potisnemo centimeter v gobo, da se oba sprimeta, ter šele nato odpremo čeljusti prijemala. Omenimo še nekaj dejavnikov, ki vplivajo na robotsko sestavljanje. Miza in tekoči trak nista fiksno pritrjena v tla, prav tako tudi nista medsebojno fiksno povezana. Pomanjkljivost kaže svoje rezultate prvič v primeru odčitavanja, drugič v primeru odjemanja elementov iz tekočega traku, tretjič pa pri odlaganju. Predpostavimo, da smo za določen primer fiksno določili tri točke odčitavanja za zdajšnjo pozicijo te- Manipulatorj Dvo-prstno prijemalo Gumijasta obloga Slika 7. Sestavljanje lesene hiše z manipulatorjem Motoman HP6 Fig. 7. Constructing wood house with robot Motoman HP6. kočega traku. Zgodi se lahko, da nam nekdo mizo tekočega traku premakne v drugo pozicijo. To pomeni, da se točke odčitavanja ne bodo skladale z želeno pozicijo elementov na paleti tekočega traku, kar povzroči nepravilno prepozna-vo, oziroma napake pri prepoznavi posameznega elementa. V najslabšem primeru je lahko prepoznava izvedena pravilno, vendar se točka prijema elementa na odjemalnem mestu ne sklada s pred-definirano. Ker bomo s prijemalom v takšnem primeru prijeli element drugače, bo ta vzrok imel posledice pri odlaganju elementa. Posledice so lahko v obliki poškodbe sestavnega elementa, poškodbe delovne površine oziroma nenazadnje v obliki poškodbe manipulatorja. 9 Zaključek V članku smo želeli predstaviti dejavnike, ki vplivajo na robotizacijo proizvodnje. Tekom izvajanja projekta smo naleteli na številne pomankljivosti na katere v uvodu nismo računali, zato smo iz tega razloga predlagali možne rešitve, ki temeljijo na preprostih principih, le tem, pa smo za primerjavo ob bok postavili principe, ki se uporabljajo v profesionalne namene. Naš pristop je temeljil na preprostih rešitvah, s katerimi smo dosegli želene rezultate. Manipulator je v navezi s tekočim trakom brez vključene optimizacije hišo sestavil v časovnem intervalu od dveh do treh minut (odvisno od zaporedja elementov na tekočem traku). Z vključitvijo pohitritve gibov manipulatorja in optimizacijo sortiranja elementov na tekoči trak, lahko čas sestavljanja opazno zmanjšamo, kar predstavlja izzive za nadaljnje delo na omenjenem projektu. Prav tako je tematika nadaljnjega dela usmerjena na področje vključitve umetnega vida za prepoznavo objektov. Literatura /1/ AVR - Avtomatizacija in robotika, Andrej Gorenc, Novo Mesto, 2003 /2/ NX-100 Users Manual, Motoman Robotec d.o.o., Yasakawa, 2005 /3/ Grundprogrammireung, Motoman, 2005 /4/ NX-100 Inform Manual, Motoman Robotec d.o.o., Yasakawa, 2005 / 5/ Modeling and High - Performance Control of Electric Machines, John Chiasson, New York, 2007 /6/ Prijemanje pri človeku in stroju, Tadej Bajd Saša Klampfer je diplomiral leta 2007, na Fakulteti za elektrotehniko, računalništvo in informatiko v Mariboru. Njegova raziskovalna dejavnost temelji na področju robotike in telekomunikacijskih sistemov. E-pošta: sasa.klampfer@uni-mb.si Boris Curk je diplomiral leta 1986, magistriral 1989 in doktoriral leta1995. Njegova interesna področja so robotika, modeliranje,simulacije in vodenje dinamičnih sistemov, avtomatizacija, računalniško podprte tehnologije ter nelinearni postopki vodenja. Prispelo (Arrived): 23.10.2007 Sprejeto (Accepted): 28.03.2008 41 UDK621.3:(53+54+621+66), ISSN0352-9045 Informacije MIDEM 38(2008)1, Ljubljana THE ARISING OF ELECTRIC DISCHARGE ARCS France Pavlovcic, Janez Nastran University of Ljubljana, Faculty of electrical engineering. Ljubljana, Slovenia Key words: discharging arc, corona, displacement current, excitation energy, gas ionization. Abstract: From the viewpoint of electric arcs, electric contacts are systematized due to their mechanic and electric operations in this paper. During the contact operation, drawn and discharging arcs or other discharging phenomena can occur depending on load currents. The difference between the drawn arcs and the discharging arcs is also shown. Further on, the phenomenon of the arising of the discharging arcs from corona is discussed by analyzing this phenomenon through the authors' mathematical model. This model calculates an electron average kinetic energy obtained by its movement along its mean free path in the non-homogeneous electric field between two spherical electrodes. The excitation energy of a gas molecule produced by the electron impact is compared with the first ionization energy and with the dissociation energy of the gas molecule, and the carry-on electron kinetic energy is determined. The displacement current is introduced into the model in the case of the alternating electric field, and its active and reactive component are established due to a complex value of the relative permittivity of the gas. The active component of the displacement current is in the phase with the electric field intensity, and causes the excitation energy in the gas molecules. Ranges of highly ionized, partly ionized and non-ionized molecules are founded in the whole volume. At the end some conclusions are made by comparison of a breakdown voltage obtained by the mathematical model with Paschen's voltage and the measuring result of the discharging arc is also introduced. Nastanek električnih razelektritvenih oblokov Kjučne besede: razelektritveni oblok, korona, poljski tok, vzbujevalna energija, ionizacija plinov. Izvleček: S stališča električnih oblokov so v tem članku električni kontakti sistematizirani glede na njihovo mehansko in elekrično delovanje. Med delovanjem kontakta lahko nastanejo potegnjeni in razelektritveni obloki ali druge oblike razelektritve, kar je v glavnem odvisno od bremenskega toka. Prikazana je tudi razlika med potegnjenimi in razelektritvenimi obloki. Nadalje je obravnavan nastanek razelektritvenih oblokov iz korone z analiziranjem tega pojava s pomočjo matematičnega modela avtorjev članka. Model izračunava povprečno kinetično energijo elektrona, ki jo doseže s preletom svoje srednje proste poti v nehomogenem električnem polju med dvema kroglastima elektrodama. Vzbujevalna energija plinske molekule, ki jo povzroča sila trka elektrona, je primerjana s prvo ionizacijsko energijo in z disociacijsko energijo plinske molekule, obenem je izračunana preostala energija elektrona, ki jo prenese na naslednji trk. Za primer izmeničnega električnega polja je v modelu določen poljski tok in ugotovljeni sta njegova delovna in jalova komponenta glede na kompleksno vrednost relativne dielektričnosti plina. Delovna komponenta je v fazi z električno poljsko jakostjo in povzroča vzbujevalno energijo v plinskih molekulah. V prostoru so ugotovljena območja z visoko vsebnostjo ioniziranih molekul, z delno vsebnostjo ioniziranih molekul in območje brez ionizacije. Na koncu so podani nekateri zaključki s pomočjo primerjave prebojne napetosti, dobljene z matematičnim modelom in Paschenovo napetostjo. Podan je tudi rezultat meritve razelektritvenega obloka. 1. Introduction Dealing with electric arcs as phenomena occurring between electric contacts, we have to classify the electric contacts according to their mechanic and electric operation. Due to the mechanic operation, the electric contacts are axial switching contacts and sliding contacts. The axial switching contacts have contact members that move in perpendicular direction to contact surface when changing their position. But, with the sliding contacts, their members move along the contact surface that means the parallel moving of both contact surfaces. Due to the electric operation, the electric contacts are making, breaking and holding or permanent. The making contacts establish the electric connection between their members and electric discharge mainly occurs due electric charged capacitance in a circuitry and especially due to a bouncing phenomenon of the making contact members when they close. This paper is not going to deal with that kind of discharges. The breaking electric contacts disconnect the electric circuit and when the contact members are separating from each other, a gap opens between them. In the gap between the contact members, drawn and discharging arcs or other discharging phenomena can occur. The holding or the permanent contacts have contact members that are touching and the connection is not time-depended. While the axial switching contacts, when holding, are steady, the sliding contacts are either steady or slipping. The drawn arcs can occur also with the sliding contacts, although they are permanent, such as slip rings, because the microscopic gap between the contact members varies due to the roughness, contamination and damages of the surfaces of both contact members /1/. This paper deals with the discharging arcs, which are stable or unstable since the drawn arcs are discussed in other papers /1/, /2/. The difference between the drawn arc and the discharging arc is in the time-depended electric current flow through the medium between the contact members when separated. The electric current flow is continuous with the drawn arc and decreases with its length. The medium is the ionized vapour of the cathode and the anode materials. But, with the discharging arc, the current between the separating contact members instantly falls towards zero value, a transient voltage appears due to time derivative of the current, which extends to a breakdown voltage value of the neighbouring gas medium - Fig. 1. 42 F. Pavlovcic, J. Nastran: The arising of electric discharge arcs Informacije MIDEM 38(2008)1, str. 42-52 dark discharge nlrtw Hiorharnc 1E-10 1E-09 1E-I 1E-07 1E-06 1E-05 0.0001 0.001 Discharge current[A] Fig. 1: The principle electric discharge UI characteristics; the discharge current is relative to the infimum arc current. The medium is an existing gas in the surrounding space. When the breakdown voltage of the gas is exceeded by the transient voltage, the electric breakdown of the insulating gas occurs, the electric current increases. What kind of discharge follows, depends on the current through the gas: the dark discharge, the glow discharge or the discharging arc. The later one is either the stable or the unstable arc. Nevertheless, which arc occurs, it arises from the ionized gas molecules. If there is no existing gas in the surrounding space of the contacts, the discharging arc begins by the ionization of the cathode material vapour. This kind of arcs is vacuum arcs. metrical. The eccentric positions of the equivalent point charges are defined by eccentric radius recc as it is defined in this paper and shown in Fig. 2, and further on, the eccentric position of the cathode equivalent point charge is the zero point of the coordinate system. A potential of any point T(r,q>) = T(r,ra) in the space is an algebraic sum of the partial potentials caused by the anode and the cathode charges since the potential is scalar value. It is defined by the following equation in the bi-radial coordinates /4/: U{r,ra)-- 4-71 e 1 1 ■-+ — T(np) (1) cathode anode Fig. 2: The geometrical drawing of the cathode, the anode and the distances between them in r-9 coordinate system. Further on, U(r, cp)= 4-ti e — + r Therefore the mathematical model of a spark gap of two spherical electrodes was developed to study the electric field and the ionizing process in the gap. The spherical electrodes were an approximation of the contact members (rivets) with the gap between them when breaking an electric circuit load. The electric load was an inductance-capacitance parallel circuit with a resistance in the inductive branch. The response of the circuit on the breaking manoeuvre was the damped oscillation at the series resonance of the circuit. This circuit represents an air coil in the most simplified way. 2. The mathematical model of a spark gap of two spherical electrodes The mathematical model is based on two spherical electrodes with the same radius ro and separated by the distance dsur between their surfaces. An anode is positively charged and a cathode has a negative charge by the same absolute amount of charge. The cathode is earthed so that there is a positive charge flow from the cathode to the earth. Due to the mutual influence of the anode and the cathode charges, the equivalent point charges of the anode and the cathode lie in the eccentric positions in the relevant spheres - Fig. 2. The mathematical model is solved in two dimensional space because the electric field is rotary sym- (2) since the cathode is earthed, its surface potential is defined as zero: r = recc A (p=0 => U = 0 (3) Between the anode and the cathode a certain voltage is applied, therefore the anode-cathode voltage is introduced instead of the anode and the cathode charges by using Eq. (2) under the following condition: r=recc+ds«r A

fi r 1+-S3L d (2 -fecc+dsur-rj / (11) The average velocity of an electron is according to Eq. (8) in literature /1/ as follows: 1 1 m„ w.;t c2 V1 (12) According to the same equation the average velocity of an air gas molecule (O2 or N2) is established by substitution of the electron kinetic energy and mass by the molecule kinetic energy and mass in Eq. (12), so that the molecule velocity is: 1 3a 1 "+7 (13) where the kinetic energy of the gas molecule is /6/: W ■■-■k-T 2 (14) The mean free path of the electron up to collision with the gas molecule is derived from /5/: RT 1 + ^-7i-d2-NA-p || e avg (15) where the quantity d is: d=re+rm (16) The average kinetic energy of the electron travelling along the mean free path is: Wek=e-E{rx)-X (17) because the electric field intensity and the mean free path are co-linear vectors. When the electron collided with the gas molecule, its kinetic energy is transferred to the molecule by impact as excitation energy of the molecule: W (18) Following the direction of the cathode-anode gap towards the centre of the gap, these phenomena can occur: the ionization and the recombination of the gas molecules, the dissociation of the gas molecules, and further on, simply no effects on the gas molecules occur by their collision with the electrons. From the gap centre towards the anode these phenomena occur in reverse order. Which phenomenon takes place, and which do not, depends on the kinetic energy of the electrons, which means it depends on the excitation energy of the molecule, as it is defined by Eq. (18). Due to the decreasing function of the electric field intensity depending on the radius in the range from the cathode to the gap centre, it is established, that there are four possible kinds of collisions with respect to the excitation energy of the molecules along the path between the cathode and the anode as follows: 1. Adjoining the ionization of the gas molecules, the inverse process also takes place. The probability of the ionization is Pi = 50 % and the probability of the recombination is (1 - Pi) = 50 %. The excitation energy of the molecule is: W >W. (19) exm ion y ' When this electron collides with the gas particle, there are two possible reactions: a. If the gas particle is the molecule, the ionization of it takes place. The collision is partly inelastic, and it consumes the ionization energy and the additional electron is emitted from the mole- 44 F. Pavlovcic, J. Nastran: The arising of electric discharge arcs Informacije MIDEM 38(2008)1, str. 42-52 cule. After the collision, the average kinetic energy per electron of these two electrons, that is of the one colliding and the one emitted, is: W -W. „ £rcm inn n (20) and it is carried on by each electron to the next collision. After each of them has passed the next mean free path it gets the additional kinetic energy defined by Eq. (17). b. If the gas particle is the ion in the neighbourhood of the cathode and the anode, the recombination occurs. The collision is totally inelastic, and it consumes the whole kinetic energy of the electron. The excitation energy of the recombined molecule is thermal energy and causes the molecule tem-perature rise above the ambient temperature for the increment: AT=^ft(l-Pi)(l-K) (21) 3-k So far the average temperature of the gas in the neighbourhood of the cathode and the anode rises and the temperature of the each electrode increases too, when the molecules bump at it. The parameter K=99.8% in Eq. (21) defines the percentage of the excitation energy, conveyed and conducted to the cathode and the anode, and further on, to the ambient as a natural or a forced cooling of both electrodes. Due to the temperature increment of Eq. (21), the average kinetic energy of the gas molecules increases according to Eq. (14), and so the average molecule velocity does according to Eq. (13). The recalculation process is convergent. 2. With the increasing radius, the electric field intensity decreases - Eq. (11), and the excitation energy of the molecule also decreases to such extend that: W. >W >WA. (22) ion exm dtss v ' In this case, the excitation energy of the gas molecule causes the dissociation of the two-atom molecule into two gas at-oms. This collision is partly inelastic and it consumes the dissociation energy. The remaining kinetic energy of the colliding electron is carried on by the same electron: and further on, it increases because the electron passes the next mean free path before the next collision -Eq. (17). 3. If the excitation energy of the molecule is lower than the dissociation energy of the gas molecule: (24) the colliding electron has no effect on the gas molecule. The kinetic energy of the electron is carried on to the next collision because the collision is elastic: W*_m=W* (25) The ionization-recombination collisions take place near the cathode, the dissociation collisions are next to them in the direction of increasing radius towards the gap centre and further on, there are the no-effect collisions, and follows in the reverse order towards the anode. Although there is a sequence of these phenomena, we could not consider there are any pure ranges such as an ionization-recombination range, a dissociation range and a no-effect range. But very near to the each electrode there is a highly ionized range because the electrons in this range have very high kinetic energy and nearly every collision causes such excitation energy in the molecule that its ionization occurs. Next to this range is a partly ionized range up to the point where no ionization occurs. At this point a non-ionized range begins and lies around the gap centre - Fig. 3. highly ionized range cathode anode partly ionized range Fig. 3: The ranges of the arising discharge due to switch off manoeuvre in the electric circuit in Fig. 4 at the input-output quantities in Tab. 1 for oxygen molecules as simulated by the model. In the highly ionized range, the ionization-recombination collisions take place mainly. In the partly ionized range, both the ionization-recombination and the dissociation collisions occur. Further on, in the non-ionized range, there are no ionization collisions, but the dissociation collisions and the no-effect collisions take action. This is the most general situation in the cathode-anode gap and in this case there is no electric breakdown through the cathode-anode gap. If the non-ionized range is not present in this gap along the shortest field line due to the high values of the electric field intensity (caused by the high anode-cathode voltage) and at least the partly ionized ranges come together from the cathode and the anode side, the electric breakdown occurs and electric discharge takes action through a stable or unstable arc, or as a glow discharge with a self-maintaining current. There were some simplifications made during this modelling process: 1. When deriving Eqs (12) and (13), the following relations were presumed: 0 <-!==!-«1 c 0< VfïL«! c (26) 45 Informacije MIDEM 38(2008)1, str. 42-52 F. Pavlovcic, J. Nastran: The arising of electric discharge arcs 2. The rest and the actual masses of the electron and the gas molecule correspond to: me « ™m n.(yt)«mm(ym) (27) 3. The ionizations and the recombinations take place in the same range that is in the highly ionized and in the partly ionized range, which lies by the both electrodes. Knowing the electric field intensity at the cathode surface at 9 = 0 and its temperature, the following conductive current densities are calculated: the current density of the field emission and the current density of the thermionic emission. Both of them are the active current densities. The current density of the field emission is calculated by the Fowler - Nordheim equation /1/: Je =- 8 -ic ■ A • E V' 3 h ' e ■^S-m'-e3 , -1/2 (28) Possible thin insulation of the cathode and the roughness of the cathode surface effect the electric field intensity, the work function and the effective electron mass /1/. Therefore the following substitutions must be considered in Eq. (28) to descride exploatation condition of the cathode: E'= <= p =5 v V* - 4 r rhv K f* * me m= — V =5 11 = 5 (29) but the values of these coefficients were presumed in the model. The current density of the thermionic emission is defined according to /5/ as: J t ■■ 4-71 -m.-e-k ■T fJk+flMl i [ 0) \4-JI-£„ J (30) The direct electric field was dealt with up to this point. If an alternating electric field is applied, a displacement current occurs, which has the following properties essential to establish the mathematical model of electric discharge: - The displacement current could be measured inside the gas gap between the cathode and the anode. - There are no current carriers (electrons and ions) in the gap due to this phenomenon. - There is no rise in electric field intensity due to this phenomenon, so the field emission of the electrons is unchanged. - This current causes no heat dissipation on the cathode surface, therefore there is no rise in temperature, and further on, there is no rise in the thermionic emission of electrons due to this phenomenon. - The active component of this current causes the excitation of the two-atom gas molecules and further on the ionization and the dissociation of these molecules. - The reactive component of this current causes that the electric energy is stored in the capacitance. - Consequently to the ionization of the gas molecules, the recombination of the gas ions occurs, the thermal energy of the recombined gas molecules increases, but this rise is the effect of the recombination process, and not the effect of the displacement current. The displacement current is defined in general by its density /4/ as: dE{rx,t) Jd -E. £„ dt (31) The displacement current is complex current density (represented by a phasor) through the capacitance between the cathode and the anode. The relative permittivity er is complex scalar quantity defined by its absolute value er and by losses angle d as follows: er=ere-ts (32) Further on, the absolute value of the active displacement current is: J da, = £ "En dt (33), and it is the one that causes the excitation of the molecules and the phasor of this current density is co-linear with the phasor of the electric field intensity - Fig. 5, so as the phasors of the field and the thermionic emission current densities. The reactive displacement current is capacitive current and its absolute value is as follows: JDreac ^r'^o' dt ■cos 5 (34) Therefore the absolute value of the apparent displacement current density is: JDapp ^r '^0 dt (35) The damping sinusoidal anode-cathode voltage /7/, which is the response of the circuit in Fig. 4 on the switch off manoeuvre, is applied, and hereby the electric field intensity has the same shape and frequency as the anode-cathode voltage: uaM = ^-Uc- e~al • e1^"-^) + Ug (36) A phase angle Zdue to Uc(0) and Il(0) and a phase angle | due to a and œ are equal because the inductance and the capacitance in Fig. 4 have no losses, otherwise the angle Z is smaller then the angle The electric field intensity is according to Eq. (11) equal: E(rx,t)= Re(zîaK(i)>^- 1 1+- sur / N (2-recc+dsur-rJ y (37) 46 F. Pavlovcic, J. Nastran: The arising of electric discharge arcs Informacije MIDEM 38(2008)1, str. 42-52 switching off 1 Fig. 4: The electric circuit switched off by the breaking contact. The time derivative of the anode-cathode voltage is: = Uc. ja2 +c0q • e** ■ ev5 (38) Using Eqs (32), (37) and (38) the phasor of the displacement current density is obtained: JD(f) = JD-eat ■e^"'-^ (39) and further on, its apparent value is: I"if 1 re l + I&a. (2-recc+dsur~rJ (40) Hereafter the shorter format of the following functions is used: E=E(rx,t) dE _ dE(rx,t) dt dt (41) Fig. 5: The principle phasor diagram at t = 0 and 9 = 0; not in the scale, because the angles are very small: Z = \ = 0.0055 and S = 0.00016 radians. Because the active displacement current causes the excitation of the molecule in the volume between the cathode and the anode, the active displacement energy is the integral of the scalar product of the phasors of the active displacement current and the electric field intensity through- out the volume. Hence, the cosine function of the angle between two phasors is applied, and it is equal to sine function of the complementary angle. So the excitation energy of one molecule in the volume, containing Nm gas molecules, due to the displacement current density is: WDaci=-L]\\\jD.E.dV.dt- 1 N J JjDaPp-E-^-dV-dt = m 0 V(Nm) (42) Supposing the electric field is homogeneous in the volume V, which contains Nm gas molecules. The displacement energy in this volume is homogeneous also, which means that its density is equal in the gas molecules themselves and in the hollow volume around them. The displacement energy in the gas molecules causes the excitation of the molecules, so this part of the displacement energy is active. The displacement energy in the hollow volume is reactive. To obtain the homogeneous electric field, the smallest volume V = V(1) has to be taken, and this is such one that contains only one gas molecule under the constant thermodynamic conditions of the gas. Hence, this volume must be the greatest one to be equally distributed among all Nm gas molecules. Further on, the active displacement energy of one molecule is defined under the following condition Vm << V(1) by: Wn. = lim y{Nm) -» v(] OFtff.) dE e, e„ •— E smS dV dt" (43) Je, e0 — E dV dt* ■EVmdt Taking into account Eqs (17), (20), (23) and (25), the electron kinetic energy just before the collision with the gas molecule is: Wek=e-E-%+Wek (44) This equation forms the calculation loop with Eq. (12), but the mathematical process converges, and the result uniformly exists. The mathematical model of the electric discharge in gases has to take into account both, the kinetic energy of the electrons and the energy of the displacement current. The electron kinetic energy is partly transferred to the gas molecule by the electron impact, and causes the ionization or the dissociation, discussed heretofore. In this case, the ionization is considered as the impact ionization although it is more probable that the ionization is done through the excitation of the gas molecule on its higher energy level /5/. The dissociation of the two-atom molecule just cannot be carried out directly by the electron impact due to 47 Informacije MIDEM 38(2008)1, str. 42-52 F. Pavlovcic, J. Nastran: The arising of electric discharge arcs the large difference of the electron mass and the dissociated atom mass - Eq. (27). The dissociation is completed by the excitation energy of the two-atoms molecule due to the impact energy when raised in such extend that the dissociation energy level is achieved. This is the dissociation due to the conductive current. The displacement current energy also affects the gas molecules, and also causes their ionization and their dissociation. Because it has no carriers, the ionization and the dissociation are caused by the excitation of the gas molecule with no impact, but only due to the displacement current. All these processes: the impact ionization, the dissociation due to the conductive current, the ionization and the dissociation due to the displacement current have the same mechanism of being completed - the excitation of the molecule on its higher energy level, and afterwards the accomplishment of the process. Therefore the kinetic energy Eq. (44) and the displacement energy Eq. (43) are summarized in the excitation energy of the gas molecule, which is the active energy: W„(r*,t,T,W»,,W*. )= e ■ E{rx,t)- X(T) + + Wek_oMon>Wdlss)+ dE(rx,t) "J- dt E(rx,t)Vm-dt (45) This equation is in the calculation loop with Eq. (18) but the calculation converges. The excitation energy is calculated by Eq. (45), and the minimal value of the excitation energy is graphically represented by the diagram in Fig. 6. The minimal value of the excitation energy is the one without the carry-on kinetic energy of the colliding electron. The gas used in this calculation is oxygen. The highly ionized range begins closely to the electrode and ends where the minimal value of the excitation energy decrease under the value of the ionization energy. The number of the ionized molecules is constant due to the radius and its level is hundred percent of molecules. This range comes out as corona. Closely to it, the partly ionized range begins where the minimal value of the excitation energy is lower than the ionization energy and higher than the dissociation energy, but the carried-on kinetic energy raises the excitation energy on a higher energy level than the ionization energy. It ends where the minimal value of the excitation energy decreases under the dissociation energy because the carried-on kinetic energy is not sufficient to raise the excitation energy on the ionization energy level. The number of the ionized molecules decreases to zero. The number of dissociated two-atom molecules increases up to hundred percent level. In the non-ionized range, where the minimal value of the excitation energy is under the value of the dissociation energy and the carried-on kinetic energy raises the excitation energy up to the dissociation energy level. The number of the dissociated molecules decreases, but the number of the unaffected molecules increases with the radius near centre of the cathode-anode gap. If the anode-cathode voltage increases, the non-ionized range in Fig. 3 narrows, and the partly ionized range from the cathode side touches the partly ionized range from the anode side, and the ionized path between the electrodes arises, the electric breakdown occurs and the electric discharge arc takes place. Consequently the definition range of the percentage of unaffected molecules, which is on the abscise of the diagram in Fig. 6, limits to zero, and the percentage of the ionized molecules is above zero throughout the whole abscise range. This change in the mathe-matic functions of the percentage of the ionized and of the unaffected molecules means the establishment of the ionized path between the electrodes. 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 0.0009 0.001 Dlstxnc* from surfxc« of sphaflctl cathode - ( r-r [m] Fig. 6: The minimal excitation energy of the oxygen molecule versus the distance from surface of the cathode to any point at 9 = 0 towards the anode, and the percentage of the oxygen molecules density at the input-output quantities in Tab. 1. The simulation was carried out with the spherical cathode and anode with the radii of 0.5 mm, and with the surface-to-surface distance of 1 mm between them. The excitation energy in comparison with the first ionization, and with the dissociation energy of the oxygen molecule, and further on, the density of the ionized, the dissociated and the unaffected oxygen molecules are shown in Fig. 6. The input and output quantities of the spark gap discharge model are numerically stated in Tab. 1. When discussing the electrical breaking contact, its contact members are the electrodes. The distance between them increases from zero, when the breaking contact still holds the closed position, up to the maximum value. In the model, the distance of 1 mm is used because the Paschen law minimum is being avoided. The Paschen law is described by the family of functions of the breakdown voltage of the spark gap depending on the product of the gap length and the gas pressure, but the functions differ by the chemical composition of the gas medium in the gap. These functions have minima: 450 V at 9.2 |jm with oxygen, 251 V at 8.8 jm with nitrogen, and 327 at 7.5 jm with air at the same pressure 101.325 kPa in all three cases /8/. At the distances lower than the ones of the minima, the break- 48 F. Pavlovcic, J. Nastran: The arising of electric discharge arcs Informacije MIDEM 38(2008)1, str. 42-52 Tab. 1: The input-output table of the spark gap discharge model of oxygen and nitrogen molecules at the same environmental conditions; the variables of the functions are (r, U medium o2 n2 cathode Ag Ag Wjon 1.955 2.464 aJ / particle Wdiss 0.816 1.266 aJ / particle ro 0.500 <— [mm] dsur 1.000 <— [mm] Tamb 293.15 <- [K] P 101.325 <— [kPa] U9 220 <— M R 3.75 [kQ] L 11.0 [H] C 94.0 <- [pF] to 17.0 [MS] UaK{to) 10.126 <— [kV] ¡Dact (recc, 0, fo) 1.49 1.21 [mA/m2] jDraac (iecc, 0, fo) 9.55 <— [A/nf] (¡E + jr)@(recc, 0, fo) 6.78 <— [A/mf] dE/dt(recc, 0, fo) 1.08 <- [TV/m/s] E (recc, 0, to) 20.3