IEEE 1149.1 STANDARD: A WIDELY SUPPORTED DESIGN FOR TESTABILITY TECHNIQUE U. Kač Institut "Jožef Stefan", Ljubljana, Slovenia Key words; electronics, electronic circuits, PCB, Printed Circuit Boards, IC, Integrated Circuits, electronic systems, testing, debuggers debugging design for testability, in-circuittest, boundary-scan test, JTAG, Joint Test Action Group, IEEE 1149.4 standards, TAP, Test Access Port, mixed-signal tesi buses, EDA, Electronic Design Automation, ATPG, Automated Test Pattern Generation, IEEE 1532 standards, in-system configurations IEEE 1500 standards, embedded core tests Abstract: This paper is a short introduction to the implementation and application of IEEE 1149.1 boundary-scan test techniques, which are l .iz: 7- -t i -f - - yiTAP controller j: si FSM 1: PCB TDi IMS TCK TDO Figure 2: Structure of a boundary-scan device set that any compliant device must support HI- Furthermore, the standard allows for optional and proprietary test instructions, and for additional test data registers to be implemented on-chip. A later supplement to the standard defines the Boundary-Scan Description Language (BSDL) syntax. BSDL is used for describing the boundary-scan device pin-out and the specific implementation of its test infrastructure (such as boundary register, optional registers, instruction set and opcodes). BSDL files are readily available from manufacturers of IEEE 1149.1 compliant devices. 2.1 Use of boundary-scan at chip level The on-chip boundary-scan test infrastructure does not contribute to the basic functionality of the device. Nevertheless it can provide substantial benefit at chip level with its provision for a standard test access method (TAP), which can be used to access chip-internal test facilities, such as internal scan path, built-in self-test (BIST) or built-in emulation and debug. Internal scan paths are implemented by substituting normal storage elements (latches, flip-flops) within the core logic with scannable ones, which can be serially interconnected to form a shift register structure (Figure 3). The primary reason to adopt this technique is the inability of sequential automatic test pattern generation (ATPG) algorithms to provide adequate fault coverage for core logic test. By dividing core logic into smaller sequential blocks (partial-scan), or plain combinatorial blocks (full-scan) that are accessible from the internal scan path, better fault coverage can be achieved with existing ATPG algorithms /8/. IEEE 1149.1 architecture allows the definition and use of proprietary instructions therefore the internal scan path register can be easily integrated with other 1149.1 test data registers. Consequently, static device test requirements can be reduced to the TAP interface, since both boundary and internal scan registers are accessible through TDI/ TDO. Furthermore, internal scan path can be accessed through the same interface for chip debug and failure diagnosis. Figure 3: Device with internal scan path The main benefit of BIST techniques is that test vectors are generated and test responses are monitored on-chip thus eliminating the need for external generation and application of large sets of test vectors via the chip primary inputs/outputs. This is usually achieved by means of pseudo-random pattern generators and signature analyzers implemented as linear-feedback shift registers (LFSRs). IEEE 1149.1 provides for easy integration w/ith on-chip BIST through the implementation of the optional runbist test instruction. When implemented, RUNBiST can provide for quick functional testing of a PCB mounted device. 2.2 Use of boundary-scan at board level Board-level test has been the primary concern of the IEEE 1149.1 standard developers. Boundary-scan cells replace ICT physical nails by providing electrical access to circuit-internal nodes through device primary inputs/outputs and are therefore often referred to as "virtual nails" or "silicon nails". At the board level, boundary-scan devices are usually daisy-chained (TDO to TDI, Figure 4) to form a single boundary-scan path. Bridging fatil Output BS cell From teste- ■nff i-m- I ■ I ■ Nonscan: i • ■ ■ I I Figure 4: Board-levei boundary-scan path implementation For boards, which are entirely populated by IEEE 1149.1 compliant devices, opens/shorts tests with 100% fault cov- erage can be generated fully automatically by ATPG software and inexpensive four-wire boundary-scan testers can be used to perform the board test. Furthermore, faults can be automatically isolated to the interconnection (for shorts) or to the node (for opens). The task of generating board-level fault tests is greatly simplified. Since each device input pin can be sampled and each output pin can be driven from the appropriate BSC, no knowledge of the device core logic is required for fault testing the board. For a group of PCB interconnections between two boundary-scan devices, a single test vector is required to test all interconnections for stuck-at-one faults. To provide stimulus, an all-zeros test vector is shifted into output BSCs via TDI to drive the interconnections low. Interconnection values are then sampled into input BSCs and shifted out via TDO for comparison with the expected value. Similarly, stuck-at-zero faults test requires a single test vector of all-ones. Bridging faults can be isolated using a binary search algorithm: a group of 8 interconnections requires only 3 test vectors for a complete bridging fault test, as shown in Table 1. ' Interconnection I 1 i 2 3 i 4 5 6 7 i 8 1 Vector 1 i 0 1 ! 0 ; 1 0 1 0 i I Vector 2 0 ! 0 1 1 0 0 lili Vector 3 i 0 0 0 0 1 1 lili Table 1: Test vectors for 100% bridging fault coverage (number of interconnections = 8) Altogether, a board with N interconnections between distinct BSCs, would require a total of (log N / log 2) + 2 test vectors for full bridging and stuck-at fault test (i.e. 5 test vectors for 8 nets). Consider now fault testing a non-IEEE 1149.1 board with ICT probes. In contrast with BSCs, bed-of-nails fixtures usually provide a single access point to any interconnection, therefore stimulus is applied to interconnections at device inputs and response is sampled on interconnections at device outputs. A plain combinatorial device would require test vectors for a full test (i.e. 256 vectors for 8 interconnections). Although the number might be significantly reduced by studying the device functionality, this requires adequate functional models and test development tools. In case of a sequential device the problem would become even more complex, since several setup vectors might be required to condition a device to test an input and several vectors might be required to propagate the fault to an output for observation. On the other hand, even if the board comprises only a few IEEE 1149.1 devices, the test development can be substantially simplified and fault coverage improved. When clusters of non-scan devices and other components are surrounded by boundary-scan devices, BSCs in surrounding devices can be used to stimulate the cluster and observe its responses. In this case a suitable test vector set targeting interconnection faults within the cluster must be prepared. When such approach is not sufficient in terms of fault coverage, the boundary-scan infrastructure can be combined with ICT physical nails to access cluster-internal interconnections. 2.3 Use of boundary-scan at system level Chip and board-level IEEE 1149.1 based tests can be reused at system level e.g. for system BIST, field service, remote diagnostics or hardware debug. The main benefit is that the physical test access can be limited to the simple TAP interface and use of complex test hardware can be avoided. Moreover, by implementing backplane bus interfaces on single PCB modules and on the backplane PCB with scannable devices, the backplane connectivity and integrity test can be performed and the system can be partitioned along modules boundaries for easier diagnostics. Board level , boundaryscan chai Backplane iterconnec _ TCK_B( . •TRST_E IEEE 1149.1 syster test bus Figure 5: Multidrop system IEEE 1149.1 architecture While a single boundary-scan chain is usually used to connect IEEE 1149.1 devices on a PCB (Figure 4), the same approach is not adequate for integrating boards into the backplane architecture (Figure 5). If the backplane is designed such that board-level scan chains are daisy-chained into a single system wide chain, then removing any board from the system will break the boundary-scan chain. Furthermore, boards must be located in specific slots in order to preserve a known test infrastructure and a fault in the chain of one board would leave the entire system untesta-ble. To avoid such problems the standard proposes a multidrop star configuration in which the TDl and TDO pins are bussed. However to prevent simultaneous scanning of multiple boards onto the same TDI/TDO bus, multiple TMS signals are required (one for each slot) and the number of backplane channels increases proportionally. An alternative solution, which does not require multiple TMS lines, is a multidrop scheme using addressable IEEE 1149.1 devices. 3. Boundary-scan development tools and testers In orderte benefit from the IEEE 1149.1 standard, the designer should specify the use of boundary-scan infrastructure in custom ASICs and place scannable catalog devices on board wherever possible. Nowadays a number of IC vendors provide a variety of IEEE 1149.1 compliant devices, including standard components (bus interfaces, microprocessors, DSPs, memory ICs, ...), user field-program-mable devices and ASICs (gate-arrays, standard cells, ...). Various support devices (test bus controllers, scan path bridges/linkers/selectors, multidrop addressable test ports) are readily available to facilitate the implementation of board or system level boundary-scan infrastructure. Another very important issue for a designer is the availability of EDA tools supporting boundary-scan. Most major EDA vendors offer boundary-scan insertion tools as well as tools for boundary-scan ATPG. Finally, some means of boundary-scan test application is also required, which can come either in the form of large production in-circuit or functional testers with integrated boundary-scan capabilities or as inexpensive, PC-based standalone boundary-scan testers. 3.1 Design of IEEE 1149.1 compliant devices Boundary-scan insertion tools provide for a more or less automated design of IEEE 1149.1 compliant ASICs, which is often combined with insertion of other on-chip test structures, such as internal scan or BIST These tools usually operate on RTL or gate-level descriptions of the ASIC design and on existing libraries of boundary-scan building blocks. Better tools provide for a more flexible configuration of the building blocks (e.g. implementation of proprietary test instructions, integration with internal scan / BIST) as well as for the generation of test patterns for use with on-chip test structures. The tool output usually consists of a device netlist and the appropriate BSDL device description (see Figure 6). 3.2 Boundary-scan test development Boundary-scan ATPG tools automatically generate prototype or manufacturing tests to be applied to the circuit under test (CUT) using the board level TAP ATPG tools usually consist of various software modules, which can be combined to suite the chosen test strategy. Modules include access analysis, boundary in-circuit test, virtual interconnects test, virtual component/cluster test, boundary functional test as well as test generators for BSDL validation and TAP/scan-path integrity testing. Access analysis tools are typically used before layout of mixed scan/non-scan circuits to identify interconnections, which do not require physical test access. Boundary in-circuit test generators combine physical probing and boundary-scan devices to reduce test complexity. Virtual interconnect test modules generate patterns to test interconnections using only the virtual access provided by the boundary-scan path while virtual component/cluster test modules use boundary-scan access to detect open and stuck-at faults on the leads of non-scan devices/clusters, eliminating the need for physical access. Some tools also support multiple boundary-scan paths on a single board. ATPG tools usually operate Scaninsertion tools Siiiiiiiiililp^ ÄplliiliiiPpa O^Jvi« nefitsb'w ßSDldiwke llllll^lllllllil büundar>'$csn ^ tost vectors fS^^gm f^lilliifci Circuit nctiist ^lillilirtiiilill dsscr'pliöfi Test yL'ncrötion (ATPG) Boundaryseari: ATPG tools Figure 6: Boundary-scan development process on given circuit netlist and BSDL description (see Figure 6), producing test patterns In standard automatic test equipment formats, sucli as the Serial Vector Format (SVF). 3.3 Boundary-scan testers We can roughly divide commercially available boundary-scan testers into two groups. The first one includes large production In-circult and functional testers with integrated boundary-scan support, which are designed to achieve the highest possible fault coverage within only one production step. This is reflected by high complexity and elevate costs of such testers. The second group Includes so-called standalone boundary-scan testers. These usually consist of a host PC and a relatively Inexpensive adapter, which controls the IEEE 1149.1 test bus and possibly features some additional parallel l/Os to control/observe CUT edge connectors. A variety of internal and external PC adapters are available on the market for many standard buses, such as ISA, PCI,\/XI, PXI, PC-CARD, PIO, RS-232, USBorGPIB. The minimum requirement for any boundary-scan tester Is the ability to exercise the board-level TAPs under the control of a simple test description (e.g. a SVF file), however an interactive boundary-scan test and debug environment is preferred to simplify the use of the test system. Most boundary-scan testers provide software tools that allow Interactive view and control of only those portions of the board (pin, register, bus, user-defined signal group) that Figure 7: Stand-alone boundary-scan tester are of Interest. The benefit of such tools Is that complexity of TAP protocol and boundary-scan chain are hidden from the user and test stimuli/responses are presented as waveform and state diagram displays. The tools usually support various test vector generation methods including interactive creation and EDA or boundary-scan ATPG generated test sets. They also allow the user to describe the boundary-scan test infrastructure using standard formats such as BSDL and EDIF (Electronic Design Interchange Format). 4. IEEE 1149.1 related standards During the existence of IEEE 1149.1 several related standards have emerged, which extended the use of the boundary-scan techniques and its infrastructure to new areas such as testing of mixed-signal circuits or in-system configuration (ISC) of programmable devices, while a standard concerning testing of System-on-ChIp (SoC) devices is currently In project phase. The original standard Itself has seen two additional supplements: IEEE 1149.1 a-1993 and IEEE 1149.1 b-1994 (BSDL). The IEEE 1149.1-1993 supplement brought some clarifications and new optional boundary-scan test commands to the original standard. Furthermore it addressed the Issue of integration of IEEE 1149.1 with other test access methods such as the Level Sensitive Scan Design (LSSD), which Is frequently used to access Internal scan paths. The supplement described a simple mechanism for converting a component from conformance to IEEE 1149.1 to conformance to a different standard. The three publications were finally merged Into the latest standard publication - IEEE 1149.1-2001. 4.1 IEEE standard for a mixed-signal test bus (1149.4-1999) The IEEE 1149.4 standard extended the boundary-scan principle into the domain of mixed analog-digital circuits with the introduction of new elements to the existing IEEE 1149.1 test infrastructure. The standard defines analog boundary modules (ABMs), which are interposed between primary analog functional pins and appropriate analog core terminals. The TAP is expanded with analog pins ATI (Analog Test 1) and AT2, which are internally connected to each ABM via the Test Bus Interface Circuit (TBIC) and a two-wire on-chip analog bus AB1/AB2 (Figure 8). At the board level, all IEEE 1149.4 devices are connected to a two-wire analog bus through ATI and AT2 pins /9/. This additional infrastructure allows analog stimulus from external generators to be routed from ATI pin to an output ABM and on to connected analog components. Analog responses arriving at an input ABM can be routed to AT2 pin and on to an external measurement unit. In this way, parametric measurements of on-board analog components can be performed. Although IEEE 1149.4 compliant catalog devices are currently unavailable, first steps are being done by IC manufactures towards the implementation of such devices /10/ and feasibility studies on experimental ICs have already shown a number of possible benefits in designing mixed-signal ICs with IEEE 1149.4 infrastructure/11, 12,13/. 4.2 IEEE standard for in-system configuration of programmable devices (1532-2000) In-system configuration of programmable devices has become a major new application of the IEEE 1149.1 standard. Programmable logic imposes several problems (lack of device models, test preparation delays) to ICT board testing methods, therefore IEEE 1149.1 infrastructure is included in the majority of programmable devices. The manufacturers soon realized that they could also use the TAP interface and the boundary-scan serial protocol for ISC of the device. The result of a standardization effort between various manufacturers is the IEEE 1532 standard, which defines additional data registers to assist configuration programming, along with new mandatory and optional instructions compatible with the IEEE 1149.1 physical and logical protocols /14, 15/. 4.3 IEEE Standard Testability Method for Embedded Core-based Integrated circuits (P1500) Test development currently represents a major problem in the design of complex SoC devices, which include embedded cores originating from different core providers. The PI500 working group was established in 1995 with the goal to develop a standard DfT method for such devices. The standard will define a test wrapper architecture and a language for the description of test related information for Boundary scan register Vth Vh Vl Vc3 Analog boundary module Vth Vh Vl Vq To core Switch control ToTDO Figure 8: IEEE 1149.4 compliant mixed-signal device structure tine cores (e.g. processor cores, memory blocl