<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-FZA93AS8</identifier><date>2022</date><creator>Beguš, Jari</creator><creator>Zadnik, Damjan</creator><creator>Žemva, Andrej</creator><relation>documents/doc/F/URN_NBN_SI_doc-FZA93AS8_001.pdf</relation><relation>documents/doc/F/URN_NBN_SI_doc-FZA93AS8_001.txt</relation><format format_type="issue">5</format><format format_type="volume">89</format><format format_type="type">article</format><format format_type="extent">str. 239-245</format><identifier identifier_type="ISSN">0013-5852</identifier><identifier identifier_type="COBISSID_HOST">138769411</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-FZA93AS8</identifier><language>eng</language><publisher publisher_location="Ljubljana">Elektrotehniška zveza Slovenije</publisher><source>Elektrotehniški vestnik</source><rights>InC</rights><subject language_type_id="eng">DDR3 SDRAM memory</subject><subject language_type_id="eng">FPGA device</subject><subject language_type_id="eng">memory controller</subject><subject language_type_id="eng">memory interface</subject><subject language_type_id="slv">pomnilnik DDR3</subject><subject language_type_id="slv">pomnilniški krmilniki</subject><subject language_type_id="slv">pomnilniški vmesniki</subject><subject language_type_id="slv">vezje FPGA</subject><title>A memory interface for DDR3 SDRAM memory in Xilinx 7 Series FPGAs</title></Record>