HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder

URN:NBN:SI:DOC-QUWMHTNB2003Verderber, MatjažŽemva, Andrejdocuments/doc/Q/URN_NBN_SI_doc-QUWMHTNB_001.pdfdocuments/doc/Q/URN_NBN_SI_doc-QUWMHTNB_001.txt233articlestr. 86-910352-90454028500URN:NBN:SI:doc-QUWMHTNBengStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMInCdekoderFPGA vezjaMPEG standardvideo tehnikaHW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder