A NEW APPROACH IN TESTING ANALOG-TO-DIGITAL CONVERTERS Martin Kollar Technical University of Košice, Slovakia Key words: testing ADC, integral non-linearity, differential non-linearity Abstract; This paper describes a new approacfi in testing static parameters of analog-to-digital converters (ADCs). The input of an ADC to be tested is connected to a generator of saw-tooth impulses. In comparison to ordinary approaches, the measured decision levels are not related to zero potential but to the decision levels of an additional ADC, which is of same type as tested ADC. Approximating principle-based test system, with a digital-to-analog converter (DAC) in the feedback, measures these differences, which are in the extreme case in the range of a few least significant bits (LSB) of tested (additional) ADC. It has been proposed a special algorithm, to which output codes of tested and additional ADC enter, to control this DAC, which output is added through a resistive divider to the input of additional ADC. By using this approach, there are no special requirements on the precision of input sawtooth impulse generator and precision of the obtained integral non-linearity (INL), differential non-linearity (DNL) characteristics mainly depends on DAC used. It was also shown that using 8 bit DAC the precision is in the range of a few hundredths of LSB. By simulations with MATLAB, the theoretical considerations are verified. Nov pristop k preizkušanju analogno-digitalnih pretvornikov Kjučne besede: testiranje analogno-digitalnih pretvornikov, integralna nelinearnost, diferencialna nelinearnost Izvleček: V prispevku opisujemo nov pristop k preizkušanju statičnih parametrov analogno-digitalnih pretvornikov ( nadalje ADC ) Vhod pretvornika, ki ga želimo preizkusiti, priklopimo na generator impulzov. V nasprotju s standardnim pristopom, kjer meriene nivoje primerjamo z ničelnim potencialom, jih v našem primeru primenamo z drugim pretvornikom istega tipa kot ta, ki ga preizkušamo. Če upeljemo testni sistem tako, da dodamo digitalno-analogni pretvorniki DAC ) v povratni vezavi, je ta sposoben meriti razlike, ki so v skrajnem primeru v območju zadnjega pomembnega bita( LSB - Least Significant Bit) testiranega (dodatnega) pretvornika. Predlagamo poseben algoritem, kjer izhodne kode testiranega in dodatnega pretvornika peljemo v DAC, katerega izhod preko uporovnega delilnika vrnemo nazaj v dodatni ADC. Pri takem pristopu točnost generatorja vhodnih impulzov ni pomembna in sta integralna in diferencialna nelinearnost odvisni predvsem od uporabljenega DAC pretvornika. Pokažemo, da je, če uporabimo 8 bitni DAC, točnost v območju nekaj stotink LSB. Teoretična predvidevanja smo potrdili s simulacijo z MATLABom. Introduction and motivation The price of mixed-signal integrated circuits is dominated by the ever-increasing testing cost of the analog blocks and converters. In particular, the full test of an ADC implies the determination of two kinds of parameters, the static errors linked to some deviations of the converter transfer function, and the dynamic features expressing the distortion and noise of the converted signal introduced by the converter. Static errors are generally deduced from a histogram-based test /1 / lying on a statistical analysis of the occurrence frequency for each output code, while dynamic parameters are usually evaluated from the spectral distribution of the converted signal, computed using a Fast Fourier Transformation (FFT) /2/. Although the principles of both the static and dynamic tests have been well elaborated /1-3/ more work remains to be done on its feasibility issues. The test methods have been originally proposed under the assumption that the input source of reference signal is without uncertainties. Let us assume that the full scale (FS) of a tested 12 bit ADC is in the range of a few V. Then the LSB will be in the range of a few mV. Since, the precision of signal generator should be at least two orders higher than LSB of ADC be- ing tested /3/, in this case the generator absolute error should be in the range of a few hundredths of mV. A serious problem appears here because if it will be 16 bit ADC, the generator absolute error should be in the range of a few thousandths of mV. To avoid such requirements on high precision of input generator a new approach will be presented in the following part of this letter. Originality consists in that all measurements of decision levels of tested ADC are not related to zero potential but to decision levels of an additional ADC. Thus, if this additional ADC is of same type as that to be tested, the maximal measured values will be in the range of a few LSB of tested ADC. To be more detailed, let us assume a tested and additional ADC with an element of transfer characteristic according to Fig.1. By using an ordinary approach the voltages W, V2 are measured in relation to zero potential, while using a new approach the voltages V-1^2 are measured in relation to a decision level output code / of an additional ADC. The voltages in both approaches have to be generated with the same absolute error. However, using new approach the acceptable relative error can be much greater than that in the ordinary approach. The principle of this new method including also a possible hardware realization is depicted in the following sections. output codes i+1 i-1 Transfer characteristic Transfer characteristic of an additional ADC of a tested ADC V, decision levels input voltage Figure 1. Principle of a new approach in testing ADCs Principle of the new method Fig. 2 shows a complete scheme of test system. As it can be seen the output codes of additional and tested ADC are processed in a microprocessor (|j.P). Also DAC, which output voltage through a precise resistive divider R2/Ri is added to input of tested ADC, is controlled by |iP. According to Fig.1, by increasing input voltage from saw-tooth impulse generator, because of given transfer characteristics, the output code / at first will be generated by additional ADC and then with a time delay by tested ADC. However, by adding a voltage from resistive divider fla/fl; which is smoothly greater than Vg the output code / at first will be generated by tested ADC and then with a time delay by additional ADC. Figure 2. Biocl< diagram of new test method To achieve very short time of measurement of voltage difference Vs approximating principle based conversion can be used. For example, by using 8 bits DAC the saw-tooth impulse must be generated 8 times by input generator. During the first impulse is only done a decision whether difference voltage is positive or negative. In case that it is positive value which means that output code / at first will be generated by additional ADC and then with a time delay by tested ADC, the voltage at resistive divider output will be set to FS/2, where FS is a full scale of DAC relating to resistive divider output. During the second impulse is tested by |J,P whether additional or tested ADC at first generates output code /. In case that again at first additional ADC generates output code /, the output voltage of resistive divider will be set to FS/2+FS/4. In opposite case this voltage will be set to FS/2-FS/4. Thus the output voltage of resistive divider is approximately set during the following six cycles. The approximating principle of conversion is well known /4/ therefore here only its summary is made. In the same manner difference voltage Vi' is measured. Since, in this case the measurement is related to decision level of output code / from additional ADC and to decision level of output code /+1 from tested ADC, ^iP tests during each cycle, which one from these output codes is generated as first. From measured Vi', V2 DNL of output code / is calculated using formula /4/ DNL{i) = LSB (1) where LSB is value of ideal least significant bit of tested (additional) ADC. output cudcs Transfer characteristic Ufa tested ADC iDT Tratisfer characteristic of ail additional ADC output voltage of resistive divider voliuge saw-toolh impulse 'I Figure 3. Precision of measured Va' From (1) it is clear that the precision of calculated DNL is determined by precision of measured Vi', \/2- Fig.3a shows an example when the difference between actual decision levels of output code / of tested and additional ADC is smoothly lower than A:7s, where /< is slope of saw-tooth impulse and Ts sampling period. In the moment ti output code /-1 is at output of additional and tested ADC, while in the moment tz it will be output code /. In this case, it is not possible to decide whether by tested or additional ADC at first was generated output code /. Thus, instead to be decreased, the output voltage of DAC will be increased about value FS/2'', where n is actual step of approximating con- version. In the remaining conversion steps this voltage will be increased but with the resolution LSBdac-R?/(Fii+Ft2), where LSBdac is least significant bit of DAC, shown in FigSb. Therefore the maximal error of measured M2 is given by formula R, LSB„ (2) Since the same error is for measured Vi, the maximal error of measured DNL is given by formula and INL = 1 0 0 1 1 0 1 1 1 1 DNL (7) A = 2 R. LSBr, (3) If nominal parameters are such that kTs is about hundredths of LSB, then an extreme change of slope about 100 % reflects to error 2kTs and thus does not influence markedly the resultant precision. Measurement of INL and DNL characteristic It is described in previous section, the difference voltages Vj', 1/2'have to be measured to obtain DNL in given output code ;. In this section, an algorithm is described by using of which the complete INL and DNL characteristic is obtained passing the full scale of tested and additional ADC s times, where s is the number of bits of DAC used. By assuming that DNL = DNL 2 DNL N 2 INL = and INL 2 INL (4) where N is the number of output codes of tested (additional) ADC we can write that --(Vi-V^ DNL={Vi-V2\l LSB-E. (5) where F, = K 2 T ^2 = y. K T K 2 E = and , (6) vy{,v-i).vi Then, for example, because iNL{i)= Y, DNL(r) it could )-=-A'72 seem that maximal error of INL(i) \s A\-N/2-i +1 |. However, it should be noted that maximal error of DNL in (3) does not represent the systematic error, but the maximal value of random signal with rectangular probability of distribution and zero mean /4/. Therefore, the maximal error of measured DNL remains in the range of a few hundredths of LSB. This fact will be verified by simulation with MATLAB in the following section. To measure vector Vi the following algorithm is to be implemented to |.lP. (feciiinilion of ijipiit vniidbf^'s y1=-N)2; y2=-N/2; P=1; A=FS; V2=zeros (N-1,1): : yp=zeros (N-1,1); f - while p<9 o/fe afnv-tooin mipitlu^ a ch' global orfe era iH(:in\ , while i