ON COST FUNCTION PROPERTIES IN ANALOG CIRCUIT OPTIMIZATION Andrej Nussdorfer, Ärpad Bürmen, Janez Puhan and Tadej Tuma University of Ljubljana, Faculty of electrical engineering, Ljubljana, Slovenija Key words: computer aided design, analog circuits, optimization algorithms, cost function, parameter space Abstract: Analog circuit design is a very complex and time consuming process. The largest percentage of the time is spent trying to achieve the best performance by varying the circuit parameters. This is actually an optimization process and there is a growing desire to automate at least a part of the optimization procedure. Unfortunately the optimization algorithms are still very slow. This is mostly due to the sheer number of circuit analyses it takes for the optimization algorithm to converge to a minimum. Obviously any previous knowledge about the shape of the cost function could help the optimization algorithm to converge faster. Unfortunately (again) the shape of the cost function is generally too unpredictable to draw any conclusions prior to the optimization run. This paper tries to show that with a special formulation of the cost function the shape of the cost function itself can be at least partially predicted. Vpogled v značilnosti kriterijskih funkcij optimizacijskih algoritmov Kjučne besede: računalniško podprto načrtovanje, analogna vezja, optimizacijski algoritmi, kriterijska funkcija, parameterski prostor Izvleček: Načrtovanje analognih vezij je zelo zapleten postopek, najtežji del katerega pa je zagotovo določanje optimalnih vrednosti parametrov vezja. Pri tem gre v bistvu za optimizacijski postopek, kjer načrtovalec s spreminjanjem vrednosti parametrov skuša doseči čim boljše delovanje vezja. Zaradi zahtevnosti postopka se pojavlja vse večja želja po določeni avtomatizaciji, to je uporabi optimizacijskih algoritmov za določanje teh parametrov. Žal so optimizacijski algoritmi zelo zamudni, to pa zaradi velikega števila analiz, kijih morajo opraviti. Vsaka vnaprejšnja informacija o lastnostih kriterijske funkcije je zato zelo dobrodošla saj lahko skrajša čas optimizacije. V splošnem velja, da je oblika kriterijske funkcije nepredvidljiva. Ta članek skuša nakazati, daje v določenih primerih mogoče obliko kriterijske funkcije do določene mere vnaprej predvideti. 1. Introduction Analog circuit design is a very complicated job. An engineer performing it must be highly skilled and must posses an intimate know/ledge of circuit topologies. In addition he must have a fairly high amount of patience. The problem lies in the fact that analog circuit design is a trial and error process. As the complexity of analog circuits grows it becomes practically impossible to compute the circuit parameters analytically. The designer has to vary the circuit parameters and simulate the circuit in hope of finding the optimal set of values. As this is actually an optimization problem there is a growing desire to employ optimization algorithms to automate at least part of the task /5-9/. The main reason for computer circuit optimization not to be widely used in circuit design is the computational intensity of optimization algorithms. Although the raw computing power of modern computers is steadily increasing the length of optimization runs is still measured in days. The sheer number of circuit analyses the algorithms require and the size of the parameter space are the main reasons for the slow convergence rate. It is understandable that there is a strong interest in the designer community for such tools and much effort has been (and still is) poured into the investigation of various optimization algorithms. The focus of this research is the minimization of the required number of circuit analyses to perform an optimization run. It is interesting to note that all the research has been fo- cused on the optimization algorithms alone and that the formulation of the cost function has been left untouched. At first glance this would seem reasonable enough as common sense indicates that the behavior of the optimized circuit should vary unpredictably across the parameter space investigated by the optimization algorithm. While this is usually true there are certain cases where the behavior of the cost function in the parameter space can be at least partially predicted and taken into account by the optimization algorithm. This paper tries to shed some light on the properties of a analog circuit cost functions. The paper is partitioned as follows. First the cost function formulation is explained. A mathematical analysis of the resulting cost function follows. The analytical results are then substantiated by the numerical results of optimization runs on real world circuits. Finally the conclusions are summed up and some suggestions for future work are given. 2. The cost function formulation The behavior of a circuit can be described with a number of measurements. More detailed the description must be, more measurements it takes. This is also true for optimization algorithms. The cost function is usually defined as a function of a set of measurements, which are in turn the results of circuit simulations. In most cases this is an ordinary linear combination of suitably weighted measurement values. (■<).sf(.t:) = ni( ii.- -I'C (2) penalty region Figure 1: /4 graphical representation of a criterion function Geometrically the criterion function is the combination of two ramps. The criterion function has two regions, one is the tradeoff region and the other is the penalty region. A measurement value in the penalty region means a working circuit with lower than specified characteristics that is penalized with a positive cost value. A measurement in the tradeoff region belongs to a circuit that meets the design specification and so it is awarded with a negative cost value. Another important concept in robust circuit design that needs underlining is corners. A corner is simply put a set of circuit operating parameters. These can be environmental parameters (temperature, humidity), process parame- ters (process and element tolerances) and operating conditions (supply voltage). Optimization results/1,2/ have already shown that this cost function formulation yields robust circuit designs. Now it must be seen whether there is anything that can be done analytically. 3. Mathematical analysis The problem that will be investigated is the behavior of the cost function when the number of criterion functions increases. To tackle this problem it must be simplified first. There is a number of assumption to be made to make the analytical approach manageable. First only a bounded region of the measurement space will be observed. Second the criterion functions will be evenly spaced across the observed interval of the measurement space. The slopes of all criterion functions will be equal. Fourth the tradeoff coefficients will be all 0. Even if this set of assumptions seems very restrictive there will still be a number of useful conclusions to be drawn from the results. The described configuration is depicted in figure 2. Figure 2: Ttie investigated scenario The notation is as follows: xq and xn are the limits of the observed region, N is the number of ramps, Xn are ramp starting points and x is an arbitrary point in the observed region. The ramps are defined in equation (3). L(-r} = /.•{.r-./■„) :.(■>.(■„ 0 '.i>tli(ririsc (3) The difference between two consecutive Xn is d. An arbitrary point X is then defined in equation (4). •r = ./■(, +/(.i'.v - ./■()) = + (4) and the ramp starting points is expressed in equation (5). .(■„ .C,, + 11(1 = .C,, + [l N\ (I (5) The cost function is then the sum of all ramp functions in the observed interval of the measurement space. (6) Expression (6) is still general but after the substitution of fn(x) with the ramp function definition (expression (3)) the cost function expression (7) is obtained. n=0 !/A' ,f„ + 11(1)) = L'.VJ 11=1) /,7/ .V (7) /,7/ [^..Vj(l/.VJ + I) A" 2 This expression can be improved with the introduction of a new variable e. /:YJ = [t - 0-V = t.\ - fA' i.\ - [/A-J 1 (8) :V A- The floor (LtNj) notation in expression (7) can now be substituted with expression (8) to get the equation (9). (/ -OA'+I) -- /,-(.r,v ---^^^-A- (9) Apart from the simplification of equation (7) expression (8) presents an upper bound for e, which will be useful later. In expression (9) the cost function is dependent on the number of criterion ramp functions N. Since the number of criterion functions is the product of the number of measurements and corners it tends to get very large. It will prove useful to compute the limit of the cost function with N approaching infinity. The result is expression (10). liiii fy(.r) - - .r,,)/ - -lu)! .\ — X, 2 (10) Notice that both x and t are present in expression (10). Since they are both rigidly tied by expression (4) equation (10) can be expressed with just one of them. The variable t can be expressed from equation (4). f = ■I'x ~ 0 (11) The resulting expression (11) can then be substituted in equation (10). hiu I-\(.r) — h-- ,v-x .cx - .in 9 2 ./-.V - .I'll (12) ■Z[.rx - .ri,J (■'■ - ■'■(i) = " (.'■ - -'oJ The resulting expression (12) is obviously a quadratic function of variable x. The conclusion that can be drawn is that the larger is the number of criterion functions the more the cost function resembles half a quadratic parabola. The obtained result applies directly only to the minimization of measurement values. It would be straightforward to show that the same result follows from the analysis of a measurement maximization criterion function. Notwithstanding the interesting results it must be born in mind that the analysis was done in measurement space. The relationships between circuit parameters and measurement values are highly nonlinear Further the assumptions that were made are generally not fulfilled. It must therefore be expected that the shape of the cost function in the parameter space will not be an ideal quadratic parabola. All that needs to be done is to check whether the analytical results resemble in any way real optimization data obtained on a real world test circuit. 4. The test circuit The test circuit is the core segment of a real world operational amplifier The heart of the amplifier is a differential telescopic amplifier stage. The stage consists of transistors m06-m 15. There is also a simplified bias circuitry (mOI -m05) where a complex compensation circuit is substituted by two current sources (iOI and 102) and a common mode feedback circuit (m17-m20). The bias circuit has also a temperature compensation made of the transistors m04 and m05 and the resistor rOI. The schematic diagram of the operational amplifier is shown in figure 3. Figure 4 shows the test application of the operational amplifier. Q-G)- H HE mCS mlC jj C!ü»j |T1!3 nlir SJüääil tEaaiH HieEsna H Figure 3: The schematic diagram of the simplified operationai ampiifier Figure 4: Operational ampiifier test appiication The test-bench circuit simulates the working condition of the operational amplifier. The element values are: rinp and rinm are both 1 mQ, routp and routm are both 1GQ, cinp, cinm, cfbp and cfbm are all 500fF, routp and routm are both 150fF and cgndp and cgndm are both 2.3pF. There are 18 matching groups of optimization parameters in the circuit. These are: 1) the lengths of transistors m03, m06, mil and m16 2) the lengths of transistors m02, m07 and ml 2 3) the lengths of transistors ml 8 and m20 4) the lengths of transistors m08 and m 13 5) the lengths of transistors m09 and m 14 6) the lengths of transistors m05, m10 and ml5 7) the lengths of transistors m 17 and m 19 8) the length of transistor mOI 9) the length of transistor m04 10) the widths of transistors mm02, m03, m06, m07, mil, m12 and m16 11) the widths of transistors ml8 and m20 12) the widths of transistors m08 and m 13 13) the widths of transistors m09 and m14 14) the widths of transistors m05, m10andm15 15) the widths of transistors m 17 and m 19 16) the width of transistor mOI 17) the width of transistor m04 18) the multiplication factors of transistors m 10 and m 15 From the matching groups it is evident that channel widths and lengths of all transistors are optimized in addition to the multiplication factors of transistor ml0 and ml5. There are also 9 corners involved in the circuit evaluation. There are 11 design goals the optimization algorithm must fulfill. These are: Maximum current consumption 0.48mA Maximum common mode feed-back offset 180mV Minimum output swing 2.6V Minimum open loop gain 61 dB Minimum unity gain frequency 90MHz Minimum phase margin 75° Minimum gain margin 13dB Maximum overshoot 0.3% Maximum settling time 11 ns Minimum slew rate 13MV/s Each design goal is checked with a suitable measurement. Combined with the number of corners this means the cost function consists of 99 criterion functions. All trade-off weights are set to 0 and all penalty weights are set to 1. Now the optimization problem has been introduced it is time to see the results. For the sake of clarity only 5 matching group cost profiles out of the 18 will be shown. There are the matching groups 8, 12, 13, 16 and 18. Figures 5-9 show the cost profiles of the cost function for the chosen axes of the parameter space. On each figure there are the profiles of the nine separate corners (thin lines) together with the complete cost function (bold line). As expected the cost function profiles are not exactly quadratic parabolas. Nevertheless it is still notable that they are quite smooth and near the optimal parameter values they are remarkably quadratic-like, specially in the neighborhood of the cost function minimum. This seems to imply that the relationship between the cost function in the measurement space and the cost function in the parameter space becomes linear in the vicinity of the cost function minimum but additional research would be needed to shed more light on the subject. Curvs- 19864 y«0 44617021 Figure 5: The cost profiles as functions of the matching group 8. The profiles In figures 5,6 and 7 are reasonably close the predictions. There is only the question about the spikes that are present on tlie otherwise smooth curves. Before delving into those it is notevi/orthy to have a look at figure 8. In this figure the profiles are full of spikes. A careful analysis of the measurement values near the spikes revealed that the spikes are caused by numerical noise that should have been foreseen. iliiji y, Imag Cuft^d; ^epäces^ @ y^l 02S59374 ; Figure 6: The cost profiles as functions of the matching group 16. The main reason for the spikes is the far too tight overshoot design goal. With such a pressing goal it is normal that the circuit will hover just below the required performance. In such a situation any numerical error in the measurement computations can result in a worse than required performance causing the observed spikes. In figures 5, 6 and 7 the measurements were well clear of the goal threshold so there is a limited number of spikes. In the case of figure 8 on the other hand the circuit hovers right on the goal threshold with the result that the cost profile is extremely noisy. When the spikes are taken into account it can be seen that even the cost profile in figure 8 is reasonably like the profiles in figures 5, 6 and 7. The remaining cost profile in figure 9 differs from the others in one point. It is not smooth. On this figure the cost profile is the function of the multiplication factor of transistors mIO and ml5. Since the multiplication factor is an integer value the steps in the cost profile are expected. Non-smooth cost functions are still a major problem for optimization algorithms /10-13/ so it is remarkable that the optimization algorithm /8,9/ successfully converged to the minimum with little trouble. x, Real Curve; ^^pace^ B. x-e5,832S071 v-1 -10617021 Figure 7: The cost profiies as functions of the matching g roup 12. X. Real Curve: -^^-rpace^^ x=-3.9326ul'92 y=0,01f:)£!510b38 Figure 8: The cost profiies as functions of the matching group 13. )(, Raal Curva m x=S,97SI3015 y«-0.101489362 Figure 9: The cost profiles as functions of the matching group 18. 5. Conclusions The evidence presented in this paper leads to several conclusions. First, the cost function in the measurement space is shown analytically to limit to a quadratic parabola. This is due to the formulation of the cost function /1,2/ and the presence of a large number of corners and measurements needed for a robust circuit design /1-4/. Even if the relationship between measurement space and parameter space cost functions is highly nonlinear this result can still prove highly useful. Second, the cost function of a real-world integrated operational amplifier was studied. The cost function profiles showed a general smoothness while in the vicinity of the minimum the cost function profile displayed a near quadratic shape. This seems to imply that the relationship between measurement space cost functions and parameter space cost functions tends to become linear in the vicinity of the minimum. If proved true this would be in itself a most remarkable result but at this stage it is still too early to draw a definite conclusion. Additional research is needed to shed more light into this subject. Third, the quadratic shape of the cost function in the vicinity of the minimum suggests the development of an optimization algorithm that could exploit such cost function properties. The fact that the quadratic shape is present only in the vicinity of the minimum a multi-stage optimization algorithm is needed. Multi-stage optimization algorithms have been investigated in the past /14-18/ but unfortunately the research was centered on the algorithms themselve without delving into the properties of the underlying cost functions. It would be expected that the exploitation of the quadratic near-minimum cost function shape could help the convergence of optimization algorithms. To build such a multi-stage optimization algorithm suitable basic optimization algorithms would have to be chosen first, then an adequate algorithm for dynamically switching to the appropriate optimization method based on the cost function properties would have to be developed. 6. References /1 / A. Burmen, J. Puhan and T. Tuma, Defining cost functions for robust IC design and optimization, Design, Automation and Test in Europe 2003, pg. 196-201, 2003 /2/ A. Burmen, D. Strie, F. Bratkovič, J. Pulnan, I. Fajfar and T. Tuma, Automated robust design and optimization of integrated circuits by means of penaity functions, AEU international journal of electronics and comunications, vol. 57/1, pg. 47-56, 2003 /3/ M. del Mar Hersherson, S.P. Boyd, T.H. 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Genetic and evolutionary computation conference, Str.42-48, 2003 Andrej Nussdorfer, Arpad Bürmen, Janez Puhan and Tadej Turna University of Ljubljana Faculty of Electrical Engineering Tržaška 25, SI-1000 Ljubljana, Slovenija E-mail: andrej.nussdorfer@fe.uni-lj.si 7. Acknowledgements The research was co-funded by the Ministry of Education Science and Sport (Ministrstvo za Šolstvo, Znanost in Šport) of the Republic of Slovenia through the programme P2-0246 - Algorithms and optimization methods in telecomu-nications. Prispelo (Arrived): 02.06.2004 Sprejeto (Accepted): 20.06.2004