ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), March 2025 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 55, številka 1(2025), Marec 2025 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 1-2025 Journal of Microelectronics, Electronic Components and Materials VOLUME 55, NO. 1(193), LJUBLJANA, MARCH 2024 | LETNIK 55, NO. 1(193), LJUBLJANA, MAREC 2025 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2025. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2025. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Boštjan Batagelj, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Franc Smole, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy Goran Stojanović, University of Novi Sad, Serbia International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Đonlagić, University of Maribor, Faculty of Elec. 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Scientific Council for Technical Sciences of Slovenian Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is cofinanced by Slovenian Research Agency and by Society sponsors. Scientific and professional papers published in the journal are indexed and abstracted in COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™. | Letna naročnina je 160 EUR, cena posamezne številke pa 40 EUR. Člani in sponzorji MIDEM prejemajo posamezne številke brezplačno. Znanstveni svet za tehnične vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 55, No. 1(2025) Content | Vsebina Original scientific papers Izvirni znanstveni članki H. Lavrič, P. Zajec, K. Drobnič, A. Rihar, V. Ambrožič, D. Vončina, M. Nemec: Challenges for Large-Scale Deployment of WBG in Power Electronics 3 H. Lavrič, P. Zajec, K. Drobnič, A. Rihar, V. Ambrožič, D. Vončina, M. Nemec: Polprevodniki s širokim prepovedanim pasom v pretvornikih močnostne elektronike S. Azizian, A. Fathi, S. Azizian, B. Mashoufi, M. S. Dilmaghani: CMOS Low-Power, Fully-Programmable Gaussian/ Trapezoidal Fuzzy Membership Function Generator 25 S. Azizian, A. Fathi, S. Azizian, B. Mashoufi, M. S. Dilmaghani: CMOS nizkoenergijski programabilni gausov/ trapezoidni fuzzy funkcijski generator P. Ramesh, B. Mohan, H. Rajamanickam, R. V. Jaikumar, A. Lakshmanasamy: Efficient Resource Allocation for Ultra Reliable Low Latency Communication Delay Minimization in Fifth Generation Networks 37 P. Ramesh, B. Mohan, H. Rajamanickam, R. V. Jaikumar, A. Lakshmanasamy: Učinkovita dodelitev virov za izjemno zanesljivo komunikacijo z nizkimi zakasnitvami za zmanjšanje zakasnitev v omrežjih pete generacije A. Thangam Manoharan, B. Thangaraju: Fractal Resonator Based Frequency Reconfigurable Antenna with Varying Capacitive Effect for Wireless Applications 47 A. Thangam Manoharan, B. Thangaraju: Frekvenčno nastavljiva antena s spreminjajočim se kapacitivnim učinkom za brezžične aplikacije, ki temelji na fraktalnem resonatorju M. Babaeian Far, M. A. Ormancı, F. Kaçar: Design and Optimization of Multiple-Channel Double Dynamic Switching Biased Op-Amp for Switched Capacitor Integrator Using FinFET Technology 55 M. Babaeian Far, M. A. Ormancı, F. Kaçar: Načrtovanje in optimizacija večkanalnega dvojnega dinamičnega preklopnega optičnega ojačevalnika za stikalni kondenzatorski integrator z uporabo tehnologije FinFET J. Liu, L. Li: A Low-Power and Low-Noise 4-12 GHz Buck CMOS Low-Noise Amplifier with Current-Reused Technique 65 J. Liu, L. Li: Ojačevalnik 4-12 GHz CMOS z nizko porabo energije in nizkim šumom s tehniko ponovne uporabe toka Announcement and Call for Papers: 60th International Conference on Microelectronics, Devices and Materials with the Workshop on Energy Management and Renewable Energy Sources 73 Napoved in vabilo k udeležbi: 60. mednarodna konferenca o mikroelektroniki, napravah in materialih z delavnico o upravljanju z energijo in obnovljivih virih energije Front page: Close-up view of a GaN transistor leg in a multi-leg DC/DC power converter (H. Lavrič et al.). Naslovnica: Podroben pogled na GaN tranzistorsko vejo v večvejnem močnostnem pretvorniku (H. Lavrič et al.) 1 Editorial / Uvodnik Respected readers, Over the last years, our journal operations and processes ran smoothly and I am grateful to EB members, reviewers and technical support team for their valuable contribution to the success. Since 2019 all published papers are openaccess (under CC-BY Creative Commons Attribution 4.0 License) and available in WoS, Scopus, DOAJ or on the journal web pages by a single mouse click. I sincerely hope that open-access policy help us in wider dissemination and larger readership. In 2024 we received more than 290 manuscripts, out of which only 23 have been accepted for publication so far, while 113 were out of scope and more than 150 manuscripts were rejected. The success rate remains low (below 10% in 2024) primarily because we receive many manuscripts are out-of-scope or do not meet the quality and scientific originality that we aim at. Citation metrics for 2023 (released in June 2024) is sound: • JCR IF-2023= 0.6, • SNIP-2023=0.366, • CiteScore-2023=1.80, which according to SCOPUS ranking positions us at 34th percentile (3rd quarter, Q3) of the journals in the field of Electrical and Electronic Engineering, i.e. 525th place out of 797 journals. In 2024 we published • 1 review scientific paper (on free software support for compact modelling with Verilog-A) and • 22 original scientific papers. Here is the link to access them directly. We strive and look forward to serving you as a part of your success in science and engineering and look forward to receiving your future manuscript(s) on our submission page (http://ojs.midem-drustvo.si/). Take care and stay healthy! Be productive, efficient and innovative! Prof. Marko Topič Editor-in-Chief 5 March 2025 2 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.101 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 3 – 23 Challenges for Large-Scale Deployment of WBG in Power Electronics Henrik Lavrič, Peter Zajec, Klemen Drobnič, Andraž Rihar, Vanja Ambrožič, Danjel Vončina, Mitja Nemec Fakulteta za elektrotehniko, Univerza v Ljubljani, Ljubljana, Slovenia Abstract: As the demand for efficient and high-performance power electronic devices continues to grow, wide bandgap (WBG) semiconductors have emerged as a promising solution due to their superior characteristics. However, realizing their full potential requires not only the development of advanced semiconductor materials but also the optimization of packaging techniques. This paper examines the crucial role of packaging in leveraging the benefits of WBG devices, with a particular focus on mitigating inductance and addressing other critical concerns. Drawing from previous research and discussions, we explore various strategies to minimize inductance effects, enhance thermal management, ensure reliability, and optimize electrical performance. Through an interdisciplinary approach that encompasses electrical engineering, materials science, and mechanical engineering principles, this paper highlights the latest advancements in WBG device packaging, providing valuable insights for researchers and engineers working towards more efficient and reliable power electronic systems. Keywords: wide bandgap; semiconductors; power electronics; packaging; design Polprevodniki s širokim prepovedanim pasom v pretvornikih močnostne elektronike Izvleček: Ob nenehno naraščajočem povpraševanju po učinkovitih in visokozmogljivih napravah močnostne elektronike, se polprevodniki s širokim prepovedanim pasom (WBG) zaradi svojih izjemnih karakteristik kažejo kot obetavna rešitev. Uresničitev njihovega polnega potenciala poleg razvoja naprednih polprevodniških materialov zahteva tudi optimizacijo tehnik načrtovanja in pakiranja. Članek predstavi ključno vlogo načrtovanja pri izkoriščanju prednosti WBG naprav, s posebnim poudarkom na zmanjševanju induktivnosti in obravnavanju drugih ključnih vprašanj. Na podlagi prejšnjih raziskav in razprav raziskuje različne strategije za zmanjšanje učinkov parazitnih parametrov, izboljšanje odvoda toplote izgubnih moči, zagotavljanje zanesljivosti in optimizacijo električnih zmogljivosti. S pomočjo interdisciplinarnega pristopa, ki zajema načela elektrotehnike, materialov in strojništva, članek poudarja najnovejši napredek pri načrtovanju WBG naprav ter ponuja dragocen vpogled raziskovalcem in inženirjem, ki si prizadevajo za bolj učinkovite in zanesljive sisteme močnostne elektronike. Ključne besede: širok prepovedan pas; polprevodniki; močnostna elektronika; pakiranje; načrtovanje * Corresponding Author’s e-mail: andraz.rihar@fe.uni-lj.si 1 Introduction emergence of new applications, including transportation electrification and renewable energy systems. Over the past few decades, various sectors, including aerospace, automotive, consumer electronics, industrial, and utilities, have increasingly adopted partial or complete electrification and digitization. This transition, largely driven by advancements in power electronics [1], has not only enhanced existing systems such as industrial electric drives but also facilitated the By 2030, it is estimated that power electronics will be instrumental in processing about 80 % of global energy production and consumption, underscoring their critical role across multiple industries. Concurrently, the global power electronics market has seen substantial growth, with its value reaching approximately $20 How to cite: H. Lavrič et al., “Challenges for Large-Scale Deployment of WBG in Power Electronics", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 1(2025), pp. 3–23 3 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 billion in 2022 (Figure 1). This market is forecasted to expand to around $32.6 billion by 2032, reflecting the increasing dependence on integration of power electronics technologies in diverse applications [2]. crease, minimizing inductance is critical for harnessing the high-frequency capabilities of WBG devices. Figure 1: Projections of global market size for power electronics in $ billion. Adapted from [2]. An important shift in modern power electronics is an increasing adoption of wide bandgap (WBG) semiconductor devices [3], which offer superior performance characteristics compared to traditional silicon-based devices. WBG semiconductors, particularly silicon carbide (SiC) and gallium nitride (GaN), are pivotal in driving technological advances across various industries due to their ability to operate at higher efficiencies, frequencies, and temperatures, thus boosting reliability and enabling reduced size and higher power densities. Figure 2: Typical applications with Si and WBG semiconductor switching devices, positioned according to their approximate rated values in terms of output power (kW) and operating frequency (kHz). Moreover, the demand for compact, lightweight, and thermally efficient packaging solutions adds another layer of complexity to designing and implementing WBG device packages. Traditional packaging materials and techniques may no longer suffice to meet the stringent requirements imposed by the unique characteristics of WBG semiconductors, necessitating innovative approaches and materials to ensure optimal performance and reliability under various operating conditions. These improvements are especially important for applications in sectors such as renewable energy, automotive, and industry, where improved performance leads to greater energy savings and reduced environmental impact (Figure 2). The global market for WBG semiconductors is still relatively small but expected to exceed $5 billion by 2032 [4]. This paper begins with an analysis of the switching phenomena in semiconductor devices (Section 2), followed by a review of WBG semiconductors including material properties, benchmarks, and benefits over silicon-based devices (Section 3). In Section 4 we discuss the effects of WBG device packaging, focusing on parasitics, thermal management, and reliability. Section 5 addresses packaging technologies for mitigation of parasitics effects, covering die attach methods, topside bonding, and innovative cooling strategies. Techniques for enhancing system performance through the integration of gate drivers, passive devices, sensors, and cooling bodies are outlined in Section 6. Section 7 details parasitics parameter estimation techniques and describes design optimization through co-simulation, as well as machine learning (ML) and artificial intelligence (AI) concepts. The paper concludes with a summary of key findings and future directions for WBG technology research in power electronics (Section 8). However, to fully realize the potential of WBG technologies, several issues must be addressed. Foremost among these is the development of robust packaging solutions capable of withstanding the increased thermal and electrical stresses present in high-performance applications [3], [5]. Additionally, the optimization of device characteristics, such as switching speeds and thermal management, is essential to reduce losses and improve the overall reliability of devices. One of the key challenges in packaging of WBG devices is the mitigation of parasitic elements such as inductance, capacitance, and resistance. These elements can affect device performance and reliability, with inductance being particularly problematic due to its impact on switching transients, power losses, and electromagnetic interference (EMI). As operating frequencies in- 4 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 2 Power electronics: why switching frequency and transition times matter During the switching action (Figure 4) the transistor is transitioning from off-state to on-state, voltage across the terminals is slowly decreasing after the current increases. A comparable situation occurs when the transistor switches back to the off-state. Power electronics focuses on efficient control of energy flow using semiconductor switches. Various converter topologies are employed, each designed for specific applications and performance criteria. The half-bridge topology is the most common one. This configuration typically consists of a switching leg with two serial connected power switches (Q1 and Q2) and either integrated or external freewheeling diodes, as illustrated in Figure 3. Switching losses Psw in MOSFETs occur during these transitions. When the MOSFET is off (VGS = 0 V), the voltage VDS between the drain and source is blocked by the device, resulting in zero current (IDS = 0 A) and no energy dissipation. Upon turning on the MOSFET, the current IDS begins to increase, while VDS remains constant until IDS reaches its steady-state value. Subsequently, VDS decreases to nearly zero, indicating the MOSFET is fully on and conduction losses commence. The instantaneous power during this transition forms a triangular profile, with the area beneath representing the energy dissipated during turn-on event. The transition time comprises the current rise tcr and voltage fall tvf times. Turn-off losses are analogous to turn-on losses. In the on-state, VDS is minimal, and current flows through. When turning off, VDS increases while IDS initially remains constant. Once VDS reaches VDC, IDS decreases to zero. The energy dissipated during turn-off is similarly represented by the area beneath the power curve. Switching losses are a sum of turn-on and turn-off power losses that are determined by the product of the dissipated energy and the switching frequency. Figure 3: Switching leg with indicated input voltage/ current and output voltage/current. Conduction losses Pcond in a MOSFET occur when the device is on (VDS = Von) and conducting Iout. The path between the drain and source acts as a resistance, denoted as RDS,on. Thus, the conduction losses depend on the RMS current squared multiplied by the resistance and duty cycle. The losses in off-state can be ignored, as leakage current is negligible. Figure 4: Simplified switching waveforms for turn‐on and turn-off transitions in a half‐bridge circuit for upper transistor Q1 Thus, total power losses Ptot for switch Q1 are In a half-bridge converter, the switches Q1 and Q2 are usually driven complementarily using Pulse Width Modulation (PWM) logic signals, producing two distinct voltage levels at the output terminal. The converter operates with a constant input voltage VDC. When Q1 is on, the output terminal connects to the positive voltage rail; when Q2 is on, it connects to the negative voltage rail. An output inductance Lout is typically included to smooth the output current Iout. Ptot  Psw  Pcond t t t t  VDS I DS f sw  cr vf  cf vr 2 2   2   I DS RDS,on D  (1) The thermal power in a converter attributed to losses must be removed by a cooling system. In most applications, the maximum output power is limited by thermal resistance (Rth) and the capacity of the cooling system to dissipate this heat, thereby limiting the overtemperature. Thus, the high-efficiency power switches allow for reduced cooling requirements which enables the design of devices with higher power density. Further reduction in volume and mass can be achieved by using smaller passive components such as capacitors and inductors. If output (and load) inductance is high enough we can simplify the analysis by assuming continuous output current and represent the converter as a constant current source Iout. Consequently, when the individual switch undergoes a state transition, a dead-time interval initiates during which the current commutates from the switch to the body diode of the opposite switch. 5 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 Throughout periodic switching transitions, the average output voltage can be adjusted in accordance with the desired duty cycle mandated by PWM, thereby regulating the current flowing through the predominantly inductive output circuit. However, its RMS value is also subjected to the triangular waveform‘s superimposed AC component. Its peak-to-peak amplitude is directly influenced by the load‘s inductance, thereby impacting the physical dimensions of the inductor. In conventional semiconductors, the bandgap typically falls within the range of 0.6 eV to 1.5 eV. For example, germanium, silicon, and gallium arsenide have bandgaps of approximately 0.66 eV, 1.12 eV, and 1.42 eV, respectively [6]. Wide bandgap semiconductors are those with an energy gap of over 2.0 eV, including GaN and SiC, which are considered current or future alternatives to Si. In addition to wide bandgap semiconductors like GaN and SiC, the term ultrawide bandgap semiconductor applies to materials with even larger bandgaps, such as diamond and AlN [7]. These, along with Ga2O3, are considered by some to be the semiconductor materials of the future [8], [9]. In the case of additional smoothing capacitors inserted behind the inductor, such as in DC/DC converters, a similar correlation between the switching frequency and the RMS current of the capacitor emerges. In both scenarios, passive elements can be significantly reduced in size (and cost) with an increase in switching frequency. 3.1.2 Physical material properties The most important physical properties of semiconductor materials are summarized in Table 1. The values or ranges of values in the table consist of minimum and maximum values obtained from various sources and are also to some extent conditioned by the development and progress of research over the years [8], [9], [10], [11], [12], [13], [14], [15], [16]. Some parameters are more and others less temperature-dependent [17]. For GaN technology, the upper value of electron mobility equals 2000 cm2/Vs for the 2DEG layer [12]. This is a 2D layer of freely moving electrons (two-Dimensional Electron Gas) that forms at the interface between AlN and GaN materials due to the polar properties of the base cells of the crystal structures and the shear force at the interface between the two materials [18]. The freely moving electrons in the 2DEG layer essentially make the GaN HEMT (High Electron Mobility Transistor), a normally on transistor. 3 WBG semiconductors: material characteristics and operational benefits WBG semiconductors have emerged as an alternative to traditional silicon due to their ability to operate more efficiently and/or to withstand higher voltage and temperature. This chapter focuses on their material properties and operational advantages. The section begins by classifying their bandgaps and detailing their physical material properties, and then discusses various benchmarking metrics. Towards the end, the chapter covers the system-level benefits of using WBG devices and provides a brief comparison of today’s commercially available WBG devices, specifically SiC and GaN. The wider bandgap leads to better electrical stability of the material at higher electrical fields and higher temperatures. WBG dies are therefore smaller compared to silicon ones, have better channel conductivity in the conduction state and enable higher switching speeds. The higher values of these two parameters are due to the easier movement of electrons through the crystal structure of the material under the influence of an electric field. The smaller dimensions of the WBG dies and consequently the smaller electrode dimensions as 3.1 General WBG characteristics 3.1.1 Bandgap classification The bandgap is essentially a non-existent or forbidden energy state for electrons, and its value equals the difference between the minimum energy of electrons in the conduction band and the maximum energy of electrons in the valence band. It is expressed in eV (electron-Volts) and depends on the type of material. Table 1: Basic material properties including minimum and maximum values from the sources [8] - [16]. Bandgap EG Critical electric field EC Electron mobility μ Hole mobility μH Thermal conductivity λ Relative permittivity εr Electron saturation velocity νS Si 1.1 - 1.12 0.3 - 0.4 1350 - 1500 450 130 - 150 11.8 1 4H SiC 3.25 - 3.26 2.0 - 3.18 650 - 1000 90 - 120 370 - 700 10 2 6 GaN 3.39 - 3.44 3.0 - 3.5 900 - 2000 10 - 120 110 - 210 9.0 - 9.5 2.4 - 2.5 Diamond 5.46 - 5.6 4.0 - 7.0 1800 - 2200 1800 600 - 2300 5.5 2.3 - 2.7 AlN 6.2 15 450 285 - 340 8.5 1.4 Unit eV MV/cm cm2/Vs cm2/Vs W/mK 7 10 cm/s H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 well as the slightly lower values of the relative permittivity result in small parasitic capacitances of the dies, which further accelerate the switching processes. Fast switching ensures low switching losses and the low resistance of the channel in the conductive state ensures low conduction losses. The small parasitic capacitances at the gate of the transistor also lead to low driving losses [19]. The blocking state of WBG dies is characterized by a lower leakage current, as fewer charge carriers are released due to the large bandgap. In WBG dies, there is only a very small, practically negligible (SiC) or no (GaN) reverse recovery charge, as the latter have no inherent reverse conducting diode. The lower power losses of the individual contributions lead to relatively low total power losses during device operation. The physical properties of the materials enable higher operating temperatures and better thermal conductivity, so that heat can be dissipated more efficiently. Figure 5: Specific resistances for five semiconductor materials; the calculations are based on minimum and maximum values of parameters taken from various sources. losses are due to the charging and discharging of the specific input capacitance Cin. It has essentially been defined as the reciprocal of the product of specific resistance and specific input capacitance and is written with certain assumptions regarding the basic material properties [20] and the assumed control voltage at the gate of the transistor VG 3.1.3 Material’s benchmarking Based on certain physical parameters, various authors have derived criteria for comparing the performance or suitability of materials for specific applications, which can also be used to predict to some extent the properties of the semiconductor devices produced. Johnson’s Figure of Merit (JFOM) gives a power-frequency product for low-voltage transistors. Keyes’ FOM predicts the switching behaviour of transistors in integrated circuits. For power transistors, two Baliga’s FOMs are of interest [20]. The first (BFOM) represents the denominator in an expression for calculating the specific resistance Ron of a material in the conductive state Ron  BHFFOM  VG 1    EC2  . Ron  Cin 4  VB3 (3) The BHFFOM versus breakdown voltages for the minimal and maximal values of the individual materials listed in Table 1 are shown in Figure 6. Different VG values were used for the calculations, namely 15 V for Si, 20 V for SiC and diamond, and 6 V for GaN and AlN. As can be seen in Figure 6, SiC has a BHFFOM value 25 times higher than Si and GaN has a value more than 40 times higher than Si. 4  VB2 4  VB2 . (2)  3  r    EC BFOM The BFOM essentially indicates the dependence of the conduction losses on the physical properties and is a measure of the performance of materials for low-frequency operation. The calculated dependencies of the specific resistances on the breakdown voltage VB for the parameter limits of the individual materials listed in Table 1 are shown in Figure 5. The minimum values of the individual parameters were considered for the lines marked with _min (solid lines), while the maximum values were taken into account for the lines marked with _max (dashed lines). Explicitly, Figure 5 shows that the specific resistance of SiC is a hundred times or more lower than the specific resistance of Si and the specific resistance of GaN is four times or more lower than the specific resistance of SiC. Figure 6: BHFFOM for five semiconductor materials, taking into account the minimum and maximum values of the material properties. The second performance metric, BHFFOM (Baliga’s High Frequency FOM), establishes the link between the physical characteristics and the ability to operate at higher frequencies, where a significant portion of the The total losses on the power FET can be calculated by using BHFFOM and assuming Irms in the conduction direction 7 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 2 P  I rms  Ron A  VG2 f . (4)   A Ron BHFFOM The situation for the switching transistor is optimal with minimum losses, which are obtained by deriving eq. (3) on the area of A (dP/dA=0) Pmin  2 I rmsVG  f . (5) BHFFOM Finally, the required minimum area of the die is determined by R f . (6) Amin  I rms  on  BHFFOM VG Figure 8: Die area ratios for various semiconductor materials, taking into account minimum and maximum values of the material properties. 3.2 System advantages and market overview The power loss ratios for the materials under consideration are shown graphically in Figure 7 and for the area ratios in Figure 8. The superiority of wide bandgap materials over Si is clear in Figure 7, but even more evident in Figure 8. It can be seen that the theoretically required active material area of the WBG dies is less than 3 % of the Si material area. In practice, the physical implementation of dies with extremely small areas is difficult due to the implementation of physical contacts and the efficient dissipation of waste heat. 3.2.1 System benefits of using wbg devices Figure 9 outlines the advantages of WBG semiconductors over traditional silicon-based devices, tracing the impact from material properties to system-level benefits. WBG semiconductors possess a low intrinsic carrier concentration and a high critical electric field, leading to beneficial device properties (Table 2), such as breakdown voltage VB,DSS, Figure of Merit (FOM), thermal conductivity coefficient λ, gate threshold voltage VG,th, and reverse recovery charge Qrr. Low on-resistance reduces power loss during operation, while high blocking voltages improve suitability for high-power applications. The combination of low on-resistance and high blocking voltage reduces conduction and switching losses. This enhancement not only improves device efficiency but also allows for higher switching frequencies compared to traditional silicon-based devices. Consequently, it enables the use of smaller passive filter components and cooling solutions, significantly reducing both the size and weight of the overall system. Overall, WBG semiconductors have become the first choice for high-power and high-frequency applications. Figure 7: Power loss ratios for various semiconductor materials, taking into account minimum and maximum values of the material properties. Table 2: Comparison of main characteristic parameters for Si, SiC and GaN HEMT technologies [21]. Technology VB,DSS Avalanche capability Short circuits RDS(A) FOM λ VG,th Normalized die area Qrr Reverse diode effect Vforward Si-MOSFET (SJ) > 1200 YES YES 10 1.5 3.5 5x 10,000 ~1.5 SiC-MOSFET > 1200 YES YES 2-3 5 2.8 1x 76 ~4 8 GaN HEMT Cell 650 NO NO 3-7 1.3 1.3 1.5x ~0 1.3-6 Unit V mohm·cm2 W/cm2K V nC V H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 Figure 9: Impact of WBG semiconductor properties on system performance. Figure 10: Graphical visualization of material characteristics using typical values for Si, SiC and GaN. 3.2.2 WBG market presence: SiC and GaN devices SiC and GaN dominate the commercial market for wide bandgap (WBG) power devices, each offering distinct advantages over traditional silicon in power electronics. The commercialization of SiC devices began with the first SiC Schottky barrier diodes (SBDs) introduced to the market by Infineon in 2001 and the first SiC MOSFETs in discrete packages by Cree and Rohm in 2010– 2011. SiC devices are now commercially available in the voltage class of 650–3300 V [22]. The principal benefits of SiC devices are most evident in applications within the automotive and energy sectors, where their high efficiency and high-voltage blocking capability are required. higher specific losses compared to GaN, thus improving overall system performance and reliability. 4 Packaging: electrical and thermal challenges The use of bare semiconductor dies is uncommon due to handling and reliability concerns. Therefore, semiconductor dies are typically enclosed in various packages containing critical components, such as the semiconductor dies, substrates, baseplate, die bonding, and encapsulant (Figure 11). The market introduction of GaN power devices dates back to 2010 when International Rectifier released the first GaN-based power transistor. The commercially available GaN devices are primarily classified as lateral GaN HEMTs, which have brought significant benefits to applications that demand high frequency and efficiency, particularly in RF and power supply sectors. GaN devices are currently available primarily in the voltage class of 100–650 V. Figure 11: Mockup view of the package cross section showing the power devices (dies with die attachment and bond wires), soldered onto a baseplate. Adapted from [23]. Figure 10 compares typical values of key material properties of GaN, SiC and Si. GaN devices, with their high electron mobility, inherently support much higher switching frequencies. They operate effectively at relatively high voltages due to their high critical electric field and exhibit lower leakage currents. In contrast, SiC devices have significantly higher thermal conductivity, enabling better heat dissipation. This advantage is particularly beneficial as it compensates for the relatively The primary function of the baseplate is to mechanically support the substrate. This is usually a ceramic (alumina, aluminum nitride or silicon nitride) with a metallization of copper (DBC – Direct Bonded Copper) or aluminum (DBA – Direct Bonded Aluminum) on the top and bottom. The top side of the DBC is attached to 9 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 the semiconductor power die and supports heat dissipation and electrical conduction, similar to bond wires. The bottom of the DBC is soldered to the baseplate to provide a path for semiconductor chips to dissipate heat, while the core of the DBC provides electrical isolation. The power terminals, including bond wires, provide the electrical connection between the die and the external circuit. Environmental effects have a significant impact on the performance of the power module and make protective measures necessary. In conventional packaging, an encapsulant covers the surfaces of power devices and bond wires to protect against adverse environmental conditions such as exposure to chemicals, humidity, and gases. Consequently, all elements, except the bottom side of the baseplate, are encased in a plastic covering. Figure 13: Equivalent circuit of a transistor leg containing structurally introduced parasitic inductances in power and gate drive loop interacting with die capacitances of the MOSFET (A). Subfigures (B)-(D) show various source contact configurations [27]. 4.1 Power and gate drive commutation loop parasitics Furthermore, it is essential to understand that the causes leading to the deteriorated switching performance extend beyond the boundaries of the device package. They encompass all high-frequency current commutation paths (Figure 13), including components like the DC link capacitor, the interconnected traces on printed circuit boards (PCBs), as well as stray capacitances between the power and the gate drive and towards the heatsink (not depicted in Figure 13). The package structure and applied materials significantly influence the electrical and thermal performance of the device. Specifically, they introduce additional stray resistance, inductance, and capacitance into the power and gate drive loops. These interact with the inherent capacitances of the semiconductor device, which are the key factors in turn-on/off switching behaviour, impacting switching losses, voltage and current oscillations, and resulting in thermal stress [24], [25]. The effect of these parasitics varies on the type of packaging used, as illustrated in Figure 12, and varies on the source contact configurations inside the package, as shown in Figure 13. With the increased switching speeds of WBG devices, the circuit experiences higher induced voltages due to the inductance (Lσ). This results in drain-source voltage overshoot and significantly elevates the voltage stress on MOSFETs compared to their (Si) counterparts. Additionally, the Lσ can during the switching transients resonate with various capacitors, such as the MOSFET output capacitor and the body diode junction capacitance. This resonance can couple into the gate drive loop through the Miller capacitor, affecting the driver signal [28]. As a result, this interaction increases switching losses [23] and generates high-frequency electromagnetic interference (EMI). 4.2 Thermal aspects of packaging In addition to electrical considerations, the design and materials used in packaging are critical for determining heat dissipation capabilities, which in turn affect the overall mechanical design of the converter. As modern WBG devices become more efficient, their physical footprint decreases. Consequently, the heat flux is concentrated over a smaller die area, and the reduced dimensions of the packaging limit heat spreading and dissipation, leading to hotspots within the device. In- Figure 12: Comparison of parasitic inductance values and switching energy loss for different package types. Adapted from [26]. 10 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 creased temperatures can also compromise the reliability of bonding, interconnections, and insulation layers. To prevent power derating and improve power density, packaging design must address both electrical and thermal aspects simultaneously [23], [28]. - 5 Mitigating parasitic effects and thermal challenges in packaging thermal conductivity substrate materials (such as Al2O3, AlN, and Si3N4) [29] are crucial. Considerations also include managing the coefficient of thermal expansion (CTE) mismatch and integrating of heat-spreading materials. High-temperature capability: Ensuring reliability at temperatures exceeding 200 °C. Cost-effective production: Focusing on precision and reliability in the manufacturing processes. The importance of these factors varies by application, such as in automotive systems or custom electronic chargers, highlighting the need for specialized packaging solutions tailored to specific voltage, current, and power requirements in different contexts. To fully leverage the advantages of WBG materials [Vecchia, 2019], which are capable of operating efficiently at high temperatures, frequencies, and voltages, traditional packaging designs used for Si-based semiconductors are no longer adequate. 5.1 Die attach For silicon devices, the dies are generally attached to the substrate using lead (Pb)-based solders. These solders have lower thermal conductivity compared to the much higher thermal conductivity of WBG devices. Consequently, WBG devices are usually attached using sintering processes performed under controlled temperature and pressure conditions. Another commonly used method is transient liquid-phase bonding [30], [31]. When selecting materials, factors such as melting temperature, thermal conductivity, and CTE must be considered, as they influence performance degradation during thermal cycling. Key drivers for optimizing packaging designs for power devices include: High-speed switching and short current paths: This necessitates advancements in bonding techniques such as using new materials, employing copper clips instead of wires, and adopting ribbon bonding. High current carrying capability: Achieved by integrating copper layers with thickness of up to 300 micrometers. Die attachment methods: Incorporating advanced techniques such as sintering and soldering, whether single-sided or double-sided. Enhanced cooling efficiency: Techniques such as double-side cooling, thermal vias, microchannels for liquid cooling, and the use of high However, many current materials and designs are not suitable for operating temperatures above 250 °C. Silver (Ag) sintering is becoming a preferred alternative due to its benefits, including lower thermal resistance Table 3: New innovative die attach techniques for SiC [26]. Die attach technology Semi Ag sinter Full Ag sinter Cu sintering AuSn eutectic (80/20) die backside Thermal conductivity Advantages 75-100 W/mK - Lower Rth - Thinner BLT - HVM - Enables 200 °C 150-300 W/mK - Lower Rth - Better BLT control - Better surge - Higher power density - Enables 200 °C 150-250 W/mK - Lower Rth - Better surge - Higher power density - Lower cost - Enables 200 °C 57 W/mK - Lower Rth - Thinnest BLT - Better BLT control - Non-Pb 11 Risks - Volatiles - Ag migration - New die/LF interface - Die size limitation - Ag migration - High thermo-mechanical stresses - Voiding/porosity - No HVM at assembly vendor - Process challenges - Storage challenges - High thermo-mechanical stresses - Die size limitation - Voiding H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 (Rth), reduced bond line thickness (BLT), and support for higher operating temperature of up to 200 °C (Table 3). Despite these advantages, concerns about Ag migration and increased thermo-mechanical stresses remain. Pressureless Ag sintering, which uses a polymer matrix for densification is a viable option but may offer inferior Rth compared to pressure-assisted methods. While copper (Cu) sintering is cost-effective and provides lower Rth, its use is limited by the lack of a film-based format and the need for an inert atmosphere. Gold-tin (Au-Sn) eutectics offer a significant advantage with a notably reduced BLT of just 3-4 µm, compared to the more than 50 µm typical of other materials. to optimize bonding processes without changing chip metallization. Moreover, Al and Cu ribbon bonding (Figure 14 C, D) provide a compelling solution for higher current carrying capabilities and improved power cycling performance [31], [36]. 5.2.1 Mitigating the magnetic field in the commutation loop Traditional wire-bonding methods have inherent drawbacks, such as increased parasitic inductance and impeded power module switching speeds. Additionally, predominant material failures like bond wire lift-off and heel cracks, caused by thermomechanical stress, elevate bonding failure to a critical operational concern during power and thermal cycling. In 2002, Nexperia introduced Cu clip bonding technology (Figure 15), marking a significant advancement in power module assembly. Replacing conventional wire bonds with flat Cu clips not only reduces parasitic inductance but also improves heat dissipation from the die’s surface. While this approach has been initially introduced for Si technology it has since been transfered to WBG devices [37]. Mechanical stresses resulting from power and thermal cycling can lead to cracks between the substrate and die. As a result, self-healing die attachment has become a notable area of interest. However, this emerging technology is still in its developmental stages and may present risks to improving package reliability [32]. 5.2 Topside-bonding (A) (B) Figure 15: Example of bond-wire and clip-lead power SOP-8 leaded packages [38]. (C) ONSEMI reported a 14 % reduction in junction-to-case thermal resistance for a single-sided PQFN package compared to its conventional wire-bonded counterpart. Nexperia’s LFPAK88 package, on the other hand, boasts a source inductance that is five times smaller than that of the D2PAK package [39] (Figure 16). (D) Figure 14: Top: wire-bonding: (A) Cu wire-bonding, (B) Cu-Al wire bonding. Bottom: Ribbon bonding: (C) Al ribbon, (D) Cu ribbon [35]. The prevalent use of conventional wire bonding in commercial SiC power module packaging is attributable to its compliance with stringent testing standards, such as successfully passing power cycle tests exceeding 20 million without failure [33], [34]. Aluminum (Al) wires, typically 20 mils in diameter, are predominantly used for wire bonding, despite their limitations on pad size and bonding throughput. Alternatives like heavy Cu wires (Figure 14 A) offer better current capacity and superior thermal conductivity compared to aluminum, as well as enhanced reliability, although they require additional processing steps such as die top system integration or plated topside Cu layers [35]. These challenges are effectively addressed by novel composite materials that combine Al and Cu (Figure 14 B), aiming Figure 16: Power package parasitic resistance (bars) and inductance (line) [38]. 12 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 In 2011, Semikron-Danfoss introduced SKiN technology, a concept designed to minimize stray inductance in their 750 V/1200 V six-pack compatible package. Instead of a solid Cu clip, they utilized a two-layer flex foil tightly positioned over the top and bottom transistors, creating three-layer current paths with minimal loop area. This approach is also employed in standard power stage modules [40], where Ag sintering is used to connect one side of the power chip to the DBC and the other to a flexible circuit board for current conduction. This design achieves remarkably low stray inductance, measuring as low as 2.5 nH per module, including overlapping terminals (DC+ and DC-, Figure 17). In comparison, the equivalent SEMITRANS module exhibits 15 nH stray inductance. The reduction in inductance in structures with close-fitting parallel traces is due to the cancellation of the magnetic field by having opposite current paths. Additionally, a separate study highlights that a significant portion of this reduction is attributable to the overlapping terminals alone. However, replacing Al material with flexible circuit boards imposes limitations on packaging reliability at high temperatures. tures from liquid coolants. A notable example is Infineon’s HybridPACK DSC (Double Sided Cooling) Power Module featuring SiC MOSFETs. Since the DSC module utilizes indirect cooling, optimizing the thermal interface material (TIM) becomes crucial. Remarkably, the Rth of a DSC module can be reduced by 40 % compared to a single-sided cooled module of the same footprint operating under identical conditions [43]. Figure 18: DSC package and its thermal stack A refined thermal stack configuration, illustrated in Figure 18, showcases improved efficacy. In this design, dies are attached and electrically interconnected on both the top and bottom of DBC. Instead of using traditional spacers, which mainly offer structural support and, in some stack configurations, apply sufficient pressure on current pads to form spring-interconnected stacked power modules, this configuration replaces solder bumps or advanced alternatives with a goldplated pin-fin-based copper connector (Figure 19). This substitution enhances reliability and addresses common issues such as void formation and cracking that occur in extensive soldering processes. Figure 17: Concept of stray inductance reduction in eMPack package. Adapted from [41] and [42]. The design also incorporates the following features: (1) a ceramic substrate with DSS (Double-Side Sintering) sintered chips, (2) the absence of a rigid joint between the substrate and the cooler, resulting in a low thermal and mechanical stress on the substrate, and (3) a DPD (Direct Pressed Die) pressure system that flattens out cavities downward, ensuring low thermal resistance Rth. Figure 19: The cross section with (A) simple flip-chip technology implementing solder bumps vs (B) doubleside sintered chips employing gold-plated pin-finbased copper connection. Adapted from [44]. 5.2.2 Bonding within double-sided cooling structures A concept similar to SKiN technology has been widely adopted across various packaging designs, with a primary focus on double-sided cooling structures. These configurations are common in high-power-density automotive applications exposed to elevated tempera- Consequently, this enhanced structure facilitates an even higher current-carrying capacity. In contrast, the 13 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 impact of parasitic capacitances (between the die and baseplate), particularly those subjected to high dv/dt during switching transients, has a much more significant effect on electromagnetic interference (EMI) and switching performance compared to single-sided configurations [25], [45]. In flip-chip technology (Figure 19), where the die of the bottom MOSFET is mounted opposite to the substrate, reducing the surface with high dv/dt, alternative methods such as increasing the thickness of the DBC substrate, incorporating an additional copper layer within the DBC for shielding, and introducing low permittivity materials into the thermal stack are found to be less advantageous due to the associated increase in thermal resistance within the power modules. die and the package, and support cooling from both sides. At the package level, integration began with transitioning from discrete devices to power modules, where multiple dies are attached to the same substrate to create the desired circuit topology [49]. This shift significantly simplifies power connections and streamlines converter manufacturing. 6.1 Integration of gate driver Both the power and gate drive commutation loops significantly affect the dynamics of semiconductor switches, driving extensive efforts to minimize their loops and reduce parasitic parameters. Various methods have been proposed, including the use of new packaging techniques, the addition of Kelvin pins, and the adoption of advanced bonding technologies, as presented in Sections 4 and 5. However, these approaches have their limitations and do not always yield the desired improvements in performance. Studies highlight that while these strategies contribute to reduced parasitic effects, they cannot fully overcome the inherent challenges posed by high-speed switching and the complexity of modern semiconductor devices. 5.2.3 Kelvin-source connection Power terminals in higher current-carrying packages are typically designed in blade terminal configurations. Conversely, gate-loop terminals often maintain internal connectivity through wire bonding in many designs. Due to fabrication constraints or safety considerations, the gate drive circuitry is usually kept separate from the power modules on distinct substrate boards. Therefore, it is crucial to minimize gate loop inductance by positioning the gate driver circuitry close to the power device. In three-terminal packages, the gate-loop also includes parasitic inductance Ls, which is placed in series with the source terminal. The ultimate step in integration involves incorporating gate driver circuitry [50], [51] directly into the power module. This approach not only simplifies the signal routing for the converter but also substantially reduces stray inductances between the gate driver and the transistor. As a result, it decreases gate voltage overshoots and minimizes ringing [52]. This integration is particularly beneficial for converters using GaN devices, which have stricter gate terminal specifications. As a result, the voltage at the die level may substantially differ from the voltage measured at the terminals due to voltage drops caused by the large current flowing through the power loop [46]. To mitigate the adverse effects of Ls, especially as switching frequencies increase, it is crucial to isolate the gate-loop from the effects of the switch power-loop current. This can be accomplished by implementing a Kelvin-source connection. Given the rising switching speeds of WBG devices, this approach is becoming increasingly important, both in discrete components and in packages containing multiple dies [46]. However, in multi-die modules, the layout of the Kelvin-source connection requires careful consideration, as it significantly impacts current sharing among the dies [47], [48]. Integrated gate drive GaN products can deliver superior efficiency, increased power density, and reduced magnetic component size across various applications, such as data center power supplies and solar inverters. Specifically, the Texas Instruments’ LMG3522R030-Q1, which is automotive-qualified, can switch at 650 V with a frequency of 2.2 MHz and achieve high slew rates of up to 150 V/ns. This combination enables a significant 59 % reduction in the size of power magnetics [53]. Research demonstrates that positioning gate driver integrated circuits and their coupling capacitors on the direct-bonded copper substrate within the power module, rather than on the PCB, can achieve up to 45 % reduction in the gate driver’s thermal resistance from junction to ambient. Incorporating an auxilliary source bond wire used as a Kelvin connection for the gate circuitry allows for effectively decoupling of the gate and power loops, achieving gate-source and drain-source loop inductances of 4.6 nH and 6.3 nH, respectively [54]. 6 Comprehensive integration in power modules One of the prominent trends in power converter design over the past decade has been the increasing level of integration. At the device level, packaging has evolved to minimize stray inductance, facilitate Kelvin-source connections, enhance thermal coupling between the 14 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 switching events are significantly reduced, which in turn decreases the required voltage margin. Integrating an inductor also proves advantageous [58]. As illustrated in Figure 21, this integration offers several benefits. When placed on top of the power stage, the integrated solution has a smaller footprint. It also reduces the capacitive coupling at the switching node, leading to lower electromagnetic interference (EMI). Additionally, if the inductor losses are minimal, it aids in extracting heat from the top side of the power stage. Figure 20: Packaging technologies. (A) presents a conventional power module structure. (B) demonstrates a PCB/DBC hybrid power module structure. Adapted from [55]. Figure 21: Integration of inductor with the power module. Adapted from [58] and [59]. Another option is integrating all components of the switching device into a multilayer PCB, which further optimizes performance by embedding the semiconductor die directly into the PCB, with copper planes connecting peripheral units. This design eliminates bond wires, reducing power loop parasitic inductance to 2.8 nH [55]. However, the use of FR4 PCB material increases thermal impedance, potentially impacting thermal and electrostatic performance. This shortcoming can be addressed with a PCB/DBC hybrid power module structure (Figure 20), where a ceramic substrate is attached to the multilayer PCB with integrated semiconductor die [55]. Gate loop inductance is particularly critical in parallel-connected high-current WBG semiconductors, where synchronized gate voltages are essential to avoid timing mismatches. This synchronization requires low-inductance switching cell designs and equal gate loop parasitics, achieved through PCB layouts with length-matched signal traces connecting drivers to power switches [56]. 6.3 Integration of sensors The integration of sensors into power modules began with simple inclusion of NTC thermistors. This approach allows for more dynamic measurement of substrate temperature, enabling the converter to operate with a reduced temperature margin. To enhance thermal coupling between the transistor and the temperature sensor, some manufacturers prefer to use a diode as a temperature sensor, which can be mounted on the same die as the power transistor [60]. Another commonly integrated sensor, especially in modules with gate drivers, is the current sensor [61], primarily used for overcurrent protection. Utilizing current mirroring based on sense MOSFETs, as suggested in [61], offers advantages by significantly reducing temperature dependence compared to the RDS,on method. 6.2 Integration of passive devices 6.4 Complete control system integration The increased switching speeds associated with WBG devices make the effects of stray inductances and capacitances more pronounced. To address these issues, some power modules incorporate decoupling capacitors [57]. By positioning the capacitor closer to the transistor leg (Figure 13), voltage oscillations during The complete integration of power devices, gate drivers, current and temperature sensors, and all control logic, including a processing unit (MCU), represents the culmination of integration efforts. Initial attempts, such as IR’s PIIPM devices from two decades ago (Figure 22), succeeded in miniaturizing the control electronics to within the power module. However, rapid advance15 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 ments in silicon technology quickly rendered these devices obsolete. the failure rates at the die level, which are further exacerbated by packaging constraints [63]. At the package level, a key focus is on thermo-mechanical reliability, which is particularly well-addressed by double-sided structures due to the robust interconnections between individual dies and their substrates. Further improvements in reliability can be achieved by integrating the semiconductor die and cooling body into a single component, typically featuring liquid cooling (Figure 24). An advanced example of this integration is seen in embedded designs, where these components are integrated into the printed circuit board [64]. Figure 22: PIIPM power module with corresponding signal electronics including current/voltage sensing, gate drivers and processing unit Recent examples include the “System in a Package” STSPIN32F0, which integrates an MCU along with complete sensing and gate-driving circuitry into a single chip (Figure 23) [62]. DRV10983 takes this a step further by also incorporating a low-power output stage, thereby delivering a complete power system within a single package. Figure 24: Schematic of power modules (upper section) with both closed (top) and open (bottom) liquid heat sink solutions. Photograph of the wave technology applied to the power module baseplate, along with the open heat sink (lower section) [65]. 7 Advanced techniques in power electronics design optimization Figure 23: System in a package including processing unit, sensing and gate drivers [62]. The approach to designing power electronics systems has evolved significantly in recent decades. Traditional methods, based on experience and analytical techniques, are now heavily supplemented by multi-domain simulations, including electromagnetic, thermal, and mechanical analyses, and lately also by machine learning and artificial intelligence concepts. The focus has shifted towards accelerating prototyping and optimizing parameters such as efficiency, compactness, and EMC/EMI characteristics. The rise of WBG semiconductors, with their higher switching frequencies and dynamics, has made parasitic parameters of PCBs, pow- Although this level of integration is currently limited to Si-based designs, it is anticipated that similar solutions will soon be available for GaN and SiC power devices. 6.5 Integration of cooling body Even though the theoretical operating temperature for WBG devices can reach up to 500 °C, leading manufacturers currently offer these devices with a maximum operating temperature of 175 °C. This limitation is primarily due to reliability concerns, specifically 16 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 er modules and even integrated circuits – inductances, capacitances, and resistances – critical to performance. 7.2 Analytical methods Analytical methods, though often more complex to derive, can offer speed and accuracy. Traditional inductance calculations using the Biot-Savart law may overestimate values when PCB trace dimensions are small. To address this, updated analytical methods [77] provide more accurate estimates and are validated through FEA analyses (program package Magnet) and experimental results. Simplified parasitic models are also employed to reduce the complexity of numerical simulations, streamline parameter sweeps, and improve design efficiency [73]. Accurate modeling of parasitic elements is essential for WBG modules, as small deviations can significantly affect converter operation. For instance, errors exceeding 10 % in loop inductance modeling can impact performance notably, highlighting the need for precise electromagnetic simulations [66]. Three main methods are used to estimate parasitic parameters: numerical simulations, analytical approaches, and experimental measurements. 7.3 Experimental measurements 7.1 Numerical simulations Parasitics can also be estimated through experimental measurements, either indirectly through transient signals and ringing characteristics [78], [79] or directly through impedance measurements. The latter are particularly useful for the characterization of decoupling capacitors [78], SMD resistors, and ferrite beads [79]. Numerical tools such as Ansys Q3D, which uses finite element analysis (FEA) and the Method of moments (MOM), accelerated by the Fast multipole method (FMM) help analyze parasitics and optimize designs by accounting for proximity effects and skin effects, dielectric and resistive losses, and frequency dependencies [67]. Such tools have been validated for both discrete and module-level analyses [68], [69], improving designs by reducing the inductance and optimizing current distribution. The extraction of parasitic parameters and characteristics of packaged SiC [80] and GaN [81] power transistors can also be done by measurements using the S-parameters. A similar approach using S-parameters is also useful for verifying the results of simulation models using Advanced Design Systems (ADS) software [82]. Authors in [70] demonstrate reduction of power loop inductance by 70 % by changing the design from lateral to vertical. A similar method was also presented for a 135 kW SiC-based traction inverter [71]. The authors in [72] significantly reduced the inductance by using multiple PCB layers for improved current distribution and magnetic field cancellation. 7.4 Design Optimization through Co-Simulation In addition to parasitic inductances and capacitances [83], optimizing thermal performance is a critical aspect of the design process. Tools like Ansys Icepak, combined with Ansys Q3D and Maxwell, facilitate electro-thermal co-design by balancing inductance, capacitance, and thermal management [78]. Parasitic RLC parameters estimated by simulations are often used in combination with SPICE models of devices in conjunction with other simulation packages, such as COMSOL Multiphysics to evaluate electro-thermal properties and improve designs of power modules [79]. Sun et al. emphasized the importance of evaluating parasitic inductances for estimating the oscillation challenges during the hard switching process [73], while Liu et al. show through LTSpice simulations that the common-source inductances can increase the converter losses by up to 20 % [74]. The common-source inductance is affected by several parameters (leakage inductances of the common conductive path between power and gate loop, coupling factor of power and gate loop, presence of Kelvin source connection, internal bond structure, number of bond wires, gate loop area, submount size), which have different effects as shown by the analysis using the CST studio software [75]. Overall, the integration of these advanced techniques into the design process is crucial for maximizing the performance and reliability of modern WBG-based power electronics systems. 7.5 Machine learning and artificial intelligence concepts Machine learning and artificial intelligence concepts are rapidly transforming the field of power electronics and semiconductors by addressing challenges across design, control, and maintenance life-cycle phases [84]. These technologies excel in tasks, such as optimization, classification, regression, and data structure explora- As operating frequencies approach 1 MHz, the design of passive components becomes increasingly complex. Novel high-frequency GaN converters sometimes employ PCB inductors, where FEMM simulations are essential for accurate design and evaluation of parasitic elements [76]. 17 H. Lavrič et al.; Informacije Midem, Vol. 55, No. 1(2025), 3 – 23 tion. For instance, ML facilitates the discovery of novel semiconductor materials through classification and predicts their physical, electrical, magnetic, or chemical properties [85]. Such materials are essential for the design of integrated circuits and power module packages, where advanced ML methods like deep learning and reinforcement learning are widely implemented in electronic design automation (EDA) for tasks such as placement, routing, and performance prediction [86]. Furthermore, AI enables reliability-focused design by mitigating the computational burden of finite element method simulations through dataset-driven predictions applied across functional design, reliability design, manufacturing, and testing phases [87]. necessitating innovations in die attach methods, bonding techniques, and module integration. High switching speeds necessitate a substantial reduction in parasitic parameters. This process is supported by accurate modeling and advanced design optimization techniques, such as multi-model co-simulation, novel analytical methods, and extensive experimental measurements. Moreover, machine learning and artificial intelligence concepts are playing an increasingly important role in supporting these design and optimization processes in power electronics, leading to reducing design times and improved performance. As computational power continues to grow, the impact of ML and AI in these areas is expected to expand further. AI and ML further enhance the design and prognostics of power modules, particularly in thermal management and material selection [88], [89], [90]. Combined approaches using genetic algorithms and FEM simulations have demonstrated significant optimizations, including a 27 % reduction in heat sink volume and a 6 °C decrease in junction temperature [91]. Similarly, multi-objective genetic algorithms have been applied to optimize Al ribbon loop dimensions, minimizing plastic strain and temperature [88]. ML also improves manufacturing processes by increasing wafer yield, optimizing die pickup procedures [85], [88], [92], and enabling fault diagnosis for wire-bonding equipment [93]. Conventional power converter design, often iterative and time-consuming, is now accelerated using genetic algorithms and artificial neural networks for multi-objective circuit parameter design with reduced computational time, as demonstrated in a 1 kW GaN inverter prototype [94], [95]. AIdriven digital twin modeling enables the prediction of transient behaviours and failure mechanisms, such as bond wire lift-off and junction temperature estimation in wide bandgap semiconductors [96], [97]. A new class of intelligent systems, called cognitive power electronics [98], integrates AI with embedded sensors and real-time analytics, demonstrating the transformative potential of these technologies. As computational capabilities continue to advance, ML and AI are expected to play an increasingly critical role in shaping the future of power electronics design and optimization. In summary, leveraging these innovations and design techniques will drive the next generation of power electronics, improving efficiency, compactness, and reliability in a wide range of applications. 9 Acknowledgments The authors gratefully acknowledge the financial support of the Slovenian Ministry of Higher Education, Science, and Innovation, as well as the Slovenian Research and Innovation Agency (Grant: P2-0258). 10 Conflict of interest The authors declare no conflict of interest. 11 Author contributions Henrik Lavrič: Investigation, writing. Peter Zajec: Conceptualization, writing. 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This is an open access article distributed under the Creative Commons Attribution (CC BY) License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 25. 09. 2024 Accepted: 04. 12. 2024 23 24 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.102 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 25 – 35 CMOS Low-Power, Fully-Programmable Gaussian/Trapezoidal Fuzzy Membership Function Generator Sarkis Azizian1, Amir Fathi2, Sarhad Azizian3, Behbood Mashoufi2, Mehdi Sefidgar Dilmaghani4 Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran Microelectronic Research Laboratory of Urmia University, Urmia, Iran 3 Department of Biosystem Engineering, Urmia University, Urmia, Iran 4 Department of Electronic Engineering, College of Science and Engineering, University of Galway, Galway, Ireland 1 2 Abstract: Design of a novel flexible structure for fuzzy Membership Function Generator (MFG) has been discussed in this article. The main advantage of the proposed circuits is the capability for the production of all Trapezoidal, Gaussian, S and Z shapes, simultaneously. This objective has been achieved at the first step by means of two interconnected differential pairs which generate Gaussian, S and Z shapes. Thereafter, with the help of an improved Min/Max circuit, the Trapezoidal shape with sharp edges has been constructed. The circuits are designed in a way to produce all shapes with the feature of full programmability for slope, core, and height. These features, along with small active area and low power consumption, qualify this work to be repeatedly used in Fuzzy Logic Controllers (FLCs). Post-layout simulation results for TSMC 0.18µm CMOS technology confirm the correct behavior of the designed circuits. Based on the results, the power consumption of the whole structure is 54µW from a 1.8V power supply. Keywords: Fuzzy membership function; Fuzzy logic controller; Fuzzifier; Min/Max circuits CMOS nizkoenergijski programabilni gausov/ trapezoidni fuzzy funkcijski generator Izvleček: V tem članku je obravnavana zasnova nove prilagodljive strukture za fuzzy funkcijski generator (MFG). Glavna prednost predlaganih vezij je možnost hkratne izdelave vseh trapeznih, Gaussovih, S in Z oblik. Cilj je bil v prvi fazi dosežen z dvema povezanima diferencialnima paroma, ki ustvarjata Gaussovo, S in Z obliko. Nato je bila s pomočjo izboljšanega vezja Min/Max izdelana trapezoidna oblika z ostrimi robovi. Vezja so zasnovana tako, da omogočajo izdelavo vseh oblik z možnostjo popolnega programiranja naklona, jedra in višine. Te lastnosti, skupaj z majhno aktivno površino in majhno porabo energije, omogočajo, da se to delo uporabi v fuzzy logičnih krmilnikih (FLC). Rezultati simulacije po izdelavi za tehnologijo TSMC 0,18 µm CMOS potrjujejo pravilno obnašanje zasnovanih vezij. Na podlagi rezultatov je poraba energije celotne strukture 54 µW pri napajalni napetosti 1,8V. Ključne besede: Fuzzy funkcija; Krmilnik Fuzzy logike; Min/Max tokokrogi * Corresponding Author’s e-mail: a.fathi@urmia.ac.ir 1 Introduction capture the natural signals more suitably than their digital counterparts. Also, the digital circuits mostly need extra blocks for the digitization of those obtained signals. Hence, the analog systems are economically efficient due to their lower power consumption [1]. Moreover, based on the information obtained from the Analog nature of the environment around us necessitates the operation of human-made signal processing systems in the analog domain. The main reason for this purpose lies behind the fact that analog systems can How to cite: S. Azizian et al., “CMOS Low-Power, Fully-Programmable Gaussian/Trapezoidal Fuzzy Membership Function Generator", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 1(2025), pp. 25–35 25 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 literature, hardware realization for most of the fuzzy systems and neural networks has been done in the analog domain. Membership Function Generator (MFG) circuits. The main objective of the fuzzification process is to transmute the analog input into a set of fuzzy variables. For higher accuracy, more fuzzy variables must be chosen where the outputs should be produced simultaneously [6, 12]. On the other hand, there has been intense competition between fuzzy systems and neural networks over recent years for the emulation of human brain behavior. Started by McCulloch and Pitts in 1943 for the realization of the first neuron model [2, 3], the historical background of neural systems seems to be older than Fuzzy Logic Controllers (FLCs). But since the practical realization of fuzzy logic systems at the end of the 1970s, in less than half a century, they have justified their capabilities for industrial use. Their applications cover a wide range of commercial consumer products such as cameras, rice-cookers, washing machines, and so forth [4]. Because of their continuous nature and lower costs, analog Membership Function Circuits (MFCs) have drawn the attention of circuit designers over previous years. Many structures have been reported in the literature for hardware implementation of fuzzifiers in the analog domain. Depending on the purpose of the application, each structure contains different characteristics such as single or multi-variable outputs, specific waveforms, etc. In order to save power, most of the reported works can only generate one fuzzy variable at their outputs [13, 14, 15, 16, 17, 18]. The characteristic feature of these works is the function waveforms with smooth edges making them unsuitable for high-precision applications. One of the famous low-power exceptions has been introduced in [1], which has the capability of producing six fuzzy variables simultaneously. The drawback of such structure is the low resolution of the output waveforms as the drain-source voltages of the transistors are not equal in transients. Moreover, the circuit doesn’t have the capability of programmability, which limits its usage in high-performance FLCs. The critical fact behind the population of fuzzy systems comes from the human brain translation ability for incorrect and imperfect sensory information which comes from perceptive organs [5]. It is because that the fuzzy set theory prepares a systematic computation which deals with such details linguistically. Moreover, it carries out the numerical calculations through linguistic labels arranged by membership functions [6]. Although Lukasiewicz and Tarski perused fuzzy logic as multi-valued logic in the 1920s [7], it was Lotfi A. Zadeh who announced his fuzzy set theory in 1965. It was the starting point for fuzzy systems [8]. Piece-Wise Linear (PWL) membership functions are the waveforms with sharp edges which are used for special purpose applications. Despite higher precision, more power dissipation is expected for their generating circuits. Those circuits are designed mostly in currentmode because of the simplicity for current summation or subtraction at the connecting nodes [19, 20, 21, 22, 23]. The reported works in this criterion only produce the triangular or trapezoidal functions. The thorough analysis depicts that the problems concerning power and active area consumption have rarely been considered in most of these architectures. In contrast to the standard binary sets where the variables usually pick up true or false values, in fuzzy sets, they can obtain a truth value revolving in the interval of 0 and 1 [9]. Meanwhile, for the case of utilizing linguistic variables, the degrees can be modeled by specific functions [10]. By considering these points, the general concept of an FLC will be brought up using the structure of Figure 1. As it is evident, each fuzzy system is composed of three main stages: 1) Fuzzification (membership function generation) 2) Fuzzy inference or fuzzy rule evaluation 3) Defuzzification One of the notable works has been presented in [21] in which by means of a simple mathematical idea an MFC has been designed using Min/Max operations. Since the circuit has been implemented in current-mode, it contains two advantages. Providing the Max and Min operations is the first privilege of this structure, while the flexibility to be configured as an MFG constitutes its second benefit. This idea can further be expanded to obtain multi-waveform membership functions. Figure 1: Structure of a Fuzzy Logic Model. As a conclusion, the main emphasis in this paper is to achieve the unique ability to generate all functional waveforms in a single scheme. Along with this, the programmability feature, along with low power and active area consumption, must be taken into account. At the starting point, the fuzzification interface maps the inputs so that they can be interpreted and evaluated by the rules of the inference engine [11]. In hardware realization, the fuzzification is done by means of 26 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 For multi-valued or continuous fuzzy sets the parametric representation is usually suitable, and to do this, the modification of some parameters is often enough for the adjustment of the membership function. On the other hand, PWL membership functions are the most employed ones because of their computational efficiency. Trapezoidal and triangular functions constitute the central part of PWL waveforms and are distinguished by four and three parameters, respectively [5, 19, 23]. This work introduces a novel Min/Max architecture based MFG, which is implemented in current-mode using TSMC 0.18µm CMOS technology. Input voltages are used to control the slope, height, and location of waveforms. The main idea is based on the expansion of the scheme introduced in [21]. Figure 2 illustrates the initial concept, which is adapted to the differential pair based MFG so that all of the waveforms can be produced in one single architecture. The normalized Gaussian function (which is the difference of two sigmoid waves), and the generalized bell function are also used for modeling of fuzzy sets in some special cases. In such functions, continuously differentiable curves with smooth transitions are needed where those features cannot be fulfilled by trapezoids [1, 16, 17, 26]. In General, for hardware realization of a fuzzy membership function, the following four features must be remarked [7]: a) The height, as the highest membership value achieved by any element in the set. b) The support, as the crisp set including all the elements of X with non-zero membership values. c) The core, as the crisp set consisting of all the elements of X with the membership values of one. d) The boundary, as the crisp set having all the elements of X with the membership values of 0  A  x  1 . Figure 2: Structure of a Fuzzy Logic Model. The designed circuit is composed of two parts. The first lock which is composed of a differential pair configuration generates the Gaussian, S and Z shapes simultaneously. Then, with the help of the optimized Min/ Max circuit, which was initially reported in [24], the Trapezoidal/Triangular shapes with sharpened edges have been produced. It must be mentioned that the optimized Min/Max circuit can calculate the minimum of three input signals. The main emphasis in this work is to design a flexible architecture for achieving all of the mentioned waveforms simultaneously. Therefore, the initial idea comes from the generation of S, Z, and Gaussian functions in the first step. After that, with the help of an auxiliary circuit, the trapezoidal waves will be produced. In Section 2, the main idea for the fuzzifier circuit is discussed, and the architecture has been demonstrated with a complete analysis. Section 3 is about the optimized Min/Max structure and its usage for customization of the output waveforms. Section 4 contains the simulation results and comparison of the designed work with previous ones. Finally, the conclusions have been summarized in Section 5. Therefore, the first part of the MFC will produce Gaussian, S, and Z shapes, where the initial idea has been illustrated in Figure 3. This circuit is composed of two differential pairs: the first pair consisting of M1 and M2 transistors, and the second pair in the right side which is constructed of M3 and M4 transistors. These pairs generate both S and Z shapes at their output loads. 2 Materials and methods Fuzzification is well described by the procedure which generates a fuzzy value from an analog value of the real world. For this purpose, different classes of fuzzifiers can be employed [25]. The most important groups, utilized for the fuzzification process are: 1) Single-tone fuzzifiers 2) Gaussian fuzzifiers 3) Trapezoidal/Triangular fuzzifiers The input voltage Vin is applied to M1 and M3 transistors at the same time. These transistors are initially in the cut-off region. Along with the increment of Vin, the gate-source voltages of M1 and M3 will grow, and they become ON. Therefore, they will produce S shape waveform at their drains while M2 and M4 transistors have the responsibility of generating Z shape. It must be considered that the base set determines the class of representation for the membership function. 27 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 Table 1: Different values of three fuzzy variables. To generate the Gaussian shape waveform, the currents of M2 and M3 are summed together, and the result will be subtracted from a normalized 10μA current. The current is specified as IVbb in Figure 3. These three currents will constitute three fuzzy variables.   (1)   (2) IM 3  1 I B  V2 2kI ss  k 2V22 2 Vin < Vb1 − 2∆V IB 0 0 Vin = Vb1 Vin = (Vb1 + Vb2)/2) Vin = b2 IB/2 0 0 IB/2 IB IB/2 0 0 IB/2 if I M 1,4  I M 6,9 I M 1,4  I M 6,9 if (4) The current waveforms of M5 and M10 are S and Z shape, respectively which are expected to have sharpened edges. These currents will be transferred to the Min/ Max circuit to produce the Trapezoidal/Triangular shape. Practically, the architecture of Figure 3 has two major problems: 1) The currents of M2 and M3 cannot be replicated easily as their loads are not directly connected to Vdd. 2) The currents of M5 and 10 M10 transistors are not sharp enough to generate a Trapezoid waveform with sharp edges because of the poor linear operating range of differential pairs. where k  1  Cox W , V1  Vin  Vb1 , and V2  Vin  Vb 2 . 2 L Moreover, IB is the bias current which has a normalized value of 10μA. Table 1 illustrates the values for IM2, IM3, and IVbb for different intervals of the input voltage. It is assumed that Vb1< Vb2. In order to solve these problems, the configuration of Figure 4 has been proposed and used as the final version of Gaussian, S, and Z shape MFG. M7a and M8a transistors are used to replicate currents of M2 and M3, respectively. For equalizing all of the currents, the bias current must be doubled for upside M3c transistor. So IVbb will be doubled, too and it must be considered for current mirroring. The subtraction of Vb1 from Vb2 determines the width for the Gaussian shape. To explain the slope changes, let’s consider the current of MOS transistor in the saturation region [27]: Id  IM3  I M 1,4  I M 6,9 I M 5,10    0 Equations (1) and (2) illustrate the currents of M2 and M3, respectively [27]: 1 I B  V1 2kI ss  k 2V12 2 IVbb M6 and M9 are current sources with constant values. Their role is to sharpen the lower part of the current for M5 and M10, which is illustrated in (4): Figure 3: Initial idea for realization of the MFG. IM 2  IM2 2 1 W  Cox  Vgs  Vth  (3) 2 L In (3), Vgs and Vth are the gate-source and the threshold voltage of the MOS transistor, respectively. μ and C0x demonstrate the process coefficients, while W and L represent the dimensions of the MOS transistor. In order to change the slop, the sizes of M1, M2, M3 and M4 must be changed to achieve the desired values. It can be done by parallel transistors of differential pair inputs in Figure 3. Figure 4: The proposed MFG. The variable resistance Rt is used to increase the linearity range of differential pairs. It is implemented by means of a single transistor biased in the triode region. The current of the transistor in the triode region can be expressed as follows [27]: 28 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 I d   Cox W 1  Vgs  Vth Vds  Vds 2    L 2  able. With a two input Min/Max circuit, at most only three of four features would be controlled. For achieving full programmability feature, a three-input Min/ Max circuit is needed. (5) Vgs, Vth and Vds are the gate-source, threshold, and drainsource voltages of the MOS transistor, respectively. μ and C0x represent the process coefficients while W and L denote the dimensions of the MOS transistor. If Vds  Vgs  Vth, the resistance can be calculated as follows: R 3 The optimized min/max circuit In hardware design, the most popular fuzzy logic functions which implement logical ‘AND’ and ‘OR’ functions, are MIN and MAX operators, respectively. Therefore, they will play an essential role in the fuzzy inference engine implementation, and most of the reported works in the literature have put their basis on them. Vds L  (6) I d  CoxW Vgs  Vth  (a) The resistance sharpens the edges of output currents IM5 and IM10, which will be transferred to the Min/Max circuit. (a) (b) (b) Figure 5: Trapezoidal membership function (a) general waveform (b) mathematical expressions. As mentioned before, the circuit of Figure 4 can only produce Gaussian, S, and Z shapes. By means of the current replicas (which perform the operations of summation and subtraction), the Trapezoid shape can be generated. However, the feature of full programmability along with good accuracy can be achieved using an additional circuit. Figure 5 demonstrates the general figure of a Trapezoidal membership function where in Figure 5(a), its four main characteristics are emphasized. Moreover, the mathematical expressions of this function are illustrated in Figure 5(b). For b = c, the trapezoidal shape will migrate to a triangular membership function. (c) Figure 6: LTA network design by means of WTA network (a) general concept (b) Initial idea of Min circuit, (c) Structure of Min circuit proposed in [24]. In order to construct a programmable circuit, the height, core, boundary, and support must be adjust29 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 One of the notable advantages of current-mode MIN and MAX circuits is that they do not necessarily need resistors in their architectures. On the other hand, the summation and subtraction of currents can simply be achieved just by wire connections. This leads to discriminating and straightforward configurations, which represent high speed and great functional density [24]. calculated. The optimized circuit with three inputs is shown in Figure 7. The circuit is composed of two cascaded Min circuits of Figure 6(c). M11 and M12 are the input transistors. IM5 and IM10 are applied from the circuit of Figure 4 to M11 and M12. In order to miniaturize the configuration and avoid more wiring, the second Min part is designed as the complement of the first part. The first part is the same as the circuit of Figure 6(c). At the second part, PMOS transistors are employed as the active loads (M19, M20, M21 and M22). M25 and M26 are the input transistors of this part. M23 and M24 have the same role as their counterparts (M13 and M14) in the first part of the Min circuit. Because single fan-out is one of the drawbacks of current-mode based MIN/MAX circuits, then the current repeatability is considered as of prime importance for these structures. Also, the distribution of signals necessitates the utilization of multiple-output current mirrors. To design the MIN/MAX structure, current-mode is chosen because of the mentioned benefits, while the disadvantages are also taken into account. If IM25 > IM26, then the gate voltage of M24 grows high and the gate voltage of M23 drops down. The extra current IM25 – IM26 passes through M24 to Vdd. The result, which is the reflected current in output, gives the minimum current (IM26). After Lazzaro’s work which was a novel report on Winner-Takes-All (WTA) structures (released in 1988) [28], a lot of WTA and closely related Loser-Takes-All (LTA) circuits have been proposed to realize Min/Max circuits [29, 30] (Figure 6). In some of the reported structures, the LTA function is obtained by means of WTA function. This fact is illustrated in Figure 6(a) whereby subtraction of the input values from a fixed reference current, the LTA function has been obtained. In order to explain the procedure, one can say that at the first step, one circuit performs the subtraction from a fixed current. Then, the maximum current selector behaves as the minimum current selector function. By considering the structure of Figure 6(b) as the initial idea, a newly designed structure has been reported in [24] (Figure 6(c)). The current of M25 can also represent the Trapezoidal/ Triangular waveform. But it only controls core, boundary, and support of the membership function. Transistor M26, which is the third input of Min circuit, is biased with a constant current to control the height of the Trapezoid function. Its maximum value which represents the fuzzy value of one is 10μA. The final waveform which has been obtained from cascode transistors (M27 and M28) is the output of the fuzzifier to produce the Trapezoidal membership function. It must be mentioned that in the circuit of Figure 7 if the location of M23 – M24 configuration is replaced with its counterpart M13 – M14 pair, the three input Max circuit can also be obtained. Wilson current mirror transistors are used to increase the output resistance. Also, the subtraction of currents at the input nodes enhances the accuracy of the output current. According to Figure 6(c), If I1 > I2, then the voltage of node A rises to a high level while the voltage of node B drops down. Therefore, the gate-source voltage of Mx1 will be increased, and this transistor will become on. On the other side, Mx2 goes to cut off region. The extra current I1 – I2 passes through Mx1 to the ground, which results in the reflected current in output as minimum current (Imin = I2). The same reason holds for I1 as the minimum current when I1 < I2. 4 Simulations and comparison The improved version in [31] has the extra feature of generating both maximum and minimum of input signals simultaneously. But the major problem associated with both of [24] and [31] is that they can only accept two signals as the inputs. As discussed in the previous section, for achieving the full control feature over four common characteristics of a Trapezoid waveform, at least the minimum of three input signals should be For the circuit of Figure 4, the simulation results of three fuzzy variables (IM2, IVbb, and IM23) constituting Z, Gaussian, and S shapes, respectively, are shown in Figure 8. The normalized 10μA current represents the fuzzy value of 1. For the overlapping areas, the summation of heights won’t pass the normalized value. 4.1 Behavioral simulation Post-Layout simulations are performed based on the TSMC 0.18µm standard process and 1.8V supply voltage by HSPICE to evaluate the correct behavior of designed fuzzifier architecture. To show programmability feature of the designed MFG, simulation results for different values of the sec30 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 ond bias voltage of differential pair Vb2 (applied to the gate of M4) are shown in Figure 9. The result indicates that the increment of Vb2 stretches the core of Gaussian shape and turns it into Bell shape membership function, whilst the position of S shape will be relocated, too. tute the inputs of Min circuit. Figure 11 shows the waveforms for these currents. As illustrated in Figure 2, these waveforms are fed to the Min/Max circuit to produce the trapezoidal output with sharp edges. Figure 7: The optimized Min circuit. Figure 10: Slope changes of the proposed MFG for all three shapes. Figure 8: Simulation results for the architecture of Figure 4. Figure 11: Waveforms of IM5 and IM10. (a) Figure 9: Core changes in the proposed MFG. (b) In order to investigate effect of input transistors dimensional variations on the slope changes of S, Z and Bell shapes, simulations have been done for three different W values of L . The result which is illustrated in Figure 10 depicts that along with core and support changes, the slope can be regulated, too. I In order to adjust the height, the four bias currents ( B ) 2 can be modified. As discussed in sections 2 and 3, IM5 and IM10 are the outputs of the first part, which consti- Figure 12: Simulation results for optimized Min Circuit (a) Trapezoidal shape (b) Triangular shape. 31 S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 Also, Figure 12 shows the output of Min circuit, which produces the desired shapes. In Figure 12(a), the Trapezoidal waveform is illustrated, whilst by some modifications in bias voltages, the Triangular membership function can be achieved easily (Figure 12(b)). and Min/Max circuits together. Finally, Table 2 shows a comparison of this work with previous designs. As the comparison results illustrate, the power consumption of the proposed architecture is less than the reported works. Moreover, the transistor count with the consideration of the fact the designed architecture produces all four classes of waveforms needed for fuzzy inference engine remains in a reasonable range. In Figure 13, the programmability feature of Trapezoidal shape has been shown according to changes of Vb1 and Rt. The increment of Vb1 shifts the left side of the waveform to the higher voltages, while the changes of Rt adjusts the slope. It must be noted that only [1] and [15] have measurement results, and the other works have relied on simulation results. For the architecture of [18], the feature of full programmability has not been mentioned as the Trapezoidal shape has smooth edges for this work. As the simulation results depict, full programmability of the designed structure (either for Gaussian and Trapezoid shapes) has been achieved successfully. This is a unique feature which is not reported in previous works. Figure 14: Layout of the proposed work. 4.2 Monte carlo simulation Figure 13: Simulation results for programmability of optimized Min Circuit considering Triangular shape. At the final stage of the design performance evaluation, the Monte Carlo simulation results are provided to show the effect of process variations on the proposed structure. To achieve this, random values with Gaussian distribution were assigned to the device parameters The layout of the proposed work is illustrated in Figure 14, which consumes a small area of 500μm2 on-chip. In order to minimize the active area consumption, we have merged the transistors of membership function Table 2: Comparison of this work with previous designs. Work Technology (µm) Supply (V) S and Z Waves Gaussian Wave Trapezoid Wave Slope Programmability Height Programmability Core Programmability Transistor Count Power (µW) Input signal Output Signal Implementation [1] 2 10 √ √ × × [15] 0.5 3 × × √ √ [16] 0.35 3.3 √ √ × √ [17] 0.35 3.3 × √ × √ [18] 0.18 1.8 √ √ × √ [21] 0.35 3.3 × × √ √ [22] 0.35 3.3 × × √ √ [23] 0.5 1.5 × × √ √ This Work 0.18 1.8 √ √ √ √ × √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 17 500 Voltage Current Fab. 28 43 23 16 48 24 61 300 260 105 108 -426 200 Voltage Voltage Voltage V/I Current Current Current Current Current Current Current Current Current Current Fab. Sim. Sim. Sim. Sim. Sim. Sim. 32 33 54 Voltage Current Sim. S. Azizian et al.; Informacije Midem, Vol. 55, No. 1(2025), 25 – 35 such as threshold voltage and size of transistors for each sample of Monte Carlo simulation. Then by running a complete simulation, a series of measurement results have been obtained. The designed circuit has been examined for 50 iterations, and the results for Gaussian and Triangular simulations are shown in Figure 15. In Figure 15(a) the results Gaussian waveform have been demonstrated while Figure 15 (b) illustrates the results for Trapezoidal shape. As the results indicate, the negative effect of process variations such as device mismatches and threshold voltage do not significantly affect the performance of the circuit. Figure 16: Temperature simulation results for Gaussian waveform. Along with Monte Carlo analysis, the effect of temperature variations has also been considered on the current variations of the MOS transistors for performance evaluation of the designed circuits. As Figure 16 illustrates, temperature changes from 0 to 60oC do not cause any concern for the Gaussian waveform. It is because that in the configuration of Figure 4, the variable resistance behaves like a local feedback configuration and compensates the current changes related to temperature variations. the Min circuit of Figure 7 (driven from voltage source). Therefore, with the consideration of 1.8V as the supply voltage, IF = 10μA, and IM = 20μA in the design process, the total power consumption will be equal to 54µW while the HSPICE simulation results have confirmed this value. For the total power consumption of the designed architecture, one can say that the power dissipation can be calculated using the following relation: In this paper, a novel architecture for a fully programmable MFC is presented which produces Gaussian shape along with the Trapezoidal waveform. The improved Min/Max circuit enables us to obtain full programmability feature for Trapezoidal function, too. None of the previously published works could get both of the mentioned waveforms in a single scheme, and this is the main advantage of the designed architecture. Low power consumption and small active area are the other advantages of the designed architecture. These features, along with careful design considerations and reasonable transistor count, qualify the proposed work to be widely used in high-speed Fuzzy Logic Controllers. 5 Conclusions Ptotal  Vdd   I F  I M  (7) (a) Post-Layout simulation results confirm the correct behavior of the designed structure while the Monte Carlo and temperature simulation results demonstrate the low sensitivity feature of this work for process variations. The power consumption of the whole structure is 54µW from a 1.8V power supply using TSMC 0.18µm CMOS technology. (b) 6 Conflict of Interest Figure 15: Monte Carlo simulation results (a) for Gaussian waveform (b) for Triangular shape. The authors declare no conflict of interest. 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Arrived: 12.12. 2023 Accepted: 24. 05. 2024 35 36 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.103 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 37 – 45 Efficient Resource Allocation for Ultra Reliable Low Latency Communication Delay Minimization in Fifth Generation Networks Parameswaran Ramesh1,2, Bhuvaneswari Mohan1,2, Hariharan Rajamanickam1, Rishi Vharsun Jaikumar1, Arun Lakshmanasamy1 Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai, India 2 Centre for Internet of Things, Madras Institute of Technology, Anna University, Chennai, India 1 Abstract: In Modern world, Fifth Generation (5G) technology is ubiquitous, so it is necessary to meet all of its service requirements. Hence, resource allocation for every service is very important. This research addresses the problem of resource allocation for both Enhanced Mobile Broadband (eMBB) and Ultra Reliable Low Latency Communication (URLLC) users. The work comprises both static and dynamic resource allocation for eMBB and URLLC users. This research aims to minimize latency for URLLC users by taking into account the time and energy constraints of both eMBB and URLLC in static resource allocation, formulating these constraints as a convex optimisation problem. The results show that the static resource allocation strategy performs better than the fixed bandwidth and Central Processing Unit (CPU) cycle schemes. However, the use of static resource allocation becomes inefficient as the number of users increases. We propose a dynamic resource allocation strategy to address this issue, which uses online conformal prediction to schedule URLLC traffic on top of eMBB. The dynamic resource allocation strategy outperforms all previous resource allocation methods, ensuring 67% eMBB efficiency and 1 millisecond latency for URLLC users. Keywords: 5G; eMBB; URLLC; Conformal Prediction; Resource Allocation Učinkovita dodelitev virov za izjemno zanesljivo komunikacijo z nizkimi zakasnitvami za zmanjšanje zakasnitev v omrežjih pete generacije Izvleček: V sodobnem svetu je tehnologija pete generacije (5G) prisotna povsod, zato je treba izpolniti vse zahteve glede storitev. Zelo pomembno je dodeljevanje virov za vsako storitev. Raziskava obravnava problem dodeljevanja virov za uporabnike izboljšanega mobilnega širokopasovnega omrežja (eMBB) in ultra zanesljivega komuniciranja z nizko zakasnitvijo (URLLC). Delo vključuje statično in dinamično dodeljevanje virov za uporabnike eMBB in URLLC. Cilj te raziskave je čim bolj zmanjšati zakasnitve za uporabnike URLLC z upoštevanjem časovnih in energetskih omejitev eMBB in URLLC pri statičnem dodeljevanju virov, pri čemer se te omejitve oblikujejo kot konveksni optimizacijski problem. Rezultati kažejo, da je strategija statičnega dodeljevanja virov boljša kot sheme s fiksno pasovno širino in cikli centralne procesne enote (CPU). Vendar, ko se poveča število uporabnikov, postane uporaba statičnega dodeljevanja virov neučinkovita. Predlagamo dinamično strategijo dodeljevanja virov za reševanje tega vprašanja, ki uporablja spletno konformno napovedovanje za načrtovanje prometa URLLC na vrhu eMBB. Dinamična strategija dodeljevanja virov je boljša od vseh prejšnjih metod dodeljevanja virov in zagotavlja 67-odstotno učinkovitost eMBB ter milisekundno zakasnitev za uporabnike URLLC. Ključne besede: 5G; eMBB; URLLC; konformno napovedovanje; dodeljevanje virov * Corresponding Author’s e-mail: parameswaran0789@gmail.com How to cite: P. Ramesh et al., “Efficient Resource Allocation for Ultra Reliable Low Latency Communication Delay Minimization in Fifth Generation Networks", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 1(2025), pp. 37–45 37 P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 1 Introduction describes the purpose of the literature survey of various research perspectives in relation to the research. Section III describes the proposed methodology and scenario for the research. Section IV presents the results and offers insights gleaned from them. Finally, Section V concludes with future work on the research. The need for high-speed internet in the modern world increases rapidly as automotive industries, augmented reality, and Internet of Things (IoT) based automation provide real-time data for processing, and the world is moving towards a greener future. Therefore, we need to reduce the energy consumption of cyber physical devices and base stations. The above requirements are satisfied by the Fifth Generation (5G) [1]. It offers a 20-G bit/s data rate, which is 20 times faster than Fourth Generation (4G). It can offer an ultra-low latency of 1 ms [2]. It has massive capacity so that it can connect billions of devices, enabling smart cities, connected homes, and the revolution in automobiles through vehicle-to-vehicle (V2V) communication [3]. It offers three services, namely massive machine-type communication (mMTC), enhanced mobile broadband (eMBB), and ultra-reliable low-latency communication (URLLC) [4]. URLLC devices require low latency (<1 ms), high reliability (99%), and moderate data rates. eMBB devices require ultra-high data rates, low energy, and high capacity. mMTC requires massive connectivity, extended battery life, and low data rates. The eMBB and URLLC are critical for day-to-day applications. Hence, this research focuses on the requirements of eMBB and URLLC. 2 Literature survey In [5], the authors proposed a downlink scheduler to regulate URLLC traffic and eMBB traffic using superposition techniques that share resources related to frequency and power. They made an optimization problem to make sure that the rate loss for eMBB users and the segmentation loss of URLLC packets were kept to a minimum while still meeting their QoS requirements. The considered problem is solved by decomposing into two sub-problems: one for finding the optimal resource and power allocation for each eMBB-URLLC pair, and another for finding an optimal pairing policy that uses a greedy algorithm. In [6], the authors developed a mechanism to maximize the efficiency of eMBB User Equipment (UE) and address the latency specifications of URLLC users. They have developed a dynamic, programmable approach to satisfy the above requirements. When a URLLC packet arrives, the algorithm uses puncturing mechanisms to stop the ongoing eMBB traffic. Resource to the huge network traffic and computational resource requirements, resource allocation is crucial for all 5G services. The resource allocation ensures that bandwidth, power, energy, and Central Processing Unit (CPU) cycles are used optimally based on the user needs. The resource allocation strategy ensures spectral efficiency, as well as a reduction in latency and energy consumption. The author in [7] addressed the issues related to URLLC and eMBB. The authors have developed mechanisms to address energy consumption and resource allocation between eMBB and URLLC. The authors divide a major problem into several minor problems, then transform them into convex functions that run in a loop until they converge. To implement it, the authors have adapted the Block Coordinate Descent (BCD) algorithm. In current technology, 5G uses dynamic spectrum sharing to allow for flexible allocation of frequency spectrum based on real-time needs. We use spectrum management algorithms for dynamic resource allocation to prevent interference. However, this strategy lacks the URLLC reliability constraint and eMBB efficiency, which gives scope for research. In [8], the authors used particle swap optimization and graph allocation-based algorithms to minimize interference. These mechanisms did not compromise data rates or throughput. They also used the TOPSIS technique to order the user preferences. The goal of this research is to address the reliability and efficiency of URLLC and eMBB, propose a static resource allocation strategy for a limited number of users and a dynamic resource allocation strategy to efficiently use the available bandwidth, computational capacity, and power, and develop an efficient scheduler based on conformal prediction to dynamically allocate resources to both eMBB and URLLC services, satisfying their Quality of Service (QoS) requirements. In [9], authors used the concept of network slicing to allocate resources to eMBB and URLLC within a 5G Cloud Random Access Networks (CRAN). The authors solved the allocation problem using mixed-integer nonlinear programming. They defined the separation between eMBB and URLLC services. They also introduced randomness to their traffic load. The authors have considered transmitting data packets of small size to ensure the characteristics of URLLC, which are low response The structure of the paper is outlined below: Section II 38 P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 time and high reliability. Further, they have used successive convex approximation algorithms to provide solutions to the framed problem statements. cloud, analysing, evaluating, and downloading the solutions to each of the URLLC UEs; this should be executed with an acceptable level of power consumption constraint, and in the case of eMBB users, the throughput and capacity are of the utmost importance. We built a single antenna within the network setup to serve as a gateway to the edge cloud, allowing users to offload. In addition to power and latency constraints [12], computation capacity and bandwidth constraints are also considered. In [10], the authors focused on higher-order layers and provided solutions to avoid Packet Duplication (PD). The authors also presented techniques to enhance the performance of URLLC. The authors provided an optimization problem based on URLLC constraints and solved it as a heuristic function so that the asset configuration can be in terms of Modulation Coding Scheme (MCS) and Physical Resource Block (PRB) reservation over many links. The final outputs indicate that the implementation of PD in the different network scenarios provides efficient usage of radio resources. The above literature reveals that the authors scheduled the time slots for the URLLC data based on previous URLLC traffic data, resulting in a system reliability of less than 90%. The authors have also overlooked the crucial factor of high eMBB efficiency. The traffic to URLLC varies with time. This is due to the dynamic nature of URLLC devices. URLLC devices have a minimal delay tolerance, and timeouts result in the loss of some generated packets. Hence, it is necessary to design a scheduler that takes care of the delay tolerance capability of URLLC devices. In this work, we design the scheduler to guarantee a reliability of more than 90% for URLLC devices, while also ensuring eMBB efficiency through both static and dynamic scheduling. Using a conformal prediction-based scheduler, URLLC’s reliability is increasing. Figure 1: System model for static resource allocation Constraint of computation capacity, with Ci being the computation capacity allotted to ith user [13]  10 C  C (1) i 1 i and for bandwidth, consider a total of i sub-channels, where BWi is the bandwidth allotted to the ith sub-channel. I BW  BW (2) i 1 3 Proposed methodology i And for Transmission Power 0  PWi  PWmaxi  i  I (3) This section describes the suggested model flow for the static resource allocation system model. It is followed by the formulation of constraints and the dynamic resource allocation network scenario, as well as the naive scheduler and the Conformal Prediction (CP)based scheduler [11]. 3.1.1 URLLC data packets estimation In this research, we have run simulations for a total of 2000 frames, and for each frame f within that range, a total of Pf  A . URLLC data packets will be generated. The nth generated packet can be denoted as Pf  n   A slot within the frame. Basically, we implement the process based on two assumptions 3.1 System model A network setup of 10 users is considered, as well as a mobile edge computing offloading scenario is shown in the Figure 1. Two types of 5G services are considered here, namely eMBB and URLLC, and each user will fall under one of the two categories. There are two sets of users here: one is URLLC users with a total number of 5 users, and another is eMBB users with a total number of 5 users again. The primary goal of URLLC users is to achieve the lowest possible delays. The delay includes the time required for transmitting data to the edge Along with the computation capacity, bandwidth, and transmission power constraints, a total of seven constraints are formulated [14]: 39 (4) P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 (5) (6) 3.2.1 URLLC data packets estimation In this research, we have run simulations for a total of 2000 frames, and for each frame f within that range, a total of Pf  A . URLLC data packets will be generated. The nth generated packet can be denoted as Pf  n   A slot within the frame. Basically, we implement the process based on two assumptions: first, that the number of URLLC data packets generated within a single slot will not exceed one. Another thing is that the total number of data packets generated will not exceed the number of slots. We note the slots allocated for the URLLC data packets and add them to a new set defined as in the equation 8,   p f  p f 1 ,. p f  p f   A (7) (8) 3.2.2 Latency and reliability constraints associated with URLLC user Here, we express the latency as two slots, imposing a latency threshold of 1 ms. We set the threshold for reliability to be 90 percent by defining the unreliability rate alpha at 0.1. Frame f’s reliability measure can be defined as in the equation 9 [16]. Equations (4) and (5) represent delay constraints for both URLLC and eMBB users, while equations (6) and (7) represent energy constraints. For URLLC [15] users, the delay constraint is crucial, and for eMBB users, the energy constraint ensures a limit in energy consumption, and vice versa. We solve these constraints as convex optimization problems to determine the optimal delay and energy consumption for each user. 1, if d f L  Covers p f r  d f |p f    0, otherwise  (9) This is for a single frame and for the total of F frames, RU  d1: F |p1: F   3.2 Dynamic resource allocation network scenario Frame-based communication is discussed here, and each frame contains both eMBB and URLLC data packets as shown in the Figure 2. Moreover, we divide each frame into 12 slots, each lasting 0.5 ms. The scheduler at the base station generates either an eMBB or URLLC data packet for a specific slot, stores and displays this information as set A. Every time a new frame begins, the base station’s scheduler defines each slot by assigning it to one of the users, and records this information in a set D f  A . 1 F r  d f |p f F f 1  (10) 3.2.3 eMBB efficiency We can mathematically express the eMBB efficiency [17] in equation 11 as the ratio of the number of slots allocated for the eMBB users to the total number of slots within a given frame window: eMBB  d1:E   1 F A df 1 F 1     df F f 1 A FA f 1 (11) 3.3 Naive prediction based scheduler The conventional scheduler [15] is shown in the Figure 3, and its output entirely depends on the predictor that the base station has adapted. We use the Naive Scheduler to minimize the Uf of assigned slots, ensuring that the sum of possibilities qf(h) across all intervals h that are L-covered by df is no smaller than 1 – φ. To address this issue, we use a two-step heuristic approach in equation 13. Figure 2: Network scenario of dynamic resource allocation 40 P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 Figure 3: Naive prediction-based scheduler Initially, we identify the smallest set φ of slot birth patterns hf to which the predictor qf(.) assigns a probability of at least 1 – φ    qf    argmin 2s   q P f (h) ≥ 1 – φ Figure 4: CP based scheduler The equation 14 gives the CP-based traffic predictor’s stretching function. The predictor uses stretching functions and learning rates to optimize the online CP algorithm and predict URLLC traffic. (13) The scheduler first finds the subset φ(α/qf ), then identifies an assignment df that guarantees maximum reliability and eMBB efficiency.   1      (1  cos  max 0, min 1,    0.5 ) 2 3.4 CP Based scheduler (14) 4 Results and discussion A conformal-based scheduler will output prediction intervals is shown in the Figure 4. Based on the confidence value and interval obtained from the conformal prediction, it is useful for the users to understand the nature of the input given and analyse the data efficiently. The online conformal prediction works initially with a smaller number of datasets, but as time progresses, the test data, i.e., the generated URLLC packets on successful transfer, will also become the trained dataset, and the model will get stronger as the dataset increases. We use the cumulative distribution function to calculate reliability constraints. The slot allocation will be made based on reliability. We will allocate the URLLC packet with high resource requirements and high reliability first, and then schedule the subsequent packets. Gamma indicates whether the URLLC packet reached its destination. We transform the beta using the stretching function to update our online conformal prediction model using the stretching function μ. 4.1 Simulation parameters This section delves into the simulation outcomes and provides a comprehensive discussion on the implications of these results. We conducted the simulations under various sets of parameters, each tailored to explore specific aspects of the system under study. Following this, we detail the performance metrics derived from these simulations, offering a comprehensive assessment of the system’s behavior and efficacy under various conditions. Table 1 depicts the parameters for the static resource allocation. 41 P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 Table 1: Simulation parameters for static and dynamic resource allocation Parameters Bandwidth Capacity Power Spectral Density Static Resource Input Data Allocation Total CPU Cycles Parameters Maximum Power of each user Radius Number of users b_mismatch Dynamic h_case Resource b_adaptive Allocation p_plus pop Parameters p_plus hat G_num_min_pop Value 1 MHz 10 bit/s -174 dB/Hz 50 K bits 100 0.5 Watts 500 meters 10 0,1 0,1 0,1 0.16 0.16 0 Figure 6: Average latency threshold for URLLC user vs energy threshold for URLLC users As shown in Figure 7, the proposed optimization significantly outperforms the fixed bandwidth and fixed CPU frequency approaches. The proposed optimization has a 17% decrease in delay when compared to a fixed CPU frequency and an 87% decrease in delay in comparison with the fixed bandwidth scheme. 4.2 Performance Analysis The suggested optimization beats the constant CPU frequency strategy by 10% and the fixed bandwidth method by 72%, as shown in Figure 5. In order to achieve the lowest feasible latency without sacrificing time limitations for the eMBB customers, it increases CPU computation capacity and bandwidth for the URLLC users. Figure 7: Average latency threshold for URLLC user vs latency threshold for eMBB users As expected, as the number of devices increases, the delay also increases due to the increased complexity, as illustrated in Figure 8. The proposed optimization has reduced the latency by 4% compared to a fixed CPU capacity and by 45% compared to a fixed bandwidth. Figure 5: Average latency threshold for URLLC user vs energy threshold The suggested optimization outperforms the fixed bandwidth and fixed CPU frequency methods, as seen in Figure 9. It exhibits superior performance compared to the fixed allocated Multi Access Edge Computing (MEC) capacity and fixed bandwidth schemes, leading to a reduction in latency of 16% and 90%, respectively. According to Figure 6, the proposed optimization performs significantly better than the fixed bandwidth scheme (by 71%) and the fixed CPU frequency scheme (16%). By increasing CPU capacity and bandwidth, it ensures optimal latency for URLLC users while also addressing the needs of eMBB users. 42 P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 Figure 10: CP-based scheduler output 4.3 Performance metrics Figure 8: Average latency threshold for URLLC users vs. task size 4.3.1 Efficiency When the mismatch factor is zero, Figure 11 illustrates the relationship between the number of delayed slots and efficiency. It demonstrates that as the number of slots rises, the efficiency steadily rises until it reaches 0.70, at which point it stabilizes. When the mismatch factor is one, Figure 12 illustrates the relationship between the number of delayed slots and efficiency. It demonstrates that as the number of slots rises, the efficiency consistently rises until it reaches 0.75, at which point it stabilizes. Figure 9: Average latency threshold for URLLC user vs number of URLLC Users The contour plot illustrates the comparison of resource allocation between the conventional scheduler and the CP-based scheduler [18] as shown in the Figure 10. The contour plot illustrates the comparison of resource allocation between the conventional scheduler and the CP-based scheduler. The first column in the contour represents URLLC traffic generated, which has pink-coloured slots, and eMBB traffic, which has blue-coloured slots. When the predictor underestimates URLLC traffic, the second and third columns represent comparisons between conventional schedulers and CP-based schedulers. According to equation 10, the average frame success ratio for predicting URLLC traffic in the conventional scheduler in figure 2 is 83 percent, whereas it is 93 percent in the CP-based scheduler. The fourth and fifth columns are the comparisons between conventional schedulers and CP-based schedulers. When the predictor overestimates URLLC traffic, the average frame success ratio for conventional schedulers is 90 percent, and CP-based schedulers is 92 percent based on equation 10. In both cases, the CP-based scheduler achieves URLLC reliability of more than 90 percent. This makes it perfect for forecasting URLLC traffic. Figure 11: Efficiency (mismatch factor is 0) Figure 12: Efficiency (mismatch factor is 1) 43 P. Ramesh et al.; Informacije Midem, Vol. 55, No. 1(2025), 37 – 45 6 Acknowledgments 4.3.2 Coverage reliability When the mismatch factor is zero, Table 2 displays the coverage reliability of a normal scheduler and a CP-based scheduler. From the table, we infer that the coverage reliability is independent of the number of delayed slots because it is almost constant for all the delayed slots, and the coverage reliability of the CPbased scheduler is slightly greater than that of the normal scheduler. The authors are grateful to the Centre for Internet of Things (CIoT), Madras Institute of Technology Campus, Anna University, for providing the resources needed to complete the research. 7 Conflict of interest Table 2: Coverage reliability-when mismatch factor 0 Number Coverage of delayed Reliability of slots normal scheduler 1 0.8185 2 0.8186 3 0.8188 4 0.8189 5 0.8191 The authors declare that there is no conflict of interest. Coverage reliability of CP- based scheduler 0.8990 0.8993 0.8995 0.8998 0.8999 8 References 1. 2. When there is a mismatch factor 1, Table 3 shows the coverage reliability of a normal scheduler and a CPbased scheduler. From the table, we infer that the coverage reliability is independent of the number of delayed slots because it is almost constant for all the delayed slots, and the coverage reliability of the CPbased scheduler is slightly greater than that of the normal scheduler. 3. Table 3: Coverage reliability-when mismatch factor 1 Number Coverage of Delayed Reliability of Slots Normal Scheduler 1 0.9855 2 0.9856 3 0.9856 4 0.9858 5 0.9859 Coverage Reliability of CP- Based Scheduler 0.9525 0.9535 0.9555 0.9575 0.9585 4. 5. 5 Conclusions 6. The proposed work creates a framework for static resource allocation for a limited number of users and a dynamic resource allocation for a larger number of users. The proposed static resource allocation strategy has outperformed the fixed bandwidth and fixed frequency resource allocation strategies. The parameters such as efficiency, Reliability of the users has been carried out to monitor the performance of it and with respect to mismatch values. The proposed dynamic resource allocation strategy achieves an eMBB efficiency of 70% and URLLC reliability of 90%. 7. 44 P. Ramesh and P. T. V. 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Arrived: 06. 05. 2024 Accepted: 01. 10. 2024 45 46 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.104 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 47 – 54 Fractal Resonator Based Frequency Reconfigurable Antenna with Varying Capacitive Effect for Wireless Applications Abitha Thangam Manoharan1, Balakumaran Thangaraju2 Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Tamilnadu, India 2 Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Tamilnadu, India 1 Abstract: A frequency reconfigurable antenna for wireless applications using a fractal antenna structure is proposed. The fractal antenna is composed of a step resonator type which has a mirror image at the vertical axis in the top with a slit and a parallel mirror image at the vertical axis in the bottom without a slit. The resonating frequency of the fractal antenna is controlled by a PositiveIntrinsic-Negative (PIN) diode. Two PIN diodes are connected between the top and bottom of the fractal antenna. With the varying capacitance effect, the four possible modes of operation of the diode are obtained at the dual resonating frequency of 2.7 and 3.2 GHz. The proposed design holds significant potential for applications in Fifth Generation New Radio (5G NR) n1 band, and Wireless Fidelity (Wi-Fi) access points due to its small size and easy control mechanism. The Specific Absorption Rate (SAR) values were analyzed and are within the safety limits. Keywords: Reconfigurable Antenna, Fractal, PIN diodes, Wireless, SAR Frekvenčno nastavljiva antena s spreminjajočim se kapacitivnim učinkom za brezžične aplikacije, ki temelji na fraktalnem resonatorju Izvleček: Predstavljena je frekvenčno nastavljiva antena za brezžične aplikacije, ki uporablja fraktalno strukturo antene. Fraktalna antena je sestavljena iz stopničastega resonatorja, ki ima zrcalno sliko na vrhu navpične osi z režo in vzporedno zrcalno sliko na dnu navpične osi brez reže. Resonančno frekvenco fraktalne antene nadzoruje dioda PIN (Positive-Intrinsic-Negative). Dve diodi PIN sta povezani med zgornjim in spodnjim delom fraktalne antene. S spreminjajočim se kapacitivnim učinkom se pri dvojni resonančni frekvenci 2,7 in 3,2 GHz dosežejo štirje možni načini delovanja diode. Predlagana zasnova ima zaradi svoje majhnosti in enostavnega mehanizma upravljanja velik potencial za uporabo v frekvenčnem pasu n1 nove radijske zveze pete generacije (5G NR) in dostopnih točkah brezžične povezave (Wi-Fi). Analizirane so bile vrednosti specifične absorpcijske hitrosti (SAR), ki so v mejah varnosti. Ključne besede: Konfigurabilna antena, fraktali, diode PIN, brezžična povezava, SAR * Corresponding Author’s e-mail: abithathangam@gmail.com 1 Introduction Sixth Generation (6G), etc., in mobile phones has been increasing nowadays. The antenna for operating at the modes mentioned earlier is designed separately [1] and integrated into a single smartphone unit. As the space complexity is high, the heat liberated from the The use of wireless technologies such as Wi-Fi, Wireless Gigabit Alliance (WiGig), Light fidelity (Li-Fi), Near-field communication technology, Fifth Generation (5G), How to cite: A. Thangam Manoharan et al., “Fractal Resonator Based Frequency Reconfigurable Antenna with Varying Capacitive Effect for Wireless Applications", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 1(2025), pp. 47–54 47 A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 phones is increasing day to day. Also, there are some major considerations to be taken care of in the design of 5G smartphones, such as resonant frequency, antenna size, isolation, and SAR. A compact reconfigurable antenna of size 18 x 20 x 0.035 mm3 has been designed. The top and bottom patches are connected through PIN diodes, and the frequency reconfigurable antenna switches at four different cases. The SAR analysis was done for the four cases of PIN diode switches and the results were analyzed. Reconfigurable Antenna finds applications where different frequencies are utilized in the same node like smartphones, Security, Radio Detection and Ranging (RADAR), and Automation etc.,. A frequency reconfigurable antenna [2] is a single antenna that switches to multiple frequencies, instead of using several antenna array elements for different frequencies. This reduces the antenna space, cost and also improves the compactness of the antenna size. The magneto-electric dipole [3] and Vivaldi antenna [4], [5] are large in size and have unidirectional beams. These characteristics are not suitable for portable devices, where a compact size is preferred. The proposed antenna is designed to reduce the size of the reconfigurable antenna and aims at reducing the SAR. 2 Antenna design The FR4 epoxy substrate of thickness 1.6 mm, and a loss tangent of 4.4 is constructed over the ground plane. To achieve the resonant frequency at the desired level, the defective ground is designed as an inverted E and C-shaped structure. The substrate has a cross-sectional area of 20 x 21 mm2 and the patch has a cross-sectional area of 18 x 20 mm2. The fractal antenna is composed of a step resonator type which has a mirror image at the vertical axis in the top with a slit and a parallel mirror image at the vertical axis in the bottom without a slit. The dimensions of the fractal antenna design are shown in Table 1. The top view and bottom view of the antenna are shown in Figure 1 (a) and (b). The switching in the reconfigurable antenna is achieved by electrical, mechanical, and optical modes. The electrical switching of frequencies is obtained by PIN diodes, Varactor diodes and Radio Frequency Microelectromechanical Systems (RF MEMS) switches. The mechanical switching is done by rotation in angular or linear motion, whereas the optical switching is done using Optical Fibre Cable (OFC), Light-emitting diode (LED) and Light amplification by stimulated emission of radiation (LASER). Of all the modes, electrical switching consumes power because an external supply is needed to bias the diodes. Despite huge power consumption, electrical switching is more advantageous due to its efficiency, reliability, and ease of integrating with microwave circuitry [6]. To switch the PIN diodes used in a reconfigurable antenna, some of the techniques used are external biasing circuit with a battery [7] and a remotely controlled Arduino unit [8]. Switching ON the PIN diode needs a high tuning speed, a high direct current (DC) bias current in the ON state, and a high power-handling capacity [6]. Owing to its reliability and cost-effectiveness, electrical switching using PIN diodes is more suitable for reconfigurable antenna. Figure 1: (a) Top view of antenna The proposed antenna is designed and simulated using Computer Simulation Technology (CST) Microwave Studio software. The PIN diode is inserted between the antenna phases at two points and is shown in Figure 2. For different switching cases of PIN diodes, the return loss and resonant frequency are tabulated. For the four switching states of the diode, the value of the inductance and capacitance are chosen from the PIN diode datasheet. The diode ON state is formulated using an equivalent circuit consisting of 4.7 Ω resistor connected in series with 0.015 nH inductor. While the OFF state is formulated with an equivalent circuit of parallel combination of 4.7 Ω resistor and 0.017 pF capacitor connected in series with 0.015 nH inductor. The Electromagnetic (EM) radiation emitted from the antenna gets coupled to the human tissue and alters the biological functions of the body [9]. The EM absorption by humans is measured in terms of SAR. As per the Federal Communications Commission (FCC), American National Standards Institute / Institute of Electrical and Electronics Engineers (ANSI / IEEE), and Safety Code 6 standards the recommended SAR values are 0.08 W/kg for a Whole body and 1.6 W/kg for over any 1gram (g) of tissue [10]. 48 A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 2.1 Antenna working strategy The substrate of the antenna was designed initially considering a conventional rectangular Microstrip patch antenna for the frequency of 3.5 GHz using the equation (1) and (2) by calculating the effective dielectric constant based on the height, dielectric constant & width of the patch antenna, and effective length [11], [12]. Leff   eff Figure 1: (b) Bottom View of Antenna Parameters Dimension (mm) Parameters Dimension (mm) Parameters Dimension (mm) 1 4 1 6 1 3 2 3 4 6 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 8 2 4.5 1.5 1.5 2.5 3.5 7 1.5 3.5 F11 F12 F13 F14 F15 F16 F17 F18 1 2 5 5 2 8.25 1.5 5.5 2 f r  eff (1)  1 r 1  h   r  1  12   2 2   w  0.5 (2) The antenna design is then optimized to incorporate the fractal step resonator structure with a split in the middle. This creates a capacitive effect between the structures as shown in Figure 3 and shifts the frequency based on the diode switching condition. For case (i) when two diodes are off, the large area is utilized for the capacitance effect and the distance between the plates is increasing [13], thereby decreasing the capacitance as computed in the equation.(3). Due to this, the resonant frequency shifts lower to 2.878 GHz. Table 1: Dimension of antenna structure G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 c C  0 r A (3) d where, εo– permittivity of air εr – relative permittivity A – Area of the plate d – distance between the plates For case (ii), when the diode D1 is inserted- Diode (10) case, the capacitance values are reduced by 3.09 x 1015 F. This result in another resonant frequency shifted left at 3.175 GHz in addition to 2.729 GHz. Similar results were obtained for case (iii)-Diode (01). For case (iv), When the diodes D1 and D2 are inserted, both the diodes are ON, and the resonant frequency is shifted higher to 3.252 GHz. At the bottom of the substrate, an inverted E- shaped structure is tilted towards the horizontal plane. In the middle of the E-structure, a small projection is connected to an inverted C-shaped structure. The inverted E and C-shaped structures together constitute the defective ground structure. The defects introduced in the ground plane alter the current distribution and result in variations of slot resistance, capacitance, and inductance. Figure 2: Antenna with PIN diode 49 A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 3 Experimental results The designed antenna is fabricated and tested using Vector Network Analyzer (VNA). The width and height of the antenna are 18 mm and 20 mm respectively and are depicted in Figure 4 (a) and (b). The antenna is provided with a port extension to check the output at the VNA connected. The bottom view of the antenna with defective ground inverted E and C-shaped structure is shown in Figure 5. Figure 4: (b) Height of antenna Figure 3: Illustration of capacitive effect The PIN diode of type BAP65-03,115 is used as an RF switch for achieving frequency reconfigurability in the fractal antenna. The insertion of two PIN diodes in between the antenna elements results in four different switching cases such as 00, 01, 10 and 11 for OFF-OFF, OFF-ON, ON-OFF and ON-ON conditions. When one of the diodes is ON, the diode acts as a short circuit, and the inductive reactance dominates. As the diode is OFF, the diode acts as an open circuit, and capacitive reactance dominates. The inductive reactance shifts the resonant frequency (fr) to a higher frequency (fr +∆f ) whereas capacitive reactance shifts it to a lower frequency (fr -∆f ). Figure 5: Fabricated antenna – bottom View The experimental setup consisting of the fabricated fractal antenna with PIN diode and VNA is shown in Figure.6. To switch ON the diode, a 3V battery is connected across the PIN diodes through wires. The diode is said to be in OFF state when the battery is disconnected, as no current flows through the diode. The return loss values are tabulated in Table 4 where the switching of the diode results in antenna resonating between 2.713 GHz and 3.252 GHz frequencies. The experimental results obtained through VNA are depicted in Figure 7 for the diode 10 state. The switching in the diode is considered to be a short circuit case for each of the diodes being set ON. The inductive reactance dominates when both the diodes are ON and resonate at a high frequency of 3.252 GHz. Similarly, when both the diodes are OFF, it acts as open-circuited capacitance. The fractal antenna resonating frequency is shifted to the lower frequency of 2.878 GHz. The average frequency, fav is calculated by taking the mean of the highest and the lowest frequency values considering ON-ON and OFF-OFF cases of the diodes. From the results obtained the average frequency of Figure 4: (a) Width of antenna 50 A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 Figure 6: Antenna testing with VNA 4 SAR Measurement 3.065 GHz shifts higher to 3.252 GHz with a ∆f of 0.187 GHz due to inductive effect, and shifts lower to 2.878 GHz due to capacitive effect. The Electromagnetic absorption by humans is measured in terms of specific absorption rate (SAR). As per the FCC, ANSI/IEEE and Safety code 6 standards the recommended SAR values for smartphones are 0.08 W/kg for a Whole body and 1.6 W/kg for over any 1gram (g) of tissue. This maximum is set to 1.6 W/kg averaged over 1g of tissue, or 2 W/kg averaged over 10g of tissue [14]. The scattering parameter S11 depicts the return loss obtained for each case of the connected diode in the fractal antenna. From the obtained results given in Table 4, the antenna exhibits a return loss of less than -10 dB for all four combinations of diodes. The lowest return loss value of -31.57 dB is obtained for the antenna operating at 2.729 GHz when the diode is in ON-OFF (10) state. The six-layer human head model (Figure 8) consisting of skin, fat, bone, Dura, Colony-Stimulating Factor (CSF), and brain is assumed to be a sphere and it is designed based on the properties of permittivity, conductivity, and thickness [15]. It acts as an absorbing surface for the radiations from the proposed antenna. Figure 8: Six layer human head model Figure 7: Return loss for diode – ON-OFF (10) state The tissue properties of these layers are taken into account to examine the amount of radiation. The tissue properties considered are permittivity, conductivity, 51 A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 and thickness, and the values corresponding to each layer are shown in Table 2 cited in [15]. The six-layer human head model is placed in the front of the antenna designed and the SAR is computed in CST Microwave studio as shown in Figure 9. can be used in 5G smartphones to be operated at 2.713 GHz, 2.729 GHz, 2.878 GHz, 3.175 GHz, 3.183 GHz and 3.252 GHz frequencies. Table 4: Return loss and SAR values Table 2: Tissue properties of human head model Tissue Permittivity Skin Fat Bone Dura CSF Brain 40.7 10 20.9 40.7 79.1 41.1 Conductivity (S/m) 0.65 0.17 0.33 0.65 2.14 0.86 Diode Resonant Switching frequencies States (GHz) D1D2 00 2.878 01 2.713 3.183 10 2.729 3.175 11 3.252 Thickness (mm) 1 0.14 0.41 0.5 0.2 81 SAR Return loss (dB) (W/kg) -18.44 -30.52 -17.71 -31.57 -16.76 -37.52 0.294 0.334 0.149 0.648 0.173 0.174 In the proposed work, SAR analysis is performed in the human head model considering 10 g of tissue to test the electromagnetic absorption from the antenna. The simulation results infer that the SAR value holds within the safety limit of 2 W/kg averaged over 10g of tissue. Figure 9: Head model with Antenna in CST The computed SAR value for diode 00 state at 2.878 GHz is shown in Figure. 10 and is well within the standard safety limits. The SAR value for diode 10 state operating at 2.729 GHz is 0.648 which is higher as compared with other cases of diode switching (Table 4). The comparison of State-of-the-art antennas is given in Table 3. The proposed antenna is compact as compared to other stateof-the-art antennas. As the space occupied is lesser, it Figure 10: SAR Analysis- diode 00 state-2.878 GHz Table 3: Comparison with the state-of-the-art antennas Ref Antenna size (mm2) Substrate (εr , h in mm) Resonant Frequencies (GHz) Reconfigurable SAR Analysis [16] 33×21 FR4-εr =4.3, h =1.6 3.3-3.7, 5-5.30 Yes No [17] 30×40 Rogers (RO4350B) – εr =3.66, h =0.76 3, 6.8 Yes No [18] 46×52 FR4-εr =4.4, h =1.6 3.42 – 3.82, 5.17- 6.07, 6.89 -7.48 (OFF-OFF State) Yes No [19] 24×30.5 RO4003C-εr =3.38, h =1.5 3.5 and in between 5.45-5.9 Yes No [20] 82.77x83.53 Taconic RF-30 – εr=4.4, h= 1.6 mm 1.8,2.7,3.1,3.3,4.1,5.1,5.4 Yes No This Work 18 x 20 FR4-εr =4.3, h =1.6 2.713, 2.729, 2.878, 3.175, 3.183 and 3.252 Yes Yes 52 A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 5 Conclusion 7. The fractal-based reconfigurable antenna is designed and analyzed for wireless applications. The S parameter results show better agreement for the numerical calculations obtained by substituting the capacitance value. The capacitance effect shifts the resonant frequency to a higher level and an average increase of return loss in dB to 50%. The SAR values are also analyzed for different diode-switching cases. The low SAR (0.149) is obtained for the diode 01 case operating at 3.183 GHz and the high SAR (0.648) for the diode 10 case operating at 2.729 GHz. The SAR values are well within the safety limits. 8. 9. 10. 6 Conflict of interest We, the authors, declare no conflict of interest 11. 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Kim, “Frequency-agile WLAN notch UWB antenna for URLLC applications,” Computers, Materials & Continua, vol. 67, no. 2, pp. 2243-2254, 2021. A. Thangam Manoharan et al.; Informacije Midem, Vol. 55, No. 1(2025), 47 – 54 20. M. M. Ismail et al., “Multi-Beam Metasurface Control Based on Frequency Reconfigurable Antenna“, Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 54, No. 2,2024, pp. 77–85. Copyright © 2025 by the Authors. This is an open access article distributed under the Creative Commons Attribution (CC BY) License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 08. 06. 2024 Accepted: 01. 10. 2024 54 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.105 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 55 – 64 Design and Optimization of Multiple-Channel Double Dynamic Switching Biased Op-Amp for Switched Capacitor Integrator Using FinFET Technology Morteza Babaeian Far1, Mehmet Aytuğ Ormancı1,2, Fırat Kaçar1 Department of Electrical and Electronics Engineering, Istanbul University–Cerrahpaşa, Avcilar, Istanbul, Türkiye 2 Department of Electronics and Communication Engineering, Istanbul Technical University, Maslak, Istanbul, Türkiye 1 Abstract: This paper presents the design and optimization of a parametric multiple-channel Double Dynamic Switching Biased Complementary Folded-Cascode Amplifier with switched capacitor integrator application in 32nm FinFET technology. The LTspice simulations demonstrate that the amplifier can attain an open-loop DC gain of 44.8dB, and a phase margin of about 87.8° with ±0.5V supply voltages. Moreover, the amplifier power consumption is measured 246µW including bias circuitry and a Gain-Bandwidth Product (GBW) of 77.45MHz under a 5pF load capacitor. The circuit’s stability enables it to offer diverse design capabilities tailored to specific application needs. This novel design is capable of reducing supply voltages and power dissipation. Keywords: 32nm FinFET Technology, Complementary Folded-Cascode Amplifier, Double Dynamic Switching Bias, Self-Cascode, Switched Capacitor Načrtovanje in optimizacija večkanalnega dvojnega dinamičnega preklopnega optičnega ojačevalnika za stikalni kondenzatorski integrator z uporabo tehnologije FinFET Izvleček: Članek predstavlja načrtovanje in optimizacijo parametričnega večkanalnega ojačevalnika z dvojnim dinamičnim preklopom, ki se opira na komponente z zloženo kaskodo, z uporabo integratorja s preklopnim kondenzatorjem v 32 nm tehnologiji FinFET. Simulacije LTspice kažejo, da lahko ojačevalnik doseže ojačenje z odprto zanko DC 44,8 dB in fazno rezervo približno 87,8° pri napajalnih napetostih ±0,5 V. Poleg tega je izmerjena poraba energije ojačevalnika 246 µW, vključno z napajalnim vezjem in GBW 77,45 MHz pri obremenitvenem kondenzatorju 5pF. Stabilnost vezja omogoča diverzno načrtovanje s prilagoditvami glede na potrebe aplikacije. Ta nova zasnova lahko zmanjša napajalne napetosti in porabo. Ključne besede: 32nm FinFET tehnologija, komplementarni kaskodni ojačevalnik, Dvojno dinamično preklapljanje polarizacije, Preklopni kondenzator * Corresponding Author’s e-mail: fkacar@iuc.edu.tr How to cite: M. Babaeian Far et al., “Design and Optimization of Multiple-Channel Double Dynamic Switching Biased Op-Amp for Switched Capacitor Integrator Using FinFET Technology", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 1(2025), pp. 55–64 55 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 1 Introduction switching capability [2]. This amplifier exhibits high power dissipation and occupies significant physical space. Operating with a supply voltage of 3V and consuming 9.2mW of power, it is suitable for signal processing applications. However, integrating it as an element in new-generation devices may pose challenges. In semiconductor technology, the constant search for smaller, faster, and more energy-efficient transistors has driven technological innovation. Recent advances at the nanoscale level and the advent of multi-gate transistors have ushered in a new era of complexity in the design process. One such breakthrough technology that has attracted significant attention in the integrated circuit (IC) design industry is FinFET transistors. These transistors offer promising solutions to the challenges of shrinking device dimensions and enable performance and efficiency in modern semiconductor devices. This study discusses the development of a Complementary Folded-Cascode (CFC) Op-Amp, designed to operate with a supply voltage of 1V (±0.5V) and achieve operational performance with a power consumption level of 246μW. PTM 32nm FinFET technology was chosen for the designs to leverage its advantages, including lower power consumption, higher density, improved scaling, enhanced reliability, and compatibility with future advancements in semiconductor technology. In line with FinFET technology, the self-cascode structure was employed, enabling both an increase in output resistance and the ability to design at lower voltages. This feature enables the design to have parametric flexibility. Moreover, integrating the DDSB circuit in [2] helps reduce undesirable phenomena such as noise and process variations, consequently enhancing the overall performance and stability. The stability and performance of the proposed circuit under various conditions were analyzed using the SC integrator application, yielding the expected triangle behavior. On the other hand, the relentless pursuit of miniaturization and performance improvement in electronic circuits extends beyond transistors to encompass various facets. Market demands and the push for advancements in portable electronics have compelled the industry to develop circuits with low voltage (LV) requirements and often restricted power consumption, presenting a significant challenge. Many emerging products must operate at voltages of 3V or lower to stay competitive in an industry characterized by rapid turnover [1]. Implantable medical electronic devices, especially those incorporating analog and digital circuits, are prime examples of this scenario. In this paper, Section 2 elaborates on the FinFET, the integration of the self-cascode structure with FinFET, and the development of the CFC Op-Amp with DDSB. Section 3 provides details on the SC integrator topology and its FinFET-based design. Additionally, this section discusses the performance evaluation of the integrator, while Section 4 summarizes the conclusions. Results obtained reveal that the novel design employed in the present study can reduce the amount of supply voltages and power dissipation. In this competitive landscape, numerous proven techniques are used in innovative circuit design as essential for market viability. For instance, companies are increasingly utilizing CMOS switched capacitor (SC) methods for implementing analog signal processing integrated circuits (ICs) due to their effectiveness. Previous research has demonstrated the effectiveness of utilizing SC techniques with CMOS operational amplifiers (OpAmps) to implement analog functions such as filters [2-4]. However, using multiple Op-Amps often creates significant power consumption, potentially leading to operational instability. To mitigate power dissipation associated with Op-Amps, various strategies including reduced supply voltages, bulk-driven topologies, floating-gate transistors, self-cascode structures, and subthreshold designs have been explored [1, 5]. 2 Design of CFC op-amp 2.1 FinFET The inception of FinFET-like structures traces back to the introduction of a Fully Depleted Lean Channel Transistor (DELTA) by Hisamoto et al. in 1989 [6, 7], highlighting the longstanding pursuit of enhanced transistor architectures. The distinctive three-dimensional structure of FinFETs, with a thin silicon body formed perpendicular to the wafer plane, enables superior electrostatic control and reduced leakage compared to traditional planar MOSFETs [8]. FinFET transistors, operating at nanoscale dimensions, exhibit reduced Drain-Induced Barrier Lowering (DIBL) and mitigated In achieving high-speed operation, it is crucial to carefully address design considerations regarding distortion alongside the increase in power dissipation. This necessity arises from the intrinsic capability of Op-Amps to process analog signals. On the other hand, prior research has introduced a CMOS FoldedCascode (FC) Op-Amp with a Double Dynamic Switching Biased (DDSB) in a simplified configuration to ensure minimal power consumption while maintaining 56 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 other Short-Channel Effects (SCEs), thereby enhancing overall performance and reliability [9]. This translates to higher on-state current, lower leakage, and faster switching speeds, making FinFETs an attractive option for many applications. Moreover, the fabrication process for FinFET transistors is compatible with conventional CMOS processes, enabling seamless integration into existing technologies. For a DG-FinFET, when the biasing condition is appropriate, current flows from the source to the drain under the influence of the corresponding sidewall gates, spanning the height Hfn of each fin. Consequently, the width (W) of the FinFET structure depends on the height of the fins. For a single-fin DG-FinFET, the total width can be determined as in equation (1). W  2 H fin (1) Overall, FinFETs operate via three primary mechanisms: independent-gate (IG) connection, shorted-gate (SG) connection, and low-power (LP) mode [10]. As depicted in Fig. 1(a), the SG type features a three-terminal device. SG FinFETs present a promising alternative to MOSFETs, offering increased on-state current and faster transition speeds, thus enhancing performance. Moreover, robust gate control provides enhanced suppression against SCEs and gate-dielectric leakage. A thick masking oxide, Tmask, can be utilized to enable the operation of the devices as Double-Gate (DG) FinFETs, with sidewall gates providing electrical functionality exclusively. This study presents an Op-Amp design utilizing IG FinFETs operating in LP mode. The simulations are based on the Predictive Technology Model (PTM) for 32nm FinFETs. PTM is selected as the simulation model due to its comprehensive coverage of physical effects and excellent scalability. This approach enables precise predictions and enhances efficiency in circuit design. Overall, the combination of the Op-Amp design with the self-cascode structure for IG FinFETs in LP mode, supported by PTM, presents a promising approach for optimizing circuit performance in advanced semiconductor technologies [8]. The IG type eliminates the upper portion of the gate to create two separate gates, as shown in Fig. 1(b). Operating as a four-terminal device, this configuration allows the front and back gates to be coupled to distinct inputs. Consequently, the IG FinFET can function as a pair of parallel transistors, enhancing design flexibility and significantly reducing the number of transistors. LP mode is an exception to the typical behavior of the IG mode, effectively reducing threshold leakage by adjusting the back gate voltage, as noted in [8]. Further details on the operation modes can be found in [10]. 2.2 Self-Cascode structure The self-cascode configuration is depicted in Fig. 2 as a two-transistor setup, which can be viewed as an individual composite transistor. This composite structure exhibits a significantly extended effective channel length and output resistance. The lower transistor, referred to as F2a, functions as an input-dependent resistor. To maintain optimal performance, the W/L ratio of F2b is set more significantly larger than that of F2a, denoted as C>1 [5]. Fig. 3 illustrates the results obtained by adjusting the structure using the parameters Composite (C) and Multiplier (M). One notable observation is the increased output resistance compared to configurations utilizing a single FinFET as expected. Increasing the value of C, which solely enlarges the size of F2b, leads to elevated output resistance. Similarly, increasing the value of M Figure 1: FinFET connection types: a): shorted-gate, b): independent-gate. Figure 2: a) Single FinFET, b) Self-cascode structure. 57 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 enlarges both FinFETs within the self-cascode structure, thereby increasing the current. g mT  g mN  g mP  g m 2 a  2b   g m 2 Aa  2 Ab  (2) The output resistance, Ro, which indicates the small-signal resistance seen from the drain of F7a-F7b and F9a-F9b, can be calculated using the parallel combination of (3a) and (3b) [6, 12]. RoN  g m 9 a 9b  ro 9 a 9b   ro 2 Aa  2 Ab  ro11a 11b     (3a) RoP  g m 7 a 7 b  ro 7 a 7 b   ro 2 a  2b  ro 5 a 5b     (3b) Fig. 5 illustrates the configuration of the DDSB. In the circuit, the initial group of FinFETs FB1-FB4 manages the activation state of self-cascoded current source (i.e., F3Aa-F3Ab) and self-cascoded FinFETs F6a-F6b, F7a-F7b within the CFC Op-Amp by regulating the bias voltage VDDSBP. This modulation spans approximately –160mV to 320mV and is achieved through a designated control pulse, фBP. Similarly, the subsequent group FB5-FB8 oversees the activation status of self-cascoded current source (i.e., F3a-F3b) and self-cascoded FinFETs F8aF8b, F9a-F9b by adjusting the bias voltage VDDSBN within a range of approximately –120mV to –380mV, controlled by pulse designated as ФBN. Figure 3: Operational outcomes for both single FinFET and self-cascode structures under various parameters (@VFG=0.5V, @VBG=VS=GND, W1/L1=80nm/64nm). 2.3 Proposed CFC Op-Amp Fig. 4 illustrates the proposed CFC Op-Amp configuration. The operational amplifier is biased with a DDSB circuit for low power consumption. To enhance input common mode voltage, a CFC is implemented, which consists of parallel-connected self-cascoded FinFETs F1Aa-F1Ab, F2Aa-F2Ab and self-cascoded FinFETs F1a-F1b, F2aF2b differential input pairs. For the differential input, the current sources are self-cascoded FinFETs F3Aa-F3Ab and F3a-F3b. Instead of a traditional cascode current mirror, a wide-swing cascode current mirror is selected to ensure a broad dynamic range, even at reduced supply voltages [6]. Figure 5: Configuration of the DDSB [2]. Figure 4: Proposed CFC Op-Amp configuration. The low-frequency gain of the proposed circuit can be determined by Aν = gmTRo. Here gmT is the total transconductance of the input stage, which is given in (2). Figure 6: a) Operation waveforms of the DDSB clocks, b) DDSB outputs. 58 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 The operating waveforms of DDSB clocks are depicted in Fig. 6a, while the output voltages are shown in Fig. 6b. As indicated by their shape, the Op-Amp is designed to turn off at 100ns and then turn on again simultaneously. This integration helps mitigate side effects and provides better stability with low power consumption [2] for the proposed Op-Amp. The transistor dimensions utilized in the DDSB CFC Op-Amp are provided in Table 1. trated in Fig. 7. The circuit’s Common-Mode Rejection Ratio (CMRR) and comprehensive input-referred noise characteristics across a wide frequency band are presented in Fig. 8. When the parameters are set to C=1 and M=1, the CMRR reaches 50.62dB. Noise analysis at these dimensions indicates that the circuit exhibits input noise voltage densities of 3.6µV/√Hz at 100Hz and 161.5nV/√Hz at 1MHz. Specifically, the input-referred noise voltage density increases with the rise in the C coefficient, while it decreases with the increase in the M coefficient at frequencies close to DC. By analyzing the frequency response diagrams for voltage gain, phase margin, CMRR, and noise, as shown in Figs. 7 and 8, the performance of the designed amplifier for different values of C and M is compared in Table 2. Table 1: Transistors’ aspect ratios. FET F1Aa F1Ab F1a F1b F2Aa F2Ab F2a F2b F3Aa F3Ab F3a F3b F4a F4b F5a F5b F6a F6b W/L (nm/nm) (1520*M)/64 (1520*M*C)/64 (1520*M)/64 (1520*M*C)/64 (1520*M)/64 (1520*M*C)/64 (1520*M)/64 (1520*M*C)/64 (420*M)/64 (420*M*C)/64 (650*M)/64 (650*M*C)/64 (500*M)/64 (500*M*C)/64 (500*M*C)/64 (500*M*C)/64 (800*M*C)/64 (800*M*C)/64 FET F7a F7b F8a F8b F9a F9b F10a F10b F11a F11b FB1 FB2 FB3 FB4 FB5 FB6 FB7 FB8 W/L (nm/nm) (800*M)/64 (800*M*C)/64 (450*M)/64 (450*M*C)/64 (450*M)/64 (450*M*C)/64 (500*M)/64 (500*M*C)/64 (500*M)/64 (500*M*C)/64 200/64 200/64 64/64 180/64 250/64 80/64 200/64 300/64 M: Multiplier, C: Composit 2.4 Simulation results The performance of the DDSB CFC Op-Amp was evaluated through simulations using the LTspice software. Increasing the C value results in elevated output resistances, as depicted in Fig. 3, subsequently boosting the circuit’s gain. Likewise, increasing the M value enlarges both FinFETs within the self-cascode structure, thereby raising the current and consequently expanding the bandwidth. Thanks to the stability maintained by DDSB, this structure proposed in the paper enables the design to be tailored to different purposes and needs. It is important to note that increasing the values of C and M enhances the circuit’s performance, but it also leads to an increase in layout size and power dissipation. For C=5 and M=5, the results reveal a gain of 44.88dB, a bandwidth of 42.1kHz, a Unity Gain Frequency (UGW) of 77.45MHz, and a phase margin of 87.8° with 5pF load capacitance. The AC response of the circuit for four different scenarios, based on variations in C and M, is illus- Figure 7: AC response of proposed Op-Amp: a) gain, b) phase. Figure 9 illustrates the variation in the Gain-Phase characteristics of the circuit with respect to CL and temperature. In Figure 9a, it is observed that for C=1 and M=1, increasing CL from 0.5pF to 5pF results in a UGW of 87.1MHz with a load of 0.5pF, maintaining stability with a phase margin of 89.4°. Further analysis shows that 59 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 with CL=10fF, the circuit achieves a UGW of 3.19GHz and a phase margin of 44.93°. When the parameters are set to C=5 and M=5, the circuit remains stable up to a load capacitance of approximately 220fF, providing a UGW of 1.38GHz and a phase margin of 45.5° for this load. The frequency response of the Op-Amp was analyzed over a wide temperature range from -40°C to 100°C, with simulations conducted at 20°C intervals as depicted in Fig. 9b. Under the conditions of C=1 and M=1, the gain and phase characteristics at -40°C are 39.8dB and 90.5°, respectively, while at 100°C they are 34.2dB and 90.1°. This indicates that the small-sized Op-Amp exhibits low sensitivity to thermal variations. This stability across the temperature range decreases as the Op-Amp size is increased. Figure 9: Gain-phase response variation (@C=1, M=1): a) with CL, b) with temperature. Figure 8: CMRR and input referred noise performance results of the proposed Op-Amp. to the high phase margin. The fluctuations in the transition band are caused by the operation of the DDSB, which continuously switches the circuit on and off. This behavior is also observed during rising and falling transitions and presents a disadvantage by reducing the SR. For a 1pF load capacitor, the measured In this paper, the slew rate (SR) was determined by using an 800mV peak-to-peak input (–400mV to 400mV) employing a 10-90% threshold. Fig. 10 shows the step response of the Op-Amp under varying load capacitances (CL) from 1 pF to 5 pF. The simulation results indicate that the circuit provides a stable output due Table 2: Performances of the DDSB CFC Op-Amp. C=1 M=1 37.42 90.66 8.46 50.62 C=5 M=1 44.80 89.85 14.82 59.16 C=1 M=5 37.72 90.10 43.15 50.61 C=5 M=5 44.88 87.8 77.45 59.13 nV Hz 3607/161.5 5246/128.9 1930/36.4 3605/79.4 Output Ref. Noise (a/b) μV Hz 277.6/1.37 912.4/2.01 148.6/1.36 627/ 5.66 Power Dis. mW 0.083 0.097 0.179 0.246 Parameters Unit Open Loop Gain (DC) Phase Margin UGW CMRR dB ° MHz dB Input Ref. Noise (a/b) CL=5pF, (a): @100Hz, (b): @1MHz 60 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 @C=5, M=5). To facilitate a comparison of truly lowpower structures, the two Figures of Merit (FoM1,2), as utilized in [13], have been employed regarding smallsignal and large-signal power. FoM 1 = GBW  CL Pdiss (4a) SRa  CL Pdiss (4b) FoM 2 = Where SRa=(SR++SR–)/2 represents the average value of slew rates of rising and falling edges of the output. It should be noted that FoM1 and FoM2 relate small-signal gain bandwidth and slew rate to dissipation power. Figure 10: Step response of proposed Op-Amp for C=1, M=1: a) SR+ b) SR-. When comparing the data in Table 3, it can be observed that the proposed circuit (C=5, M=5) outperforms other published circuits in terms of FoM1, providing 1574(MHz∙pF)/mW. Regarding FoM2, the value of 1440(V∙pF)/(µs∙mW) from reference [14] stands out. The advantage of this study lies in its design, which includes a slew rate enhancement block aimed at achieving a high slew rate. However, the low phase margin value of 48.2° achieved by this circuit with 8pF load capacitance is a significant factor, and the likelihood of unstable operation increases with lower capacitive loads. SR+ (SR-) is 12.8 (9.3)V/µs for C=1, M=1, while for C=5, M=5, it increases to 97 (68.6)V/µs. When CL is increased to 5pF, the SR+ (SR-) values decrease to 2.41 (1)V/µs for C=1, M=1, and to 32.2 (14.3)V/µs for C=5, M=5. Monte Carlo (MC) analysis, conducted in LTspice over 50 iterations, investigated the impact of three key parameters on the circuit’s performance: threshold voltage (V TH), oxide thickness (tox), and supply voltages (VDD, VSS). The analyses are provided insight into how minor deviations in these parameters influence the overall behavior and stability of the circuit. The results are depicted in the Fig. 11 for C=1 and M=1. 3 SC integrator application Table 3 compares Op-Amps from the literature using CMOS and FinFET technologies with the proposed DDSB CFC Op-Amp configurations (@C=1, M=1 and Switched capacitor (SC) circuits are fundamental components in the construction of integrated circuits that Table 3: Performance comparison of proposed Op-Amp with literature. Performance Parameters Unit Process N/A Power Supply Power Dissipation CL Open Loop Gain (DC) GBW Phase Margin Slew Rate (SR+/SR–)(1) FoM1 FoM2 This This [2] [6] [14] [15] [16] [17] Work(2) Work(3) 32 nm 32 nm 1 µm 0.6 µm 0.18 µm 20 nm 55nm 45nm (FinFET) (FinFET) (CMOS) (CMOS) (CMOS) (FinFET) (FinFET) (FinFET) ±0.5 ±0.5 ±1.5 1.8 1.8 ±0.5 1 1 0.083 0.246 9.2 0.24 1.18 0.377 0.648 0.175 5 5 10 20 8 3 3 0.02 37.42 44.8 47.7 80.8 68 39.27 45.51 29.22 8.46 77.45 14.3 6.9 172.5 8.26 63 5.1 90.66 87.8 47.9 71 48.2 45.05 60.1 90 2.41/1 32.2/ 14.3 106 2.2 212.5 2.3 41.34 1830/ 1120 V mW pF dB MHz ° V/µs MHz  pF 509.64 mW V  pF 103.01 µs  mW 1574 15.54 575 1169 65.72 291.66 0.582 472.56 115.21 183.33 1440 18.30 191.38 168.57 (1): For articles with a single SR, SRa=SR was considered, (2): C=1, M=1, (3): C=5, M=5. 61 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 find extensive application in a variety of domains, including voltage regulators, filters, and analog-todigital converters. The principle behind SC circuits involves capacitors’ periodic charging and discharging to perform specific signal-processing tasks. A SC circuit comprises a core network of capacitors, switches, and operational amplifiers. Switches control the connection and disconection of capacitors in the circuit and enable charge transfer between them. By opening and closing these switches at precise intervals, the circuit effectively mimics the behavior of resistors or other analog components. The history of SC circuits dates back to the middle of the 20th century, stemming from the need for more efficient analog signal processing methods. SC circuits use discrete components such as relays and mechanical switches to implement switching [18]. As discussed previously, the substitution of a resistor can be achieved by utilizing two FinFETs and a capacitor connected at a single node. The insensitive SC integrator, utilizing FinFETs as shown in Fig. 12An independent, non-overlapping clock signal controls each gate pin of the two FinFETs. This system operates under the assumption that the output is sampled at the conclusion of the ф2 clock phase. Under this assumption, the transfer function of the integrator can be derived as given in (5) [19, 20].  vo C1 / C2  T   vi jT   T 2sin    2    (5)    Here T represents the period of sampling. The operation waveforms of the SC clocks are depicted in Fig. 13. The total equivalent resistance in the circuit is set to 250kΩ. The capacitors used in the circuit, C1 and C2, each have a capacitance of 40pF. The dimensions W and L of the FinFETs were chosen as 80nm and 32nm, respectively. The integrator receives a sinusoidal input signal with a frequency of 3.33kHz and a peak voltage of 50mV. As expected, the output displays a cosine waveform. The analysis of Total Harmonic Distortion (THD) was derived from the 20ms transient response of the integrator. The performance characteristics of SC integrators designed with two different Op-Amp configurations are provided in Table 4. The operating waveforms of the SC integrator designed with C=1 and M=1 Op-Amp are shown in Figure 14. Figure 12: Configuration of the insenstive SC integrator utilizing FinFETs. Figure 11: MC Analysis results: a) tox with 3% variation, b) V TH with 1% variation, c) Power supplies (VDD, VSS) with 5% variation. 62 M. Babaeian Far et al.; Informacije Midem, Vol. 55, No. 1(2025), 55 – 64 In this case, with its provided 44.8dB voltage gain, 42.1kHz bandwidth, and 246µW power dissipation, it is highly suitable for low-power wide-band signal processing applications. 5 Conflict of Interest Figure 13: Operation waveforms of the switched capacitor clocks. The authors declare no conflict of interest Table 4: Performance Comparison of SC Integrators. 6 References Performance parameters Unit Power Supply Voltages Switching Frequency Input Signal Amplitude THD(fin =3.33 kHz) V kHz mV N/A This Work(1) ±0.5 10 50 0.336 % 1. This Work(2) ±0.5 10 50 0.251 % 2. (1): C=1, M=1, (2): C=5, M=5 3. 4. 5. 6. Figure 14: Input and output waveforms of the SC integrator (@C=1, M=1). 7. 4 Conclusions In this paper, a design of Complementary Folded-Cascode Op-Amp is presented using PTM 32nm FinFET technology. The circuit’s stability at low voltages is achieved through the integration of DDSB and wideswing cascode current mirror topologies. The dimensions of the circuit, parameterized by M and C, can be scaled down to nanoscale dimensions (C=1, M=1) according to application requirements, reducing power consumption to as low as 83µW. In this scenario, it can provide a DC gain of 37.42dB and a bandwidth of 8.46MHz. When C=5, M=5 the circuit simulations demonstrate a superior performance in terms of FoM1. 8. 9. 10. 63 S. Yan and E. Sanchez-Sinencio, “Low voltage analog circuit design techniques: A tutorial,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 83, no. 2, pp. 179-196, 2000. H. Wakaumi, “A Switched-Capacitor Low-Pass Filter with Multiple-Channel Double-DSB OP Amplifiers,” in 2021 International Conference on Electronics, Information, and Communication (ICEIC), 2021: IEEE, pp. 1-4. J.-T. Wu, Y.-H. Chang, and K. L. Chang, “1.2 V CMOS switched-capacitor circuits,” in 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996: IEEE, pp. 388-389. J.-f. Huang, J.-y. Wen, and Y.-j. Lin, “Chip design of a 10-MHz switched capacitor low-pass filter for wireless application,” in 2014 Sixth International Conference on Wireless Communications and Signal Processing (WCSP), 2014: IEEE, pp. 1-5. S. Rajput and S. S. Jamuar, “Low voltage analog circuit design techniques,” IEEE Circuits and Systems Magazine, vol. 2, no. 1, pp. 24-42, 2002. B. Song, O. Kwon, I. Chang, H. Song, and K. Kwack, “A 1.8 V self-biased complementary folded cascode amplifier,” in AP-ASIC’99. First IEEE Asia Pacific Conference on ASICs (Cat. No. 99EX360), 1999: IEEE, pp. 63-65. D. Hisamoto et al., “FinFET-a self-aligned doublegate MOSFET scalable to 20 nm,” IEEE transactions on electron devices, vol. 47, no. 12, pp. 2320-2325, 2000. N. Liao et al., “Low power adiabatic logic based on FinFETs,” Science China Information Sciences, vol. 57, pp. 1-13, 02/01 2014, https://doi.org/10.1007/s11432-013-4902-x. A. Kumar, B. Kaur, and M. Arora, “Evolution of Transistor Technology from BJT to FinFET–A study,” in International Conference on Advanced Emerging Technology (ICAET), 2016. S. K. Saha, FinFET devices for VLSI circuits and systems. CRC Press, 2020. M. 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Hadidi, “Systematic approach for IG-FinFET amplifier design using gm/ Id method,” Analog Integrated Circuits and Signal Processing, vol. 109, no. 2, pp. 379-385, 2021, https://doi.org/10.1007/s10470-021-01917-9. R. A. Thakker et al., “A novel architecture for improving slew rate in FinFET-based op-amps and OTAs,” Microelectronics Journal, vol. 42, no. 5, pp. 758-765, 2011. T. Tanzawa, “Innovation of switched-capacitor voltage multiplier: Part 2: Fundamentals of the charge pump,” IEEE Solid-State Circuits Magazine, vol. 8, no. 2, pp. 83-92, 2016. B. J. Hosticka, R. W. Brodersen, and P. R. Gray, “MOS sampled data recursive filters using switched capacitor integrators,” IEEE Journal of Solid-State Circuits, vol. 12, no. 6, pp. 600-608, 1977. K. Martin, “Improved circuits for the realization of switched-capacitor filters,” IEEE Transactions on Circuits and Systems, vol. 27, no. 4, pp. 237-244, 1980. Copyright © 2025 by the Authors. This is an open access article distributed under the Creative Commons Attribution (CC BY) License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 23. 05. 2024 Accepted: 14. 10. 2024 64 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.106 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 65 – 72 A Low-Power and Low-Noise 4-12 GHz Buck CMOS Low-Noise Amplifier with Current-Reused Technique Jian Liu1, Li Li2 School of integrated circuits, Guangdong University of Technology, Guangzhou, Guangdong Province, China 2 School of integrated circuits, Guangdong University of Technology, Guangzhou, Guangdong Province, China 1 Abstract: In this paper, a wideband fully integrated low-power and low-noise amplifier (LNA) is presented. It features an 8 GHz (from 4 GHz to 12 GHz) bandwidth and an excellent noise figure (NF) using 65 nm CMOS technology. This LNA was designed utilizing a current-reused technique and a cascode gain boost technique. In addition, the interstage inductors use series peaking to reduce the roll-off of high frequency gain and achieve high broadband gain. The proposed LNA circuit achieved high and flat power gain of 23.5±1 dB with input return loss less than -8 dB within the bandwidth of interest (4-12 GHz). The flat NF is 3.3±0.5 dB and the NFmin is a staggering 2.8 dB. Achieving the above performance, the third-order input point (IIP3) also reached -10.78 dBm, which is considered excellent. The LNA consumes 6.07 mW from a 1.2 V supply and occupies a layout area of 0.53x0.55 mm2. Keywords: low-noise amplifier (LNA); noise figure (NF); Current-reused; CMOS Ojačevalnik 4-12 GHz CMOS z nizko porabo energije in nizkim šumom s tehniko ponovne uporabe toka Izvleček: V članku je predstavljen širokopasovni popolnoma integriran ojačevalnik (LNA) z nizko porabo energije in nizkim šumom. Ima 8 GHz (od 4 GHz do 12 GHz) pasovno širino in odlično šumno število (NF) z uporabo 65 nm tehnologije CMOS. LNA ojačevalnik je bil zasnovan z uporabo tehnike ponovne uporabe toka in tehnike kaskodnega povečanja ojačitve. Medstopenjske dušilke uporabljajo zaporedno ojačitev za zmanjšanje visokofrekvenčnega ojačenja in doseganje visokega širokopasovnega ojačenja. Predlagano vezje LNA je doseglo visoko ojačenje 23,5±1 dB z vhodno povratno izgubo, manjšo od -8 dB, znotraj pasovne širine (4-12 GHz). Ravna NF je 3,3±0,5 dB, NFmin pa je 2,8 dB. Pri doseganju zgornje zmogljivosti je vhodna točka tretjega reda (IIP3) prav tako dosegla -10,78 dBm. LNA porabi 6,07 mW pri napajanju z napetostjo 1,2 V in zavzema površino 0,53 × 0,55 mm2. Ključne besede: ojačevalnik z nizkim šumom (LNA); Vrednost šuma (NF); Ponovna uporaba toka: CMOS * Corresponding Author’s e-mail: xzliujian@gdut.edu.cn 1 Introduction to the way of human work and life The development of integrated circuits [1-2]. Therefore, the LNA in UWB system has become a research hotspot. Because the performance of the first stage in the only communication system LNA amplifier directly affects the performance of the communication system, high gain and low noise figure become very important. In recent years, CMOS has become the mainstream of RF integrated circuit With the rapid development of wireless communication, integrated wireless communication chip is widely used in the whole Ball positioning system, Internet of things, smart home, sensor and other industries, has been widely used and has penetrated into thousands of households and brought great and profound changes How to cite: J. Liu et al., “A Low-Power and Low-Noise 4-12 GHz Buck CMOS Low-Noise Amplifier with Current-Reused Technique", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 1(2025), pp. 65–72 65 J. Liu et al.; Informacije Midem, Vol. 55, No. 1(2025), 65 – 72 design. Its main advantages are low cost and easy integration [3-5]. sign process and current-reused technique. Section 4 is mainly devoted to the simulation results of the key indicators of LNA under different process voltage temperature (PVT). Finally, Section 5 draws the conclusions. As defined by the Federal Communications Commission (FCC), the frequency range 4-12 GHz is considered as UWB applications [6]. The low noise amplifier (LNA) is the first stage of the receiver system, and its performance affects the entire receiver system. Since it receives weak signals from the entire bandwidth range (4–12 GHz) and provides an adequate signal-to-noise ratio for subsequent signal processing, the LNA performance is crucial. If the noise is too large, the signal will be ‘submerged’ by the noise, thus affecting the performance of the entire receiving system. Therefore, it is critical for the LNA to have a low noise factor (NF), a high and flat power gain, and good input impedance matching performance. Several techniques have recently been proposed for research design of UWB LNA [6-8]. Additionally, with the wide application of UWB, a large number of excellent papers have been reported [9-10]. One of them is in [9], A two-stage LNA based on 90 nm CMOS is reported, with the first stage being a current reuse stage and the second stage being a cascode stage. Although a relatively low power consumption of 7.2 mW and a flat gain of 12.5 dB are achieved, NF 5.2 dB and low gain are still unsatisfactory. In [10], this paper reports a single-stage cascode topology fabricated in 0.13 um CMOS. Although the gain is relatively flat, it is too low to be acceptable for processing weak signals. What is more unsatisfactory is that only 4.25±0.4 dB NF is achieved with 30 mW power consumption. 2 Circuit basic principle analysis In the circuit design process, the designer may use the traditional common source stage as the first stage of the LNA. This is because the input matching and noise matching can be achieved by adding peripheral devices. Figure. 1(a) and Figure. 1(b) respectively are the traditional common source stage schematic diagram and small signal equivalent circuit whose gain expression is as follows: Figure 1(a): Common source stage circuit diagram. In the process of analog integrated circuit design, designers need to follow the octagon principle of circuit design, and need to make a compromise between noise and gain, power consumption and matching, which requires constant debugging to achieve optimal performance. In order to compensate for the shortcomings of previous reports, this paper uses a twostage topology. The first stage uses a Complementary common source stage and uses negative feedback to reduce gain sensitivity, the second stage uses a cascode stage to compensate for the lack of gain, and uses an inducer parallel peaking between stages to make up for the roll off of high-frequency gain. At the same time, the current multiplexing technology is used to effectively utilize the current to achieve low power design of the LNA, and all MOS are operating in the saturation region to achieve excellent performance. Figure 1(b): Common source stage small signal equivalent circuit. AV   g m1 (ro1 || ro 2 ) (1) Where gm1 is the transconductance of the input transistor M1, ro1 and ro2 are the small-signal equivalent resistances of the input transistor (M1) and the current source transistor (M2), respectively. From the gain expression, it can be seen that the traditional common source stage can improve the gain by increasing the small signal resistance, which is related to the current. Therefore, the small current can achieve high gain but will bring large noise, which is not consistent with the characteristics of LNA itself. Figure. 2(a) illustrates the noise equivalent circuit for noise analysis. The noise equivalent to the input is given by Expression (2) as follows: The paper is structured as follows. The section 2 mainly focuses on circuit signal analysis including but not only input impedance and gain analysis. How do conventional structured small-signal analysis and matching devices affect input matching and noise figure. Section 3 introduces the proposed wideband LNA and the de66 J. Liu et al.; Informacije Midem, Vol. 55, No. 1(2025), 65 – 72  1 g   m2 2  (2) Vn2,in  4kT    g m1 g m1  Figure 2(a): Common source stage noise equivalent circuit. Here k is Boltzmann’s constant, T is the temperature and is the noise factor of the MOSFET. By observing Expression 2, it is not difficult to find that only the transconductance of gm1 is small to achieve relatively low noise, The expression for g is given by (3) as follows: g m  2 I  cox Figure 3(a): Input equivalent circuit of the LNA first stage. W Vgs  Vth  (3) L Here are all the equivalent resistances seen by the node in Figure. 3(a), Cgs1and Cgs2 are the MOSEFET gatesource parasitic capacitors of M1 and M2, respectively. Figure. 3(b) is the equivalent circuit of the first stage to analyze the gain of the first stage circuit, whose gain can be given by the following expression (5) by calculation. Through expression (3), it can be proved that gm will become smaller when the current decreases, and through expression (2), it is not difficult to find that the noise will become larger, which means that too small current will bring relatively large noise. Here μ and Cox are the mobility and gate oxide capacitance of the MOSFET, Vgs and Vth are the gate-source voltage and threshold volt- 2 Vout 1  g m R1  s L1 1  g m1 R1  Av1   Vin 1  s 2 L1 1  sR1   W age of the MOSFET and L is the aspect ratio usually  (5) determined by the designer. The first stage of this paper adopts the complementary common source stage and the following is the principle analysis. Figure. 2(b) shows the first level circuit schematic diagram and Figure. 3(a) is the calculation of its input equivalent circuit used as the input impedance. Figure 3(b): The first-stage small-signal equivalent circuit is used for gain analysis. In order to maximize the transmission power of the receiving antenna, the LNA needs to design 50-ohm impedance matching. Figure. 4(a) shows the process of impedance matching. The matching process can be clearly seen from the Smith circle diagram. When the capacitor C1 is added, the radius of the impedance circle is continuously reduced, as shown by the blue arrow in Figure. 4(a). When the inductor L1 is added, the impedance curve is close to the center of the 50-ohm point circle, as shown by the green curve in the figure. The final circuit input impedance matching is shown by the red curve in the figure, achieving a good input matching. Figure 2(b): The first level of a circuit schematic. The proposed of the LNA input impedance of the small-signal equivalent circuit according to Figure. 3(a) can be proved by Expression 3 as follows: Z in  s 2 R1C gs1 L1  R1  s 2C1 s 3 R1C gs 2C gs1 L1  s 2 L1C gs1  sR1  C gs1  C gs 2   1 (4) 67 J. Liu et al.; Informacije Midem, Vol. 55, No. 1(2025), 65 – 72 source voltage of M4 to change. Where to control the drain current. Therefore, the designed LNA achieves high gain and high linearity without passing through. Current reuse is reflected in the fact that the DC current flowing through M4 and M2 is multiplexed by M1 and M3 respectively so that no additional drive current is required to achieve lower power consumption. With the continuous development of 5G millimeterwave technology, the working frequency band is becoming higher, and the process requirements are also increasing. This demands MOSFETs with a higher cutoff frequency (ft), faster speeds, and greater carrier mobility. After comprehensive consideration, this paper uses 65 nm CMOS technology to design a two-stage LNA applied to ultra-wide system, as shown in Figure. 4(b). The first stage uses a complementary common source stage which has a higher gain than the traditional common source stage. Because the first stage uses a feedback resistor to reduce the gain sensitivity, at the same time, it matched the noise with L1 to reduce the noise of the first stage, the second stage still uses a high gain cascode stage to improve the gain. The cascode stage not only has high gain but also has excellent inputoutput isolation characteristics which improve the isolation performance of the circuit. In essence, excellent isolation is achieved by negative feedback. When the output of M4 fluctuates, it will also produce the same fluctuation at its source, which will cause the gate- The wideband matching is not only reflected in the input impedance matching, but also in the frequency band of interest to avoid the attenuation of gain. In this paper, an inductor L2 is added between the two stages. Using series inductive peaking can prevent the bandwidth degradation caused by the parasitic capacitor Cgs3, which is brought about by the large transistor M3. By selecting a suitable inductance value for L2 and resonating with the parasitic capacitance of the M3 transistor, the high-frequency gain can be improved, and the bandwidth can be expanded. At the same time, the noise matching with the second stage can be realized to ensure the low noise characteristics of the LNA. Figure. 5 (a) shows that the LNA designed in this paper simultaneously achieves high and flat power gain and excellent noise characteristics within the frequency band of interest. In order to verify the effect of interstage inductance L2, Figure 5(b) shows the results with and without series inductive peaking. It can be seen from Figure 5(b) that, with the series inductive peaking, the gain at the higher frequency increases from 12.4 dB to 23 dB, and the overall increase is nearly 11 dB. When there is no interstage inductance L2, the gain will be greatly reduced in the high frequency part, which is the result we do not want to see. Therefore, the final choice of L2 is equal to 2 nH. The former inductor L3 and capacitor C2 are designed to resonate with the parasitic capacitance of the leakage end of M4 to achieve output matching, while the latter is a direct isolating capacitor to avoid the current of VDD flowing to the output end of the amplifier. Figure 4(b): The Schematic of the proposed UWB LNA. Figure 5(a): Verification of high and flat maximum gain and excellent noise characteristics in the frequency band of Interest. Figure 4(a): Smith Chart of impedance matching process. 3 Circuit design 68 J. Liu et al.; Informacije Midem, Vol. 55, No. 1(2025), 65 – 72 under PVT conditions are illustrated in Figure. 7(a). The peak gain of 27 dB demonstrates exceptional performance compared to other published papers [11-16], while maintaining excellent S21 gain flatness across the entire UWB range with a minimal fluctuation range of only 1 dB. This characteristic enables effective amplification of in-band RF signals. Furthermore, even under the worst process angle (ss), it achieves a high gain ranging from 14-20 dB. Figure 5(b): Comparison of simulation results of with or without inducer. 4 Performance summary The proposed UWB LNA design has been implemented in 65 nm CMOS process, verified in Cadence Virtuoso p l atform, post-layout simulation of parasitic parameters extracted by Cadence Calibre, and imitation of netlist after import in Cadence Virtuoso, Figure. 6(a) shows the layout of the proposed LNA. Figure 6(b): Simulated S11. Figure 7(a): Simulated S21. The simulation curve of input-output isolation under PVT is depicted in Figure. 7(b). The reverse isolation exhibits a gradual increase across the entire frequency range, yet remains below -20 dB. within the UWB band. Notably, the reverse isolation index remains consistent across all three corners, indicating excellent performance of the UWB LN. Figure. 8(a) shows the noise characteristics of the proposed LNA. In the communication system, the LNA needs to deal with the energy from the antenna, so the output signal of the LNA is required to have a high enough signal-to-noise ratio NF to measure its performance. The proposed LNA exhibits an amazing 2 dB NF and achieves lower than 4 dB. NF over the entire frequency band even in the worst case, which is a very excellent result. The simulation results in Figure. 8(b) depict the third-order intermodulation Figure 6(a): Layout of the proposed LNA Figure. 6(b) shows the simulation results of the reflection coefficient of input return loss under different temperatures, different voltages and different process angles (PVT). The reflection coefficient of ff process Angle is the smallest and S11 is less than -10 dB in almost the whole frequency band. The minimum value of S11 is about -12 dB. Meet the impedance matching requirements. The simulation results of the UWB LNA 69 J. Liu et al.; Informacije Midem, Vol. 55, No. 1(2025), 65 – 72 One value is 61 m and values are only 180 m, reflecting that the random mismatch of the device has very little influence on the LNA NF. The simulation results of S11 in Figure. 9(b) demonstrate a small mismatch ratio when running 200 points, primarily distributed around -8 dB. The value of one is 470 m, and the value of mismatch 1.4, indicating that the random device mismatch has a relatively negligible impact on the S11 performance of LNA. Its deviation remains within an acceptable range without affecting the overall UWB performance. Figure. 10(a) shows the simulated mismatch results for S21 gain. In the case of running 200 points, the mismatch of S12 is relatively small, with a value of 1, as the mismatch mainly concentrates on the gain greater than 23 dB. Even if there is a little mismatch, it is only a few points that have a minimal impact on the performance of the LNA. The minimum gain of the mismatched LNA is also greater than 20 dB, indicating that the LNA has excellent performance. curve, which serves as an indicator of the linearity of UWB. Distortion arises from poor linearity in the output signal of an LNA, consequently leading to subpar performance of the entire communication system. In comparison with other research papers, this paper LNA exhibits exceptional linearity at approximately -10.78 dBm [17-19]. Figure 7(b): Simulated S21. Figure 9(a): Monte Carlo results of NF Figure 8(a): Simulated NF. Figure 9(b): Monte Carlo results of S11 Figure 8(b): IIP3 of the proposed LNA Figure. 9（a）shows the simulation results of the mismatch of NF. In the case of running 200 points, the mismatch of NF is very small and can almost be ignored. 70 J. Liu et al.; Informacije Midem, Vol. 55, No. 1(2025), 65 – 72 7 References 1. 2. Figure 10(a): Monte Carlo results of S21. 3. 5 Conclusion This article comprehensively describes the detailed analysis and design ideas of an LNA that adopts a twostage structure implemented on 65 nm CMOS technology. The proposed two-stage LNA uses inter-stage matching to achieve broadband matching and high gain. Most importantly, noise matching is achieved to obtain a low NF, and at the same time, the currentreused technology is used to effectively reduce power consumption. Finally, the Monte Carlo and processcorner simulations confirm that the proposed design is suitable for the UWB system. The proposed LNA achieves a peak gain of 24.7 dB, with its 3- dB bandwidth ranging from 5 to 12 GHz and an NF of 2.8 dB at 11 GHz, while consuming 6.07 mW of DC power. The core area of the LNA is optimized to only 0.292 mm2. 4. 5. 6. 6 Conflict of interest The authors declared no potential conflict of interest with respect to the research, authorship, and publication of this article. 7. J. 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Arrived: 09. 08. 2025 Accepted: 19.1 1. 2025 72 Call for papers Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 1(2025), 73 – 73 MIDEM 2025 60th INTERNATIONAL CONFERENCE ON MICROELECTRONICS, DEVICES AND MATERIALS WITH THE WORKSHOP ON ENERGY MANAGEMENT AND RENEWABLE ENERGY SOURCES October 1st – October 3rd, 2025 Ljubljana, Slovenia Announcement and Call for Papers Chairs: Prof. Dr. Barbara Malič Dr. Andraž Bradeško IMPORTANT DATES Abstract submission deadline: May 16, 2025 Acceptance notification: June 30, 2025 Full paper submission deadline: August 29, 2025 Invited and accepted papers will be published in the Conference Proceedings. Detailed and updated information about the MIDEM Conferences, as well as instructions for paper preparation, can be found on: http://www.midem-drustvo.si/ GENERAL INFORMATION The 60th International Conference on Microelectronics, Devices and Materials with the Workshop on Energy Management and Renewable Energy Sources continues the successful tradition of annual international conferences organized by the MIDEM Society, the Society for Microelectronics, Electronic Components and Materials. The conference will be held in Ljubljana, Slovenia, from OCTOBER 1st – 3rd, 2025. Topics of interest include but are not limited to: • Energy management and renewable energy sources (workshop topic), • Novel monolithic and hybrid circuit processing techniques, • New device and circuit design, • Process and device modelling, • Semiconductor physics, • Sensors and actuators, • Electromechanical devices, microsystems and nanosystems, • Electronic and photonic chips, • Nanoelectronics, • Optoelectronics, • Photovoltaics, • Electronic materials science and technology, • New electronic materials and applications, • Materials characterization techniques, • Reliability and failure analysis, • Education in microelectronics, devices and materials. ORGANIZER: MIDEM Society - Society for Microelectronics, Electronic Components and Materials, Slovenia PARTNERS: UL FE, IJS, IMAPS - Slovenia Chapter, IEEE - Slovenia Section, Slovenian Competence Center on Chips and Semiconductor Technologies 73 Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Honorary president: Prof. Dr. Marko Topič, UL, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Janez Krč, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Iztok Šorli, Mikroiks d.o.o., Ljubljana, Slovenia Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Prof. Dr. Slavko Bernik, Jožef Stefan Institute, Slovenia Assoc. Prof. Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Đonlagić, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Mag. Leopold Knez, Iskra TELA, d.d., Ljubljana, Slovenia Mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Asst. Prof. Dr. Gregor Primc, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Asst. Prof. Dr. Hana Uršič Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Supervisory Board | Nadzorni odbor Dr. Drago Resnik, retired, Slovenia Prof. Dr. Franc Smole, retired, Slovenia Prof. Dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Court of honour | Častno razsodišče Darko Belavič, retired, Slovenia Prof. Dr. Danjela Kuščer Hrovatin, Jožef Stefan Institute, Ljubljana Dr. Hana Uršič Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si