Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), June 2018 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 48, številka 2(2018), Junij 2018 ISSN 0352-9045 70 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 2-2018 Journal of Microelectronics, Electronic Components and Materials VOLUME 48, NO. 2(166), LJUBLJANA, JUNE 2018 | LETNIK 48, NO. 2(166), LJUBLJANA, JUNIJ 2018 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2018. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2018. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Malgorzata Jakubowska, Warsaw University of Technology, Poland Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Đonlagić, University of Maribor, Faculty of Elec. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana 71 Content | Vsebina 73 85 97 115 121 129 Journal of Microelectronics, Electronic Components and Materials vol. 48, No. 2(2018) Izvirni znanstveni članki A. Marzuki: CMOS RGB barvni sensor s kompenzacijskim vezjem temnega toka B. Skočir, G. Papa, A. Biasizzo: Multi-hop komunikacija v Bluetooth Low Energy ad-hoc brezžičnem senzorskem omrežju M. Faseehuddin, J. Sampe, S. Shireen, S. H. Md Ali: Izgubni in brezizgubni induktivni simulator ter univerzalen filter z z novim prilagodljivim aktivnim blokom G. Wang, J. Liu, S. Xu, J. Mo, Z. Wang, F. Yu: Načrtovanje širokopasovnega LNA z aktivnim napajanjem na osnovi negativne tehnike S. A. Tuncer: Generator naključnih števil v realnem času z dvo- jno funkcijo nekloniranja na osnovi obročnega oscilatorja Doktorske disertacije na področju mikroelektron- ike, elektronskih sestavnih delov in materialov v Sloveniji v letu 2017 Naslovnica: Ukazna in podatkovna pot v drevesni topologiji omrežja. (Skočir et al.) Original scientific papers A. Marzuki: CMOS RGB Colour Sensor with a Dark Current Compensation Circuit B. Skočir, G. Papa, A. Biasizzo: Multi-hop communication in Bluetooth Low Energy ad-hoc wireless sensor network M. Faseehuddin, J. Sampe, S. Shireen, S. H. Md Ali: Lossy and Lossless Inductance Simulators and Universal Filters Employing a New Versatile Active Block G. Wang, J. Liu, S. Xu, J. Mo, Z. Wang, F. Yu: The Design of Broadband LNA with Active Biasing based on Negative Technique S. A. Tuncer: Real-Time Random Number Generation with Ring Oscillator Based Double Physically Unclonable Function Doctoral theses on Microelectronics, Electronic Components and Materials in Slovenia in 2017 Front page: Command and data path in tree topology network. (Skočir et al.) 72 73 Original scientific paper  MIDEM Society CMOS RGB Colour Sensor with a Dark Current Compensation Circuit Arjuna Marzuki Universiti Sains Malaysia, School of Electrical and Electronic Engineering, Malaysia Abstract: This article presents the design and development of a Red, Green, Blue (RGB) Colour Sensor with a dark current compensation circuit. The presented design employs a new approach to eliminate the conventional low pass filter, where it is normally required to integrate the pulsating signal. This is accomplished by employing switched capacitor circuit techniques. A covered photodiode is used to derive a proportional to dark current common mode voltage or compensated common mode voltage, Vdvcm. The measured performance of the sensor when it was used as an optical feedback solution for a light emitting diode (LED) backlighting system was very promising. The colour point accuracy, ' 'u v∆ = 0.002, while colour point drift over temperature was less than 0.008 at 50 °C. The maximum reduction of 36 mV output voltage error was observed when the Vdvcm was applied to the single to differential circuit. The overall power consumption of the fabricated sensor was 7.8 mW. The whole sensor design was implemented in 0.35 μm CMOS technology. The Vdvcm concept can be applied to other similar circuitry such as temperature-sensitive circuits. Keywords: Integrated Circuit; RGB Sensor; Current Integration; dark current cancellation CMOS RGB barvni sensor s kompenzacijskim vezjem temnega toka Izvleček: Članek predstavlja obliko in razvoj RGB senzorja s kompenzacijskim vezjem temnega toka. Predstavljen dizajn, za eliminacijo pulzirajočega signala ne uporablja klasični nizkopasovni filter temveč tehniko preklopnega kapacitivnega vezja. Za določitev razmerja sofazne napetosti temnega toka ali kompenzirane sofazne napetosti je uporabljena fotofioda. Merjene lastnosti senzorja v uporabi povratne informacije LED sistema so zelo vzpodbudne. Natančnost barvne točke pri temperaturnem driftu pod 0.008 pri 50 °C je ' 'u v∆ = 0.002. Največje zmanjšanje izhodne napetosti je 36 mV. Senzor je izveden v 0.35 μm CMOS tehnologiji. Ključne besede: integrirana vezja; RGB senzor; izničenje temnega * Corresponding Author’s e-mail: eemarzuki@usm.my Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), 73 – 84 1 Introduction There are numerous applications of colour sensors in consumer application industries. Such applications are reflective colour sensing [1] and an optical feedback for RGB light source [2-4]. The latter application requires the system to maintain a given colour of the LEDs over temperature and time. Selecting the colour can be ac- complished by specifying the colour coordinates in the CIE colour space. This is achieved via colour coordinate feedback (CCFB) technique. An example of optical feedback solution [2] required a low pass filter (LPF), a gain stage, an analogue digital converter (ADC) and external RGB sensor. The solution is therefore unacceptable for small or portable devices which require a small footprint [3-5]. The LPF was used to average out pulse width modulation (PWM) voltage can have an effect on the response time of the total solution. Several digital colour sensors which employ light to frequency technique [6, 7] require an advanced processor such as DSP or PC to measure or calculate the frequency [8, 9]. Dark current can be caused mainly by the random movement of carriers (solely on carrier concentration) and the thermal generation combination. Dark current can affect the dynamic range [10, 11] of CMOS image sensors. It is also a subject of study in colour sensors [6] and photodetectors [12]. 74 A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 Reduction of dark current can increase the dynamic range of colour sensors [7]. Two approaches to re- duce the dark current, namely through photodetector (photogate) physical modification [13] and secondly through electronic correction, are normally employed in a low dark current colour sensor. The latter approach was a circuit-based approach and it required a dummy photodetector. The real photo current is a result of the subtraction of active current from the photodetector and dark current from the shielded dummy photode- tector [7, 14]. The photogate technique [13] required different biasing voltages; therefore, it is quite difficult to be implemented in small colour sensor design. The problem with the shielded dummy approach is that the biased voltage of the shielded photodetector dif- fers from the one applied to the main photodetector. Recent work [15] had improved the work based on the subtraction technique [14]. An integration capacitor is usually used to store voltage, so the leakage due to switching and others has to be reduced in order not to affect the voltage stored in the integration capacitor. Another approach which was based on ‘stored’ volt- age for biasing the current mirror or current source had been developed. This work was based on current steering of dark current to the ground instead of to the output [16]. This work however was prone to device mismatch. Recent works [17,-19] which are based on the integrat- ing current concept has managed to integrate ADC, RGB sensors and the function of the low pass filter (LPF) and gain stage. The works had eliminated the conven- tional LPF by employing an integration capacitor (Cint). The gain stage was also eliminated by using selectable capacitors and photodiode sizes, but the gain function remains the same. Nevertheless, the works [17], [19] did not employ a dark current cancellation circuit and the measured dark current is within 1 LSB [19]). The dark current limits the signal to noise ratio for sensors oper- ating at high temperature or under low light conditions where the integration time is long. The objective of this work was to solve the dark current issue in the recent CMOS colour or RGB sensor [17, 19] and improve dark current cancellation work [18]. The solution was not obvious, as either the differential tran- simpedance amplifier (TIA) or zero biasing technique cannot be employed in the design. The dark current cannot be cancelled at the digital level due to different sampling or integration time issues. An example of the application such as backlighting will also be presented. This paper is organized as follows. Section 2 discusses the design aspect. It covers backlighting application, concepts, control signals, RGB Photodiode, Integrator (Switches and Capacitor array), dark current cancel- lation, a single to differential circuit and sample/hold (S/H) buffer amplifier and process, voltage and temper- ature (PVT) corners analysis. Sensor development and measurement results are discussed in section 3. This paper is concluded in the conclusion section. 2 Design 2.1 Backlighting application Figure 1: A typical Block diagram LED backlighting so- lution using optical feedback [2, 20] The block diagram of the optical feedback system em- ployed in RGB LEDs backlighting is shown in Figure 1. The general flow is as follows: The RGB sensor which is a colour sensor measures the intensity of each colour produced by the LED module. The low-pass filter (LPF) (in this solution only one low pass filter is used) averages the sensor voltage output over time before transferring it to an adjustable gain stage (the objective is to obtain the maximum analogue to digital converter (ADC) code when the LED is at full brightness). The ADC digitizes the averaged sensor voltage and the feedback control- ler (inside the FPGA) adjusts the PWM output according to the deviation of the measured sensor data from the reference values. The PWM signals are used to drive the external LED drivers, which control the on-time duration of the red, green and blue LEDs. The on-time duration is continually adjusted in real time to match the light out- put from the LED array to the RGB ratio needed to main- tain the specified colour [2]. This measured condition- digitize-adjust is a free running process. A more detailed explanation can be found in Lim et al. [2] 2.2 Colour sensor concept overview The proposed design as shown in Figure 2 is an im- proved version based on previous works [17 – 19]. It 75 receives signals from the photodiode array, a program- mable setting can be applied to the signals, and it then converts the resulting differential voltage signal into digital words. The programmable settings are integra- tion period, capacitor size and photodiode active area size. The design can sense pulsating light without the need of a filter. This is because the design works on the principle of integrating photodiode current. Five major blocks are shown in Figure 2: test multi- plexer (TEST_MUX), REFERENCE, ADC, TIMING GENERA- TOR and integrator and sample & hold (INTEG S&H). The TIMING GENERATOR is used to derive the required control signals (see Figure 3). INTGR and PRECHARGE SIGNALS are the inputs to the TIMING GENERATOR. The INTEG S&H block is the point of interest and will be explained in detail in this paper. Photomux shown in Figure 2 is a simplified idea; its function is to select the photodiode active area and channel or colour. Each switch for CHSEL [2:0] consists of three switches for col- our selection (RGB). The integration of photo current is accomplished by using an array of capacitors, called integration capacitor, Cint, so together with switches (transistor symbol), it forms an integrator. Figure 2: Block Diagram of a novel RGB colour sensor Table 1 describes the description of the I/O of the pro- posed design. Table 1: Pin List Name Type Description VDDA P Analog supply. Nominal 2.6V. VSSA P Analog ground. PDASZ[3:0] DI Photodiode size CAPSZ[7:0] DI Capacitor select. CHSEL[2:0] DI Channel select. INTGR DI Integrating control signal PRECHARGE DI Precharge control signal EN_SINGLE DI Select 7 bit mode (active high) CLK_ADC DI ADC clock ADC_PD DI ADC power down pin (active high) AMP_PD DI Amplifier power down (active high) BG_PD DI Bandgap power down (active high) DARKVCM_SEL DI Select normal Vcm (active high) ATESTSEL[8:0] DI Analog test control signal (TSTMUX) Photodiode pins ANA Photodiode connection ANA1 ANA TEST PIN1 ANA0 ANA TEST PIN2. ADCDATAOUT[7:0] D0 ADC data out The simplified integrator output, Vin is: int int arg C TI VV egrationphotodiodeeprechin × −= (1) where Vprecharge is the voltage across integration ca- pacitor, Cint. The voltage is provided by the REFERENCE block. Iphotodiode is the photocurrent and Tintegration is the in- tegration time. From equation (1), when the light incident on the pho- todiode is PWM light, the integration phase (see Figure 3) is synchronized to a multiple of the PWM periods, then the voltage Vin is inversely proportional to the PWM duty cycle. A single to differential amplifier (sig- diff ) is then used to produce the differential voltages for the differential input ADC; these values are later sampled by the S/H amplifier. In the single to differen- tial circuit (sigdiff), a compensated common mode volt- age is used for dark current cancellation. The sampled values are held for analogue to digital conversion. At the same time, the Cint is charged back to the Vprecharge value. Details about integrator and sample hold (INTEG S&H) are discussed in Sections 2.5, 2.6, 2.7 and 2.8. A pipeline ADC with 8-bit resolution is used for analogue to digital conversion. The ADC can receive ± 1.2 V, i.e. differential input voltages with the nominal voltage (common mode voltage) of 1.2 V. The relationship of voltages and the ADC output is described in equation (2): A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 76 256 2 )( (DEC)Output ADC ×        + = ref ref V Vinp-inm (2) where inp is the positive input of the ADC, inm is the negative input of the ADC and Vref is the reference volt- age. For output of 0 DEC, the differential voltage is -1.2 V (e.g. inp = 0. 6 V, inm = 1.8 V) while for output 256 DEC (28), the differential voltage is 1.2 V. Both equations (1) and (2) show that the concept is ca- pable of integrating several functions (gain stage and LPF) into a single silicon. The REFERENCE block is used to generate bias voltages (e.g. VBG or Vcm) and bias cur- rents for internal usage such as voltage to precharge the Cint. The design also includes extensive routing for testability. Each block’s input can be overridden and each block’s output can be measured. This allows an ef- ficient means of debugging the signal chain within the design should the need arise. 2.3. Control signal Figure 3 shows the simplified proposed control signal for the INTEG S&H block. ‘pr’ is the precharge control signal and ‘phi2’ is the signal to control the integrator switch (see Figure 5). ‘phi0’ and ‘phi1’ are signals to con- trol the S/H buffer amplifier (see Figure 9). These signals are depicted in Figure 2. Figure 3: Control signals 2.4 RGB Photodiode Figure 4 shows the RGB photodiodes. The RGB photodi- odes are N-Well type photodiodes with colour photo array (CFA) filters [21], [22]. The RGB filters are arranged in a common centroid pattern. Photodiode sizes can be selected from ¼, ½, ¾, or full size. Light is converted to photocurrent by these photodiodes. An interface cir- cuit called PhotoMux is designed to select photodiode sizes and channels (RGB). The total size of the RGB pho- todiodes is 400 μm × 400 μm. Figure 4: RGB Photodiodes 2.5 Integrator (Switches and capacitor array) Figure 5: Switches and Capacitor Array (Cint) The integrator circuit in Figure 5 employs a capacitor array of 4x8 pF and switches. The value of the capaci- tance can be selected through the Capsel register. The capacitor block is pre-charged to ~1.8 V (Vprecharge) when the ‘pr’ signal is high. Before the ‘phi2’ signal is high, the ‘pr’ signal is first low. The ‘phi2’ signal is high when integration is selected. During the integration period, 1 2 Capacitor C1 VSSA VSSA VDDA Capsel <7:0> prb pr Vprecharge Iphotodiode Vin phi2phi2 nphi2 nphi2 A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 77 the pre-charged capacitor voltage starts to decrease as described by equation (1). The capacitor array together with photodiode sizes can be used to adjust the re- quired Vin. This is similar to the gain stage function as in a prior work [2]. Figure 6: Integrator Output (Vin) Simulation at slow, fast and nominal corners Figure 6 shows the integrator output simulation re- sults; the simulated slope is 3824 V/s. The slope can be calculated based on equation (3): dT dVCI = (3) where I is the photodiode current, C represents the in- tegration capacitor value and dV/dT is the slope. When all capacitors are selected (32 pF), the photodiode cur- rent (I) is 125 nA and using equation (3), the slope or dV/dT = 3906.25 V/s. The calculated slope is not very different compared to the simulated slope as shown in Figure 6. It is also shown that the capacitor corners (slow = minimum capacitance, fast = maximum capaci- tance) affect the slope more than transistor corners. 2.6 Dark current cancellation circuit concept Figure 7 shows the dark current cancellation concept. Two operational amplifiers are used to create a single to differential circuit. The operational amplifier is based on the differential folded cascode amplifier, the con- cept of which is similar to a reported work [23]. Assum- ing no current into the negative terminal of the opera- tional amplifier and Vcm is selected (DARKVCM_SEL = HI), current flowing into resistor, R is: R VV R VV cmoutnoutpcm −= − (4) where Vcm is common mode voltage, Voutp is voltage of positive output, Voutn is voltage of negative output and R is resistor. Re-arranging equation (4), Voutp =2Vcm–Voutn, the differ- ential output voltage, Vdiff = Voutp–Voutn, since Voutn = Vin, Vdiff is: grcmoutncmdiff VVVVV int2222 −=−= (5) From equation (5), when Vcm is Vdvcm, theoretically the differential output voltage would be without a dark current element. This is firstly achieved by precharge an integration capacitor in the dark current circuit with Vcm. The stored voltage at the integration capacitor is discharged due to solely dark current. This voltage is now can be called Vdvcm. When DARKVCM_SEL is 0 V, the Vdvcm is applied to the operational amplifier and the dark current element from the uncovered photodiode can be eliminated. It is also easy to conclude that for the worst offset scenario of the single to differential ampli- fiers is: groffsetcmoffsetdiff VVVV int242 −+=− (6) Figure 7: Dark Current Cancellation approach Figure 8: Non-Inverting Output (outn) and Inverting Output (outp) The output of the non-inverting amplifier (outn = inm or input of ADC) will be cut-off at 100 mV as shown in Figure 8, which is due to the amplifier limitation. From equation (2), this corresponds to a maximum digital sensor output of 245 DEC when outp (equal to inp) is maintained at 1.2 V (a pseudo differential signal to ADC). A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 78 2.7 S/H Buffer amplifiers An S/H buffer amplifier as shown in Figure 9 consists of an operational amplifier (Figure 10), two capacitors and switches. Bottom plate sampling is employed in the de- sign in order to reduce the substrate noise [24]. Figure 9: S/H buffer amplifier The S/H buffer amplifier is used prior to the ADC block due to the ADC that is used in the colour sensor design is a free running ADC. Two capacitors with a value of 100 fF are used as the S/H capacitors. This value is opti- mized for low kT/C noise. During the sampling (‘phi0’ is low) of the differential voltages, the output of the operational amplifier (as shown Figure 10) is shorted to its input and the DC voltage is set at Vcm by a common mode feedback cir- cuit [25] in the operational amplifier. During the hold- ing phase (phi1 is low) the output is shorted to the left/ bottom plate of the S/H capacitor. By employing the common mode feedback circuit (CMFB), the output of this S/H buffer amplifier is always re-centred at Vcm. The CMFB employs the capacitive sensing technique. Two capacitors are used to average out the differential out- put voltage, the averaged output is connected to the CMFB amplifier input, the CMFB amplifier compares it with Vcm (connected to Vref), and adjusts the biasing cur- rent until the averaged output is equal to Vcm. ibias is supplied by the bandgap circuit. Vsample is connected to phi1 while Vhold is connected to ‘phi0’. Figure 11 shows S/H buffer amplifier outputs during sampling and holding periods. During the sampling, both outputs are tied to Vcm and only during the hold- outp outn phi1 phi1 phi0 phi0 phi1 phi1 inp inm capacitor capacitor Vcmp Vcmn V h o ld V sa m p le V sa m p le Vcmp Vcmn Vref D 1 D 2D1 D2 out+ out- out+out- In+ In- ibias VDDA VSSA VSSA Figure 10: Differential input Operational Amplifier with the CMFB Figure 11: S/H buffer amplifier output at fast corner and vs. temperature A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 79 ing phase are the outputs connected to the sampled signals. Figure 11 also depicts the differential signal at an output of 1.19 V which is achieved whilst the com- mon mode voltage is 1.19 V (Vcm). The S/H buffer am- plifier seems immune to temperature variation (-40 oC, 22.5 oC, 85oC). 2.8 Process, voltage and temperature (PVT) corners analysis Table 2 shows the summary of the PVT for the INTEG S& H block. Table 3 shows the zero code calculation of pre-layout based on the output voltages of Single to differential amplifier and voltage references. The offset voltage of the amplifier is three times of PVT results as shown in Table 2. Table 3: Zero Code Calculation based on Single to Dif- ferential Output Parameters Nom Min Max VREFM (V) 0.602 0.57 0.619 Voffset (V) 0.006 0.006 0.006 VREFP (V) 1.750 1.727 1.773 Vcm (V) 1.167 1.151 1.178 Voutp (V) 0.602 0.593 0.601 Voutn (V) 1.744 1.721 1.767 Vref (VREFP- VREFM) 1.148 1.157 1.154 Vdiff-offset (V) -1.142 -1.128 -1.166 Zero code (LSB) ~0 4 -2 Note: Equation 6 is used to calculate the Vdiff-offset. Equa- tion 2 is used to calculate the zero code. Table 4 shows the summary of the PVT zero code (pho- todiode current is zero) of post layout (extracted) com- plete design. At the PVT Nom, the design offset is at least 2 LSB. These offsets can be eliminated at the digi- tal level. Table 4: Zero Code Post layout Simulation of Complete Design Parameter PVT Min PVT Nom PVT Max Integrator Out- put (V) 1.804 1.770 1.830 Output of single to differential amplifier (V) 1.175 1.179 1.147 Output of S/H buffer (V) 1.171 1.176 1.142 Non-overlap- ping-Clock, ph0- ph1 (ns) 7.85 4.15 2.94 Clock Delay, ph2-ph1 (ns) 2.83 0.9 1.06 Output ADC code 00000011 00000010 00001000 Note: Temp= -40, 27, 85oC. FET= Fast, Slow, Nom. Resistor/Ca- pacitor =MIN, NOM, MAX. VDD= 2.5, 2.6, 3.6 V. PVT Min = Slow, MAX, 2.5 V and 85oC corners. PVT Nom = Nom, NOM, 2.6 V, 27oC. PVT Max = Fast, MIN, 3.6 V and -40oC. 3 Sensor development and measurement results 3.1 CMOS Sensor implementation Figure 12a shows the floor plan of the RGB colour sen- sor with a dark current cancellation block diagram. A Non-Overlap Block (TIMING GENERATOR) is used to generate ‘phi0’ and ‘phi1’ or ‘phi2’. Biasing Circuitries (REFERENCE block) are used to provide necessary ref- erences such as ibias, bandgap voltage (VBG), current sources or sinks to the operational amplifiers and the ADC. VBG is a voltage reference based on bandgap voltage circuitry. The common mode voltage, Vcm, is based on this voltage reference. The total size of the basic core layout is 800 μm x 400 μm (without the RGB Table 2: PVT Simulation of Sub-Blocks of INTEG S&H block Parameter PVT Min PVT Nom PVT Max Units Comments Integrator output voltage 3415 3824 4349 dV/dt Process variation Single to differential output voltage +2mV From nominal differential signal S&Hold buffer output voltage 3mV Worst with Vdd variation Note: Temp= -40, 27, 85oC. FET= Fast, Slow, Nom. Resistor/Capacitor =MIN, NOM, MAX. VDD= 2.5, 2.6, 3.6 V. PVT Min = Slow, MAX, 2.5 V, 85oC corners. PVT Nom = Nom, NOM, 2.6 V, 27oC. PVT Max = Fast, MIN, 3.6 V, -40oC. A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 80 photodiodes). Figure 12b shows the final layout of a RGB colour sensor with the dark current cancellation layout. TEST_MUX is not shown in the Figure 12a and Figure 12b. Decoupling capacitors, as shown in Fig- ure 12b, are used to reduce noise from VDD. Figure 12c shows a picture of the fabricated sensor; all blocks or circuits (as in Figure 2) except the RGB photodiode are covered with a metal layer to protect them from light. Figure 12: (a) Floor Plan of the novel CMOS RGB, (b) Layout of the implemented design, (c) Microphoto- graph of the novel CMOS RGB colour sensor with dark current cancellation Figure 13 shows the complete prototype of the sensor with I/O bondpads. The prototype is I/O pad limited since the size is limited by the size of the I/O pad struc- ture. 3.2 Test boards Figure 14a shows the test system architecture for the sensor, while Figure 14a and 14b are the DUT board and Test Board respectively. The sensor was packaged in clear 48 pin TSOP and soldered onto the DUT board. Six voltage level shifter ICs (MAX 3001E) were used to connect the sensor and the PC/FPGA. These ICs were soldered onto the Test Board. Figure 14: (a) Test System Architecture, (b) PCB drawing of the DUT board, (c) PCB drawing of the Test board 3.3 Measured colour sensor results Table 5 shows the light intensity vs photodiode current. Table 5: Light intensity vs photocurrent Light intensity (lux) Current (nA) 0 0.4 265 14 528 29 762 40 1049 55 1324 63 1583 78 1822 90 Note: Test condition: Red channel, VDD=2.6V, Integra- tion time=150 μs, Photodiode size=400 μmx400 μm, room temp, Cint =32 pFFigure 13: Microphotograph of the prototype CMOS RGB colour sensor with dark current cancellation and I/O pads A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 81 Table 6 shows the designed Cint value versus measured value. The value of smaller capacitors (4 pF and 8 pF), as shown in Table 6, were difficult to be realized, which could be due to a parasitic component associated with selection switches. Table 6: Value of Cint Designed value (pF) Measured value (pF) 4 5.76 8 10.6 12 13.5 16 16.9 20 20.8 24 25.5 28 28.9 32 32.7 Table 7 shows the DC value of the voltage references (from biasing circuitries), VBG, VREFP, VREFM and to- tal current consumption, ICC of the sensor across VDD (power supply). The measured current consumption is very close to the simulated current consumption. Table 7: Analog/bias parameters Simulation Measurement VDD(V) VDD(V)   2.6 2.5 2.6 3.3 VBG(V) 1.167 1.171 1.183 1.171 VREFP(V) 1.750 1.757 1.76 1.75 VREFM(V) 0.602 0.624 0.63 0.617 ICC(mA) 2.856 ~2 ~3 ~4 Based on Table 7, at nominal, the Vcm (which is VBG) is 1.183 V and Vinm (VREFP) is 1.76 V, and VREFP and VREFM are generated for ADC references. From Figure 7, Vinp (depicted as Voutp in the figure) is 0.624 V. Thus, using equation (6) and equation (2), the sensor offset is zero. This is agreed as shown in Table 3. Figure 15 shows the ADC response or settling time (adacdataout<4>) which is 46 ns. The clock is at 4 MHz. The response indicates that the maximum ADC output frequency is approximately 21 MHz. The results in Table 8 – Table 10 show that the sensor results agree with equations (1)-(3); hence, this has proven that the concept discussed in section 2.2 is fully functioning as designed. Out-Vdvcm is the sensor digital output when the Vdvcm is applied to the single to differ- ential circuit. Out-Vvcm is the sensor digital output when the Vvcm is applied to the single to differential circuit. Table 8 also shows that the measured sensor offset is similar to the post-layout simulation sensor offset, i.e. when Vdvcm is applied to the single to differential circuit. Table 8: Digital CMOS sensor output vs integration time Integration time (unit)   0 4 8 12 15 Out-Vdvcm 1 12 23 32 40 Out-Vcm 2 13 23 34 41 Note: Integration time of 0 = 150 μs. Test condition: Red channel, VDD=2.6V, Photodiode size =100μmx400μm, Cint=32 pF, room temp, 150 lux. Vcm = VBG, Vdvcm is Vcm generated from the dark photo- diode. Table 9: Digital CMOS sensor output vs photodiode size Photodiode Size(μmxμm)   100x400 200x400 300x400 400x400 Out-Vdvcm 39 73 105 133 Out-Vcm 39 75 106 134 Note: Test condition: Red channel, VDD=2.6V, Integration time=15, Cint =32 pF, room temp, 150 lux Vcm = VBG, Vdvcm is Vcm generated from the dark photo- diode. Figure 15: ADC response A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 82 Table 9 indicates that the total integration capacitance increases when a larger photodiode is selected; how- ever, the output is still linearly associated with the size of the photodiode. Based on equation (2), and from Table 10, the biggest reduction of output voltage error is 36 mV when the compensated voltage common mode, Vdvcm, was ap- plied to the single to differential circuit and the Cint is 4 pF. This observation of dark current reduction can be verified when ¼ of the dark current value (Table 5) with equation (3), equation (6) and equation (2), the cal- culated the dark current ADC code is 4 LSB (~36 mV). Overall, it is shown that when Vdvcm was applied to the single to differential circuit, an improvement of at least 1-bit resolution is achieved. Table 10: Digital CMOS sensor output vs Cintegration Cintegration (pF)   4 8 12 16 20 24 28 32 Out-Vdvcm 118 72 51 40 33 28 24 21 Out-Vcm 122 75 53 42 33 28 25 22 Note: Test condition: Red channel, VDD=2.6V, Integration time=8, Photodiode size=100μmx400μm, room temp, 150 lux Vcm = VBG, Vdvcm is Vcm generated from the dark photo- diode. As described in Table 6, the integration capacitance at the lower end is much higher than the targeted value. This will affect the value of output when 4 pF or 8 pF is selected. Nevertheless, the output follows the trend of 1/Cint. 3.4 Colour point of backlighting application results A digital controller similar to that in Lim et al. [2] was implemented and used to configure the basic CMOS RGB sensor as an optical feedback for a PWM-based LED backlighting solution. Several units were tested at 25°C with a power supply of 2.6 V. The colour set point was at CIE x = 0.287, y = 0.296 (9000 K). It was found that the average colour accuracy, ' 'u v∆ , is 0.002 and the standard deviation was 0.0012. For colour point stability measurement, RGB LEDs with colour coordinates of Red (x,y) = (0.691, 0.309), Green (x,y) = (0.161, 0.704) and Blue (x,y) = (0.131, 0.073) were used. The R:G:B luminance ratio was 2.6 : 3.9 : 1.0 re- spectively. Figure 16a, 16b and 16c show colour drift with temper- ature (the CMOS RGB colour sensor temperatures are at -20°C, 25°C and 85°C respectively). The LED tempera- ture was varied from 25°C to 70°C. From Figure 16a, 16b and 16c, it is shown that ' 'u v∆ < 0.008 when the LED temperature is less than 50°C. Figure 16 (a): Colour point drift with temperature at 25% duty cycle PWM Figure 16 (b): Colour point drift with temperature at 50% duty cycle PWM Figure 16 (c): Colour point drift with temperature at 100% duty cycle PWM A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 83 In Table 11, the performance of the presented design is compared with that of other colour or image sensors in CMOS technology. The presented design is able to com- pletely remove dark current as described in equation (5). The work of Nahtigal and Strle [7] had achieved a very high dynamic range; however, it required a DSP to pro- duce the required RGB colour luminosity; therefore, the work was quite complex and power consuming for port- able application. The measured dynamic range (DR) of the design was 90 dB which is comparable to human eye capability. Overall, the performance of the design as a colour sensor was good and comparable to others. Table 12: Published Colour sensor for backlighting ap- plication comparison   [9] [26] This work Topology Analog I-F Current Integrat- ing and ADC Technology LCD and off the shelf components CMOS CMOS 0.35 µm ' 'u v∆ 0.008 0.006 0.008 RGB RGB Color Filter Metal filter RGB Color Filter Table 12 shows the comparison of published colour sensors for backlighting application. The presented design has achieved comparable ' 'u v∆ results com- pared with several works [9], [26]. The work in Lee et al. [9] did use several off-the-shelf components, which will incur some cost and increase the size. Meanwhile, the work in Gourevitch et al. [26] required a DSP to produce the required RGB colour luminosity. The presented de- sign is a complete integrated on-chip solution with real RGB colour signal. 4 Conclusion In summary, the CMOS colour sensor with integration capacitor had eliminated the need for a low pass filter for detecting PWM light. The gain stage component was also eliminated by using selectable integrating capacitors and photodiode sizes, but the gain function remains the same. Together these techniques had also made the integration of RGB sensor possible. An ADC was integrated together with the circuits into a single silicon in order to produce digital outputs. The meas- urement results of the fabricated CMOS colour sensor with a dark current cancellation circuit had also proved that the novel dark current cancellation circuit func- tions as required. The cancellation of dark current was necessary for low value of Cint and longer integration time. The implemented CMOS colour sensor in 0.35 μm CMOS technology performed well from –20°C to 85°C as an optical feedback solution where ' 'u v∆ < 0.008 was achieved at 50°C. The implication of the research is the technique of using a compensated common mode voltage in the single to differential amplifier. This technique can be applied to other similar circuitries such as temperature- sensitive circuits, and in this case, the common mode voltage is temperature compensated rather than dark current compensated. 5 References 1. Avago Technologies, “Reflective Color Sensing with Avago Technologies ’RGB Sensor, White Pa- per”, AV02-0172EN-Mar. 22, p. 1-10, 2010. 2. K. Lim, J. C. Lee, G. Panotopulos and R. Heilbing, “Illumination and Color Management in Solid state lighting” IEEE Industry Applications Confer- ence, 41th IAS Annual Meeting, Tampa, Florida, USA, pp. 2616-2620, Oct. 2006. 3. D. G. Keithley, “Color Correcting For Ambient Light”, U.S. Patent 2008/0303918 A1, 2007. 4. S. K. Ng, K. H. Loo, Y. M. Lai and C. K. Tse, “Color control system for RGB LED with application to light sources suffering from prolonged aging”, Table 11: Comparison of published colour sensors with dark current cancellation circuit   [13] [7] [14] [15] [16] This work Technique Photogate bias Subtraction at digital level Subtraction Subtraction Current source/ steer Subtraction (modified Vcm) Dark Current or Dark Signal 0.93 nA/cm2 or 15 mV/s at 14 V/lux.s Complete remove Complete remove Small Complete remove. Max range is 12 nA Complete remove Dynamic Range (dB) 85 117 N/A 53 N/A 90 Sensor Ap- plication Image Color sensor Image Image Image Color Sensor A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 84 IEEE Transactions on Industrial Electronics, Vol. 61, pp. 1788–1798, 2014. 5. A. Kettler, M. Szymanski, J. Liedke and H. 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Meyer, “Analysis and Design of Analog Integrated Circuits”, 5th Edition, Wiley, 2010, pp. 811-821, 2010. 26. A. Gourevitch, T. Thurston, R. Singh, B. Banachow- icz, V. Korobov and C. Drowley, “Novel sensor for color control in solid state lighting applications”, In Proceedings of SPIE - The International Society for Optical Engineering, 2010. Arrived: 24. 01. 2018 Accepted: 18. 04. 2018 A. Marzuki; Informacije Midem, Vol. 48, No. 2(2018), 73 – 84 85 Original scientific paper  MIDEM Society Multi-hop communication in Bluetooth Low Energy ad-hoc wireless sensor network Branko Skočir1, Gregor Papa1,2, Anton Biasizzo1,2 1Jožef Stefan International Postgraduate School, Ljubljana, Slovenia 2Jožef Stefan Institute, Ljubljana, Slovenia Abstract: This paper presents a multi-hop mechanism for Bluetooth Low Energy (BLE) 4.0 ad-hoc wireless sensor network (WSN). The BLE 4.0 protocol supports only the piconet topology and does not support data transfer over multiple nodes. To overcome this limitation a mechanism to relay sensor data over multiple BLE 4.0 nodes using Master/Slave switching was developed. The mechanism dynamically creates communication paths within the BLE ad-hoc sensor network where all BLE nodes are identical. The sensor data query is initiated from a designated node and forwarded through the dynamically build network. The sensor data are collected over the same path, back to the designated node. The mechanism does not perform route discovery therefore no routing tables are needed. Using this mechanism, the range of the sensor data acquisition can be extended from BLE range to whole BLE sensor network. Keywords: Bluetooth Low Energy (BLE); wireless sensor network; multi-hop mechanism Multi-hop komunikacija v Bluetooth Low Energy ad-hoc brezžičnem senzorskem omrežju Izvleček: Članek predstavlja multi-hop mehanizem za Bluetooth Low Energy (BLE) 4.0 ad-hoc brezžično senzorsko omrežje. BLE 4.0 protokol omogoča kreiranje samo piconet topologije in ne podpira prenosa podatkov preko več vozlišč. Da bi obšli to omejitev smo razvili mehanizem za posredovanje senzorskih podatkov preko več BLE 4.0 vozlišč s preklapljanjem med Master in Slave načinom delovanja. Mehanizem v BLE ad-hoc brezžičnem senzorskem omrežju, kjer so vsa vozlišča enaka, dinamično ustvarja komunikacijske poti. Poizvedba o senzorskih podatkih se sproži iz točno določenega vozlišča in se posreduje prek dinamično sestavljenega omrežja. Podatki posameznih senzorjev se posredujejo nazaj po isti poti do vozlišča, ki je poizvedbo sprožil. Glavna prednost tega mehanizma je vzpostavitev senzorskega omrežja brez usmerjevalnih tabel. Z uporabo tega mehanizma se pokritost z BLE lahko razširi na celotno senzorsko omrežje. Ključne besede: Bluetooth Low Energy (BLE); brezžično senzorsko omrežje; multi-hop mehanizem * Corresponding Author’s e-mail: b.skocir@gmail.com Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), 85 – 95 1 Introduction Bluetooth Low Energy (BLE) is a communication tech- nology developed for low power consumption and low cost applications. It was introduced in 2006 as “Wibree” and in 2010 merged into the main Bluetooth standard with the adoption of the Bluetooth Core Specification Version 4.0 [1]. Due to the low energy consumption and ease of use the BLE technology is used in various devices, rang- ing from health care, fitness, home automation, toys, transportation and industry. Because of its low power consumption design, it is especially suitable for coin cell battery communication devices like wireless sen- sors. Several wireless sensors can form a Wireless Sen- sor Network (WSN) [2] that can acquire environmental data and send it through the network to the main de- vice or gateway. From here data can be sent over ex- isting network infrastructure to the remote client thus making a WSN and associated sensors a part of Internet of Things (IoT) [3]. In contrast to other wireless technologies, that are also used for wireless sensor networks like Zigbee and 86 B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 ANT+, the BLE 4.0 only supports Peer-To-Peer (P2P) and star topology with no multi-hop capabilities. Although the BLE 4.0 protocol is already offering a wide spread of possible usage the data relaying over multiple nodes within the network would highly increase the number of potential uses. While BLE lacks the multi-hop capabilities, there have been some attempts to implement multi-hop func- tionality using the Bluetooth application layer. Some implementations of multi-hop data transfer with BLE 4.0 are presented by Mikhaylov and Tervonen [4] as well as by Maharjan, Witkowski and Zandian [5]. In [4] a mechanism that relays data to a node with known address over intermediate nodes was suggested. The proposed mechanism was implemented on only four nodes carrying out two to three hops. The emphasized problem in the article is the high route time discovery, which takes about 25 seconds on average and is due to the service discovery time and data exchange for route establishment. In [5] the multi-hop mechanism is based on a tree network with unique node identity number addressing. The presented implementation of this approach limits the number of nodes that can be connected to each central device to at most three. The selected range of node addresses enables the forming of tree topology network up to level 5. In this paper a mechanism that enables multi-hop data transfer to a central node over multiple BLE 4.0 nodes is presented. A wireless sensor network is constructed using tree topology. All wireless sensor nodes are iden- tical and can transfer acquired data and/or relay data from the connected nodes. An evaluation wireless sen- sor network with 7 nodes was built to validate our mul- ti-hop mechanism. Each node is composed of Bluegiga BLE113 [6] communication module mounted on break- out board [7], temperature sensors [8] with additional peripheral hardware, and power supply. BLE node was implemented on our developed demonstration evalu- ation board. The rest of the paper is organized as follows: in the fol- lowing section an overview of BLE 4.0 technology is presented. The third section is focused on the related work in BLE 4.0 multi-hop data transfer. In the fourth section our multi-hop data transfer mechanism is de- scribed. In the fifth section the implementation of the mechanism is described and the results are given. The paper concludes with section six. 2 BLE 4.0 technology Bluetooth Low Energy (BLE) 4.0 is a wireless commu- nication technology that allows data to be transmit- ted over the air between two BLE devices. It uses the 2.400 GHz - 2.4835 GHz Industrial, Scientific and Medi- cal (ISM) band. BLE uses frequency hopping spread spectrum modulation technique called Direct-Se- quence Spread Spectrum (DSSS) for interference mini- mization and security maximization [9]. In contrast to the classic Bluetooth that uses 79 1MHz channels the BLE frequency hopping spans over 40 2MHz channels. 37 channels are used for data transfer, whereas the re- maining three channels are reserved for advertising [1]. Figure 1: BLE 4.0 link layer state diagram The connection and data transfer is achieved through the link layer state machine as shown in Figure 1. In Advertising state, the device has an advertiser role and transmits the advertisement packet on three advertising channels. The advertisement packet can contain from 2 to 31 bytes of advertisement data. Advertisement data can be intercepted by the devices that are in Scanning state. Depending on the gathered advertisement data the scanner can demand additional data, initiate the connection with the advertiser, or ignore the advertiser. After the connection is established both devices are in Connection state. Typically, the device that was initially scanning assumes the role of a master device whereas the advertising device becomes a slave device. While connected the devices cannot change their role. When two devices are connected they form a master/ slave pair as shown in Figure 2a. According to Bluetooth 4.0 standard a device cannot simultaneously assume master and slave role. Furthermore, while a master de- vice can connect to several slave devices a slave device can connect only to one master device. This limits the possible network configurations to a P2P pair and to a simple star topology known as piconet topology, as depicted in Figure 2b. Once the connection is established the devices can transfer data over 37 data communication channels. The data can be sent in unencrypted or encrypted packets that can have 0 to 31 bytes of Protocol Data Unit (PDU) payload [1]. Depending on the devices link layer state the PDU payload can contain the advertis- 87 ing or scanning device addresses and advertise or scanning response data. The encryption is achieved with security manager protocol (SMP) key distribution between master and slave during the pairing process. The BLE 4.0 stack is composed of several protocol layers which can be divided into two logical entities: Control- ler and Host, as shown in Figure 3. The Controller is composed of physical layer (PHY) and link layer (LL). Hardware implementation of Physical Layer is composed of a balun and an antenna which forms a radio frequency (RF) transceiver while the lay- ers from Link Layer and above reside in a SoC. The RF transceiver as a part of PHY is responsible for data transfer between devices. The link layer from the Controller manages the transmis- sion and reception of data packets with respect to the flow control and connection parameters established with other nodes. If device is in scanning, advertising or connection mode the link layer manages the data re- ceiving and transmitting. It also provides first line of se- curity by allowing the data exchange only from selected nodes. The connectivity between Controller and Host stack is managed by host controller interface (HCI). Following the HCI layer are the Host layers. The logical link control and adaptation protocol (L2CAP) manages the data multiplexing for the attribute protocol (ATT) and security manager protocol (SMP). The SMP offers different security modes, data encryption and authen- tication services. The ATT manages the discovery of server-client attributes and enables the attributes read- ing and writing functionalities. The discovery and char- acteristics exchange of the BLE 4.0 protocol services are defined by the generic attribute profile (GATT) frame- work built on top of the ATT layer. The uppermost lay- ers of BLE 4.0 stack are the generic access profile (GAP) and the applications layers. The GAP manages the com- munication between lower layers and applications and is responsible for establishing different modes of op- eration such as scanning and advertising [10]. BLE 4.0 protocol stack provides the device with all the support to operate in master or slave mode individual- ly. Unfortunately, no support is provided for the device to operate in master and slave mode simultaneously thus BLE 4.0 protocol does not support multi-hop data transfer. Figure 3: BLE 4.0 protocol stack 3 Current ble 4.0 multi-hop solutions Although the BLE 4.0 emerged in 2010 there are cur- rently just a few multi-hop implementations. In the first multi-hop implementation [4] the data transfer is achieved by implementing a new multi-hop GATT layer service. A service is divided into two parts: route di- scovery and data transfer. A transmitting node has a known end-node address so at first a route over inter- mediate nodes has to be established. At each route generation a gateway node to the target node, the target node, and number of required hops are stored in each node. After route discovery is completed the data is sent through the known route to the target node. The prime challenge at service implementation, as authors emphasized, was advertiser/scanner ope- rational state switching and memory availability. The working multi-hop service was implemented in four nodes and results were presented. In another imple- mentation of multi-hop data transfer [5] a tree network topology is used. This implementation distinguishes three different node types: root node as main or central device, inter- mediary node that act as a peripheral or central device depending on connection initiation, and leaf nodes as the peripheral devices in the tree structure. Intermedi- ary node is constructed from two devices: a central and Figure 2: BLE Master/Slave connection options B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 88 peripheral device, which are interconnected with I2C bus [11]. In their implementation the central device can be connected to at most 3 peripheral devices and with 2 byte addressing the tree network can be extended up to level 5. The tree network topology was successfully implemented and the results were presented. For futu- re work authors emphasize on reducing the negative effects of node failures thus hopefully increasing the robustness of the network. 4 Multi-hop data acquisition mechanism Data from distant nodes cannot be transferred using a direct connection, for instance if we have three nodes A, B, and C, as shown in Figure 4, where node C is not visible from node A, node A cannot directly acquire data from node C. In order for node A to acquire data from C, node B must first acquire data from C and then relay them to node A. To do this, node B must first be- come a master node, detect node C using scanning, make a connection, and retrieve data from node C. To relay data it must switch back to slave mode and advertise that the gathered data are available. The switch from slave to master operation in node B is ini- tiated by node A inquiry. Figure 4: Distant BLE nodes The basis of our multi-hop communication mechanism is the ability of each node to temporary assume the master role and to acquire the data from not already processed nodes, and relay acquired data to its master node along with its sensor data. Since this procedure is recursively repeated on each node a communication tree is dynamically generated on each data inquiry and can change with each query depending on the nodes availability and their latency. The multi-hop communication mechanism can be viewed as a two phase protocol: 1. In first phase the communication tree is build. This is started when root node begins to collect available idle nodes. A node in master mode con- nects to the available idle nodes and sends COL- LECT command to claim exclusive access to child node. Child node records connected master node as its parent node in order to prevent connections from other master nodes. This procedure is recur- sively repeated on each child node: it switches to master mode and start collecting available nodes. First phase is finished when there are no available nodes. 2. In second phase, every non-root node has a par- ent node which was determined during the first phase. Sensor data are reported back from leaf nodes towards the root node. The report is made in similar fashion as collecting: the node with ac- quired data from all its children switches back to slave mode and advertises that it has required data. When the parent detects that its child has available data, it connects to the child and initi- ates data transfer by sending READ command. When the data transfer from all children nodes is finished, the children reinitialize as idle nodes. In the presented mechanism each master node con- nects twice to each of its children: first to collect avail- able idle nodes, and then to request acquired data from child node. Since actions of the slave nodes occur when they are connected to a parent node, they are triggered by commands issued by parent node using established data connection. The multi-hop communi- cation mechanism can be viewed as building the com- munication tree by sending commands towards leaf nodes and gathering sensor data in the opposite direc- tion. The global root node initiates the data acquisition and triggers the generation of the communication net- work as depicted in Figure 5. Global root node operates as a master node only, thus its functionality can be in- terpreted as a subset of the sensor node functionality. Figure 5: Command and data path in tree topology network Let us present example with only three nodes to illus- trate the concept of our multi-hop mechanism. Node A and node C cannot be directly connected due to long distance or some obstacle, while node B is reachable B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 89 by both nodes. Let us assume that the data inquiry is started from node A. The behaviour of the multi-hop mechanism is depicted in Figure 6 and Figure 7 where master nodes are denoted by black shading and slave nodes are white. Figure 6: Communication tree formation Figure 6 describes the communication tree formation of multi-hop communication mechanism: - Initially all nodes are idle and are advertising their presence (Figure 6a). - Node A is selected as a root node (inquiry node), node A became a master node and is scanning for neighbour nodes. It detects node B as an idle node (Figure 6b). - Since node B is idle, node A connects to node B and issues a command to node B to start its own data inquiry (Figure 6c). - Both node A and node B are scanning, however node C is reachable only by node B. Node B de- tects node C as an idle node (Figure 6d). - While node A is still scanning nodes (for the data inquiry results) the node B connects to node C and issues a command to node C to start its own data inquiry (Figure 6e). - All three nodes are scanning; node A and node B are scanning for data results, while node C is scan- ning for an idle node (Figure 6f ). The first phase terminates when there is no available idle node. The scanning of the node, which is search- ing for an idle node, is terminated by a predetermined timeout. The timeout must be long enough to guar- antee the detection of an idle node in the vicinity (we used a value of 1 second). Figure 7 describes the data acquisition of multi-hop communication mechanism: - After the timeout in node C (Figure 7a), node C reads its sensor data and switches from scanning mode to advertising mode indicating that it has data available. - Node B is scanning for its child nodes with sen- sor data and detects that node C have data ready (Figure 7b). Note that while node A is also scan- ning for nodes with data ready the node C is not its child and would be ignored even if it was de- tected. - Node B connects to node C and node C sends its sensor data to node B. Node B adds its sensor readings to the received data from node C (Figure 7c). - Node B finishes its scanning since it has processed all its children. Then it switches to advertising mode indicating that it has sensor data available. Node A which is scanning for its child nodes with sensor data ready, detects that node B has data ready (Figure 7d). - Node A connects to node B and node B sends its sensor data to node A. Node A adds its sensor readings to the received data from node B (Figure 7e). - Since Node A is the root node it report all gath- ered sensor data and switch from master mode to advertising mode (Figure 7f ). From the single node point of view the multi-hop data acquisition mechanism is composed of: - Master mode operation, which is further divided to operations: - Collecting all available neighbouring slave nodes and claiming exclusive access to the collected slave nodes. This is achieved by sending COLLECT command to all free slave nodes. Since the master node doesn’t know how many available slave nodes are in its vi- cinity this operation has to be stopped using timeout. - Requesting sensor data from child node when the child node has acquired all available sen- sor data from its descendant nodes. This is achieved by sending READ command. - Slave mode operation, which consists of follow- ing operation: - Idle operation: the node advertises that it is available and has no parent node. The node waits for the connection from any master node. After the node is connected to a master node, it accepts only COLLECT command. On Figure 7: Data acquisition B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 90 the receipt of this command it records parent node address and advertises parent node ad- dress along with its current state - Serving data operation: the node has all avail- able data from its descendant nodes. It adver- tises its parent node address and its current state. After the node is connected from the parent node it transfers the acquired data to the parent node. When the sensor data is transferred the node erases parent node ad- dress and restarts with the idle operation. The simplified procedure of the multi-hop mechanism is: while true { advertise idle while not (cmd = COLLECT) {} // wait for COLLECT command record connecting node master_mode advertise parent and data_ready while not (cmd = READ) {} // wait for READ command send acquired data erase parent node address } The master mode operation of the multi-hop mecha- nism is: start scanning // switch to master mode while not timeout { if node_available { add node to set connect send COLLECT cmd } } foreach node in set { if node data_ready { Connect node Send READ cmd } } The multi-hop mechanism was implemented using finite state machine. The states identify the current mode of operation of the node. Initially we used four states: IDLE, COLLECT, READ, and READY. States IDLE and READY states correspond to slave node operation and states COLLECT and READ correspond to master node operation. However, the resulting connection trees using these states were quite deep. This was because each slave node that entered the COLLECT state on re- quest of a master node immediately started collecting free nodes in its vicinity and thus also competed with its master node. This is undesirable because it results in very deep connection trees with longer data acqui- sition time. To impose breadth-first generation of the connection tree generation an additional slave state PREPARE between the IDLE state and COLLECT state was introduced. This way the collected slave nodes start collecting remaining nodes after the master node fin- ished the collect operation. Consequently, correspond- ing master state TRIGGER has to be added to control the additional slave state transition. There are similar problems on the data acquisition part of the mechanism hence the FREE state was introduced between READY state and IDLE state to delay the releas- ing of slave nodes, and RELEASE state between READ state and READY state in order to control the state tran- sition. The final finite state machine of the multi-hop node is depicted in Figure 8. Figure 8: Master and Slave state mechanism Initially all BLE nodes operate in slave mode and advertise their presence using unique 128bit multi-hop service UUID. Besides the multi-hop service identification master nodes require also additional data: whether the slave node is avail- able and if the node has acquired data from its descend- ant nodes. While this information could be gathered by es- tablishing the data connection such solution would cause larger delays since a slave node can connect to a single master node and while connected it is inaccessible to other master nodes. Best solution is to advertise current state of the node. Furthermore, to eliminate the unnecessary con- nections to the nodes, which are already collected by some node the slave node advertises the ID of its parent node. This way the master node can filter out the slave nodes which do not respond to it. Since there are no suitable pre- determined advertisement packets in the GATT layer of BLE 4.0 protocol stack a custom advertising packet is used. The final advertising data are shown in Table 1. B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 91 Table 1: Advertising packet ADV packet Custom 128bit UUIDDevice state Masters MAC address Data Length 1 6 16 Packet length 9 18 The advertising data is composed out of 27 bytes. Each advertising packet occupies one byte for packet type ID, one byte for packet length, and packet data. Device state occupies 1 byte and is a copy of the current state of the device. The master node ID is the MAC address of the master node. The master node ID of the node is initialized to NULL in the IDLE state. After first connec- tion from a master node its MAC address is copied into the advertising packet and only connections from this master node is allowed until the node is released. Then the node enters the IDLE state and the master node ID is restored to NULL. Consequently, the master node ID of the root node is always NULL. Generic multi-hop state machine implementation is: 1 while true { 2 switch (state) { 3 case IDLE: // slave mode 4 if (cmd=PREPARE) { 5 parent = master_node 6 state = PREPARE 7 advertise(parent,state) 8 } 9 case PREPARE: // slave mode 10 if (cmd = COLLECT && master_mode = parent) { 11 state = COLLECT 12 start_scan() // switch to master mode 13 } 14 case COLLECT: // master mode 15 if timeout state = TRIGGER 16 else if available_idle(node) { 17 connect(node) 18 send_cmd(PREPARE) 19 add_to_children_set(node) 20 } 21 case TRIGGER: // master mode 22 if children_set_processed() state = READ 23 else if available_prepare(node, my_address) { 24 connect(node) 25 send_cmd(COLLECT) 26 } 27 case READ: // master mode 28 if children_set_processed() state = RELEASE 29 else if available_ready(node, my_address) { 30 connect(node) 31 data_request_cmd(READ) 32 } 33 case RELEASE: // master mode 34 if children_set_processed() { 35 state = READ 36 advertise(parent,state) 37 } 38 else if available_free(node) { 39 connect(node) 40 send_cmd(RELEASE) 41 } 42 case READY: // slave mode 43 if (cmd = READ && master_mode = parent) { 44 send_sensor_data() 45 state = FREE 46 advertise(parent,state) 47 } 48 case FREE: // slave mode 49 if (cmd = RELEASE && master_mode = parent) { 50 clear parent 51 state = IDLE 52 advertise(parent,state) 53 } 54 } 55 } The states of the multi-hop mechanism are: - IDLE state: the node is in slave mode but it has no parent node therefore it is available. It operates as a slave and advertises its state. On connection from a parent node using the PREPARE command the state changes to PREPARE state. - PREPARE state: the node is in a slave mode but it is reserved by the parent node. It advertises its state and its parent node. It accepts the connections only from its parent node and the only viable action is to change to COLLECT state by COLLECT command. - COLLECT state: the node is in master mode. In the master mode the advertisement is stopped. It scans the neighbouring nodes, collects available nodes, records them and sends them TRIGGER command for an exclusive access. After reason- able timeout, the collecting process is stopped. The node then switches to TRIGGER state if there are some collected nodes, otherwise the node switches to READY state. - TRIGGER state: the node is in the master mode. The collected nodes are triggered to a COLLECT master state in order to acquire data from distant nodes. The node scans the neighbouring nodes and when a slave node, advertising that it was collected by this node, is found, TRIGGER command is given to this slave node. After all collected slave nodes are processed, the node switches to READ state. - READ state: the node is in the master mode. It scans the neighbouring nodes and when a slave node, advertising that it has data ready for this node, the read process is triggered using READ command. After all collected slave nodes are pro- cessed, the node switches to RELEASE state. - RELEASE state: the node is in the master mode. It scans the neighbouring nodes and when a slave node, advertising that it could be freed is detect- B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 92 ed, RELEASE command is given to free the collect- ed slave node. After all collected slave nodes are processed, the node switches to READY state. - READY state: the node is in the slave mode. When the data connection from the parent node is es- tablished the acquired data along with the local node sensor data are sent to the parent node. After the data transfer is completed the node switches to FREE state. - FREE state: the node is in slave mode. It advertises that it could be freed. On the receipt of RELEASE command from the parent node it re-initializes all data structures and switches to IDLE state. Initially all BLE nodes operate in slave mode. To initi- ate the data acquisition on a selected BLE node a com- mand is issued on its UART peripheral interface to as- sume the role of the root node. At this point the root node starts collecting neighbouring nodes, acquires their data, and reports the acquired data over the UART peripheral interface. 5 Implementation and results For testing and evaluation of the multi-hop communi- cation mechanism a custom measurement board was developed. Peripheral hardware consists of power sup- ply, USB and UART interface, LM75B temperature sen- sor [8], and a Bluegiga BLE113 breakout board [7]. Table 2: BLE113 specifications Device Bluegiga BLE113 Supply voltage 2V – 3.6V Peripheral interface UART, SPI, I2C,PWM,GPIO, ADC TX consumption 18.2mA RX consumption 14.3mA Sleep mode consumption 0.4uA TX power 0dBm to – 23dBm RX sensitivity -93dBm SoC CC2541 chip: - 8051 CPU, - 32MHz clock, - 128kB or 256kB Flash - 8kB SRAM Smart stack GAP, GATT, L2CAP and SMBluetooth smart profiles Max connections in master mode 8 Throughput 100kbps + The main specifications of BLE113 module are pre- sented in Table 2. The module is based on a CC2541 SoC from Texas Instruments with integrated 8051 CPU, Bluetooth radio and software stack [12]. Module offers a wide range of peripheral interface on 17 con- figurable I/O ports, two configurable I/O ports with 20 mA driving capability and two ports that can be used as digital I/O or I2C communication channel. BLE113 module configurable ports offer a broad assortment of peripheral functionality: - UART and SPI communication, - three timers that each can offer timer, counter or PWM functionality, - up to 12bits of resolution ADC converter BLE113 is capable of managing 8 slave devices in master mode with over 100kbps throughput. Mod- ule is mounted on the BLE113 breakout board which is installed on a peripheral hardware board with tem- perature sensor. The communication between BLE113 module and temperature sensor is implemented with I2C interface. Software was written in BGScript language [13], which is event-driven BASIC-like application scripting lan- guage. Each event handling subroutine can consist out of numerous instructions and each instruction can be executed in 1-2ms [13]. Since the BLE113 module in- corporates 8051 MCU with several GPIO ports as well as some general purpose communication protocols (e.g. I2C, SPIO) we were able to develop a fully stan- dalone BLE device without the external CPU and/or additional memory. BGScript incorporates additional APIs for managing Bluetooth connections and various hardware interfaces. In this regard I2C data transfers for temperature sensor readings, UART for debugging pur- poses, and GPIO for external triggering were used. Although the BGScript provides most common pro- gramming structures and relatively rich APIs it has several limitations. The main limitations are the limited amount of available RAM used for variables, the limited amount of available non-volatile memory for program storage and most notably the limited amount of pro- gram stack. The program stack is limited to at most 100 bytes which does not allow deep function nesting nor moderate size function parameters. For the evaluation process seven BLE devices were used from which one was used as root device and six were used as child nodes. The collected data from each child node was a temperature stored as a short integer occupying two bytes. Total amount of program code was around 60KB which is approximately 23% of available non-volatile mem- ory [6]. The program code was the same on all nodes in the network. To initiate the data collection through B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 93 the network one node was connected to the comput- er. This node became a root node once it received the command to start the data collection over the USB/ UART communication port. Detailed mechanism im- plementation in BGScript language for our measure- ment board is presented in technical report [14]. In the first experiment set we tested completely con- nected wireless sensor network where each pair of nodes are connectable. The nodes were placed in the same room at a random distance of a few meters from each other. Using such placement, we conducted two sets of tests. In the first test set the maximum num- ber of connected slave nodes were limited to two. This way we forced the master nodes to connect to at most two child nodes which resulted in a binary tree network topology. In the second test set we released the maximum connection limitation. Since all nodes were relatively close, they formed a star topology. Both test sets consist of 2000 temperature data acquisitions and were collected automatically using python scripts on a PC computer. There was a pause of few seconds between each data acquisition to mitigate errors that might arise from environment disturbances. In the first test set, when the number of child nodes was limited to two, the formed networks were binary tree networks with maximal depth of 3 and various fan-out shapes. In the test the isomorphic binary trees were collected together. Representations of the most frequent isomorphic network trees in the first test set are shown in Figure 9 whereas the frequency of the isomorphic network formation is presented in Table 3. The most common binary tree network was a balanced tree shown in Figure 9d. The data collecting time in bal- anced tree network varied from 13 to 16 seconds. Table 3: Frequency of binary tree network formation Binary tree network 9a 9b 9c 9d Occurrences 33 44 413 1205 Figure 9: Binary tree networks In the second test set performed without connection limitation, nodes formed a star topology structure where all child are nodes connected directly to root node. With this mode of operation, no multi-hop data transfer was conducted. The data collecting time varied from 20 to 38 seconds. During 2000 data acquisition requests a total of 35 dif- ferent tree network topologies were created. In both test sets there were some cases where not all nodes were connected. This can be attributed to the environment disturbances when some nodes become inaccessible. Since we implemented only basic er- ror handling in the multi-hop mechanism such errors might span over few consecutive tests. Finally, we tested the mechanism in real-life environ- ment. In the real-life environment the sensor nodes do not form a complete graph and if there is a limita- tion on the number of child nodes some nodes may become inaccessible. Therefore in the real-life environ- ment the limitation on the number of the child node must be omitted. In our test the sensor nodes were placed throughout the building where they formed a sensor network shown in Figure 10. Figure 10: Sensor network connection graph Figure 11: Tree networks with N1 as the root node B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 94 We conducted two sets of tests. In the first test set the N1 sensor node was chosen as a root node. In the Figure 11 two typical tree networks are depicted. The maximal depth of connection trees was 3. The data col- lecting time for these connection trees were 25,1 and 23,2 seconds respectively. In the second test set N7 was chosen as the root node. In the Figure 12 two examples of tree networks are shown. The data collecting time for these connection trees were 27,2 and 25,5 seconds respectively. Figure 12: Tree network with N7 as the root node 6 Conclusions As Bluetooth Low Energy technology continues to gain its use in wireless sensor network the demand for vi- able data transfer mechanisms over wireless sensor network also increases. In this paper a multi-hop communication mechanism for data acquisition in Bluetooth Low Energy 4.0 ad-hoc wireless sensor network is presented. The goal was to extend the range of BLE wireless sensor network by re- laying data over a series of identical sensor nodes in the wireless network. Initially, the mechanism was coded using numerous nested functions and medium-size function param- eters that increased program stack consumption. That led to program stack overflow and subsequently to un- predictable behaviour of BLE113 module such as de- vice reboot or variable corruption. The code was later flattened to eliminate program stack overflows. We demonstrated that our multi-hop data acquisition mechanism can be used for a sensor data collection in tree topology networks. Although the sensor data collection can take a noticeable amount of time the mechanism can be nonetheless used for relatively slow processes such as temperature measurements. In future we will improve the reliability of the mecha- nism and include a time-to-live mechanism that will improve robustness and allow the use of mechanism in more dynamic environments. 7 Acknowledgments The authors acknowledge the financial support from the Slovenian Research Agency (research core funding No. P2-0098). 8 References 1. Bluetooth Core Specification, Version 4.0, SIG, June 2010. 2. M. Ilyas and I. Mahqoub, »Handbook of Sensor Networks: Compact Wireless and Wired Sensing Systems,« CRC press LLC, 2005. 3. G. Kortuem, F. Kawsar, D. Fitton, and V. Sundra- moorthy, »Smart objects as building blocks for the internet of things,« Internet Computing, IEEE, vol. 14, 44-51, 2010. 4. K. Mikhaylov and J. Tervonen, »Multi-hop Data Transfer Service for Bluetooth Low Energy«, 2013 13th International Conference on ITS Telecommuni- cations (ITST), IEEE 2013. 5. B. K. Maharjan, U. Witkowski and R. Zandian, »Tree network based on Bluetooth 4.0 for wireless sen- sor network applications,« in Education and Re- search Conference (EDERC), 2014 6th European Embedded Design in, pp. 172-176, 2014. 6. BLE113 Bluetooth Smart Module. Available at: https://www.bluegiga.com/en-US/products/ ble113-bluetooth-smart-module/, visited on 15.5.2016 7. BLE113 Bluetooth Low Energy Breakout, Available at: http://www.inmojo.com/store/ jeff-rowberg/ item/ble113-bluetooth-low-energy-breakout/, visited on 15.5.2016 8. LM75B Digital temperature sensor and thermal watchdog, Available at: http://www.nxp.com/ documents/data_sheet/LM75B.pdf, visited on 4.6.2016 9. K. Mikhaylov, N. Plevritakis, and J. Tervonen, »Per- formance analysis and comparison of Bluetooth Low Energy with IEEE 802.15.4 and SimpliciTT,« J. Sens. Actuator Networks, vol. 2, no. 3, pp. 589-613, Aug. 2013. 10. Carles Gomez, Joaquim Oller and Josep Paradells, »Overview and Evaluation of Bluetooth Low En- ergy: An Emerging Low-Power Wireless Technol- ogy«, Sensors, 29 August 2012. B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 95 11. Wikipedia – I²C, Available at: http://en.wikipedia. org/wiki/I2C, visited on 22.8.2017 12. »2.4-GHz Bluetooth Low Energy and Proprietary System-on-Chip«, Texas Instruments, June 2013 13. BGScript, Available at: http://www.hmangas. com/ Electronica/Datasheets/Bluetooth%20Mo- dule/BLE112/Bluetooth+Smart+BGScript+Deve- loper+Guide.pdf, visited on 18.6.2016 14. Branko Skočir, Gregor Papa, Anton Biasizzo. Multi- hop communication code, IJS technical report No. 12380, 2018. Arrived: 19. 12. 2017 Accepted: 03. 05. 2018 B. Skočir et al; Informacije Midem, Vol. 48, No. 2(2018), 85 – 95 96 97 Original scientific paper  MIDEM Society Lossy and Lossless Inductance Simulators and Universal Filters Employing a New Versatile Active Block Mohammad Faseehuddin1, Jahariah Sampe2, Sadia Shireen3, Sawal Hamid Md Ali4 1Institute of Microengineering and Nanoelectronics (IMEN),UniversityKebangsaan Malaysia (UKM), Bangi, Selangor, Malaysia 2Institute of Microengineering and Nanoelectronics (IMEN), University Kebangsaan Malaysia (UKM), Bangi, Selangor, Malaysia 3Department of Electronics and Communication, Indus Institute of Technology and Management, Kanpur, India 4Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia Abstract: In this paper six new implementations for realizing lossy and lossless active inductors are presented. The new topologies are obtained using a newly formulated active block namely, the extra X current conveyor transconductance amplifier (EXCCTA). The designed grounded inductor simulators (GIS) require only three grounded passive elements for implementation which is desirable for integrated circuit fabrication. Moreover, the inductance simulators are electronically tunable and free from matching requirements. Additionally, two structures of universal filters are also proposed. The voltage mode (VM) filter is multi input single output (MISO) structure and uses canonical number of passive components. The current mode (CM) filter is a single input multi output (SIMO) structure with grounded passive elements. The filter structures can realize all five standard filter responses without any matching conditions and have features of low/ high output impedance, low active and passive sensitivities, tunability, independent control of pole frequency and quality factor. The effect of non-idealities on the inductor and filter topologies are also analyzed. The simulations are performed in 0.18μm parameters from TSMC in Spice to validate the theoretical predictions. Experimental results using AD844 and LM13700 integrated circuits (ICs) for the proposed inductor and filter are also provided to further ascertain the feasibility of the proposed solutions. Keywords: active inductor; current mode; current conveyor; filter; tunability Izgubni in brezizgubni induktivni simulator ter univerzalen filter z z novim prilagodljivim aktivnim blokom Izvleček: Članek predstavlja šest primerov realizacije izgubnih in brez izgubnih aktivnih dušilk. Nove topologije uporabljajo nov aktivni blok; ekstra X tokovni transkonduktančni ojačevalnik (EXCCTA). Načrtani ozemljeni induktivni simulatorji (GIS) zahtevajo le tri ozemljene pasivne elemente in so elektronsko nastavljivi ter neodvisni od zahtev ujemanja. Dodatno sta predlagani dve strukturi univerzalnega filtra. Več vhodni in eno izhodni filter v napetostnem načinu uporablja standardno število pasivnih elementov. Tokovni filter je eno vhodni in več izhodni z ozemljenimi elementi. Filtri lahko realizirajo vseh pet standardnih odzivov brez prilagajanj. Imajo nizko/visoko izhodno impedanco, nizko aktivno in pasivno občutljivost, nastavljivost, neodvisno kontrolo frekvence in faktorja kvalitete. Simulacije so izvedene v 0.18 μm tehnologiji iz TSMC in SPICE za validacijo teoretičnih predvidevanj. Eksperimentalni rezultati so pridobljeni s uporabo AD844 in LM13700 integriranih vezij. Ključne besede: aktivna dušilka; tokovni način; tokovni ojačevalnik; filter; nastavljivost * Corresponding Author’s e-mail: faseehuddin03@siswa.ukm.edu.my Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), 97 – 113 98 M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 1 Introduction The physical spiral inductors suffer from low realiz- able inductance value of the order of 1nH [1, 2], low quality factor, higher chip area requirement, excessive losses and susceptibility to process variations [1]. These drawbacks make them unsuitable for integrated circuit implementation. Since inductors are inevitable com- ponents given their broad spectrum of applications in active filters, parasitic cancellation, oscillators, radio frequency (RF) systems etc. [2]. The active simulation of inductors where active devices are employed instead of spiral inductors to emulated the behavior of passive inductors has become popular [1-3]. Analog filters are an integral part of almost every electronic system and so their synthesis and development remains an ever evolving field. Among various filter structures univer- sal filters (UFs) are the most versatile as all the standard filter functions can be derived from them[6-9]. They serve as standalone solution to many filtering needs. The UFs find applications in phase locked loop FM ste- reo demodulator, telephone decoder, speech process- ing etc.[7-8]. The current mode active elements are the best choice for inductor and filter synthesis, own- ing to their large dynamic range, great linearity, wide bandwidth, higher slew rate and excellent low voltage performance compared to their voltage mode coun- terparts [6-7]. Numerous current mode active blocks have been employed for inductance simulation and filter design like second generation current conveyor (CCII) [4], differential voltage current conveyor (DVC- CII) [2], dual X current conveyor (DXCCII) [22], current conveyor transconductance amplifier (CCTA) [28], dif- ferential current conveyor (DCCII) [11], differential dif- ference current conveyor (DDCC) [1], fully differential current conveyor (FDCCII) [34], voltage differencing current conveyor (VDCC) [25], current feedback opera- tional amplifier (CFOA) [13], modified current feedback operational amplifier (MCFOA) [18], inverting current feedback operational amplifier (CFOA-) [5], current dif- ferencing transconductance amplifier (CDTA) [37] etc. The GIS can be categorized based on many criteria like number of active devices used, passive component count, lossy/lossless type inductance realization, use of grounded passive elements, feature of inbuilt tu- nability, capability of active element realization using the off the shelf integrated circuits (ICs) like AD844 etc. The GIS presented in [4, 12-13] require more than one active element for inductance simulation. The GIS imp- lementations presented in [4, 12-13, 15, 21, 23] require more than three passive elements. Although in current fabrication technology it is feasible to implement floa- ting capacitor but use of grounded capacitor has inhe- rent advantages in terms noise cancelation, chip area and parasitic reduction. The GIS implementations in [5, 10, 12, 14-17, 19, 21-24] makes use of one or more floating capacitors. Tunability is one of the major de- sign requirements in today’s mixed mode systems. The GIS circuits in [1, 4-5, 11-24] did not have inbuilt tuning capability. A thorough comparison of the exemplary in- ductance topologies available in the literature with the proposed lossy/lossless GIS topologies is given in Table 1. The literature survey reveals that the draw backs of the majority of the presented inductor simulators are (i) no provision for on chip tunability (ii) use of more than one active element (iii) use of floating capacitor (iv) excessive use of passive elements (v) passive com- ponents matching requirnment. In this research a new active block the extra X current conveyor transconductance amplifier (EXCCTA) is utili- zed in designing six topologies of lossy/lossless indu- ctance simulators. All the designed GIS employ only a single active element and two/three grounded passive elements for implementation. No matching is required for implementation and inductance can be easily tuned via bias current of the transconductor. Further more, two minimum component VM and CM mode universal filters are proposed. The filters structures are characte- rized by following attributes (i) use of minimum num- ber of active blocks and passive components (ii) inbuilt tunability (iii) use of grounded passive elements (iv) provision for independent control of pole frequency and quality factor (v) avalibility of output at low impe- dance in case of VM filter and high impedance in CM filter. The simulation are performed using 0.18μm pa- rameters from TSMC in Spice to validate the theoretical findings. Additionally, an experimental study of pure inductor and VM SIMO filter is conducted using AD844 and LM13700 ICs. The measured results are compared with the ideal ones. 2 Extra X current conveyor transconductance amplifier (EXCCTA) The proposed Extra X current conveyor transconduc- tance amplifier (EXCCTA) is functionally a connection of extra x current conveyor (EXCCII) [26] and operational transconductance amplifier (OTA) [30]. The new block carries features of CCII and tunable OTA in a single in- tegrated circuit structure. The Voltage current charac- teristics of the developed EXCCTA are given in matrix Equation1 and the block diagram is presented in Fig. 1. The block is found to be suitable for implementing minimum component filters and inductor simulators as it provides two independent current input X terminals and an inherent tunable structure. 99 (1) Figure 1: Block diagram of EXCCTA The CMOS implementation of EXCCTA is presented in Fig. 2. It is a 9 terminal active element. The first stage consists of EXCCII transistors (M1-M28). The voltage ap- plied at Y node appears at XP and XN nodes. The cur- rent input at Xp node is transferred to nodes Zp+ and Zp-. In the same way the input current from XN node is trans- ferred to ZN+ and ZN-. The current following in ZN and Zp terminals are independent of each other. The class AB output stage is selected for the implementation as it is suitable for low voltage operation [6]. The second stage is composed of OTA. The transconductance is realized using transistors (M29-M40).The output current of the trans-conductor depends on the voltage Zp+. Assuming saturation region operation for all transistors and equal W/L ratio for transistors M29 and M30 the output cur- rent Io of the OTA is given by Equation 2. ( ) ( )( )2 O mi ZP Bias i ZPI g V I K V+ += = (2) Where, the transconductance parameter Ki = µC0x W/2L, (i=29, 30) W is the effective channel width, L is the ef- fective length of the channel, Cox is the gate oxide ca- pacitance per unit area and µ is the carrier mobility. It is evident from (2) that the transconductance can be tuned by the bias current thus imparting tunability to the structure. The most critical parameters of the EXCCTA can be computed by following the analysis procedure given in Table 1: Comparison of exemplary active inductors with the proposed ones Reference No. of Active Devices Used No. of Passive Elements Capacitor Floating Matching Condition Inbuilt Tunability [1] Fig. 5 MDO-DDCC (1) 3 No Yes No [4] CCII (3) 4 No No No [5] CFOA − (1) 3 Yes No No [10] VDBA (1) 2 Yes No Yes [11] DCCII (1) 3 No Yes No [12] OTRA (2) 5 Yes Yes No [13] CFOA (2) 4 No Yes No [14] DCCII (1) 3 Yes No No [15] OTRA (1) 4 Yes No No [16] MICCII (1) 3 Yes Yes No [17] GVCCIII (1) 3 Yes Yes No [18] MCFOA (1) 3 No No No [19] CFOA (1) 3 Yes No No [20] CCII (1)+Current Follower (1) 3 No No No [21] PFTN (1) 5 Yes Yes No [22] DXCCII (1) 3 Yes Yes No [23] OTRA (1)+Voltage Buffer (1) 4 Yes Yes No [24] CFOA (1) 3 Yes No No Fig. 3 Proposed GIS-(1-2, 4-6) EXCCTA (1) 3 No No Yes Fig. 3 Proposed GIS-3 EXCCTA (1) 2 No No Yes M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 100 [6]. The voltage transfer ratio between Y and Xp node can be derived as given in Equation 3. ( ) ( ) 009 014 9 14 4 09 014 009 014 9 14 3 09 014 2 1 2 p m m m XP P pY m m m rr r g g g r rV rr rV g g g r r α + + = = + + + 4 3 m m g g (3) Where r0p = r03//r07, r0 is the output resistance of the MOS transistor and gm is the transconductance of the MOS transistor. In the similar way the voltage transfer between Y and XN can be obtained as given below. The current transfer ratios βp and βN depend on the load connected at X and Z terminals. This is a slight draw back but if the value of the load connected is less than MOS transistor resistance than an accurate transfer is achieved. The current transfer ratios are derived as giv- en in Equation 5-6. 1 2 mXP N Y m gV V g α = ≌ (4) (5) ZN N XN I I β = 20 24 19 28 m m m m g g g g + + (6) The X terminal resistance of XN and Xp terminal is calcu- lated as given in Equations 7-8. ( ) 009 014 9 14 4 09 014 1 2 XP p m m m R rr r g g g r r = + + + ( )0 4 9 14 2 p m m mr g g g+ (7) XNR ( )0 1 19 28 2 n m m mr g g g+ (8) Where r0p= r03//r07 and Where r0n= r02//r06 The Z and O nodes impedances are found to be high given by parallel output resistance of MOS transistors. 010 015 010 015 ZP r rR r r = + (9) 020 024 020 024 ZN r rR r r = + (10) 033 039 0 033 039 Z r rR r r+ = + (11) The extra transistor count should not be considered a disadvantage since the unused Z terminal can be re- moved reducing the transistor count. M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 2: CMOS Implementation of EXCCTA 101 GIS-1 (a) GIS-2 (b) GIS-3 (c) GIS-4 (d) GIS-5 (e) GIS-6 (f ) Figure 3: The proposed lossless and Lossy inductor simulators Table 2: The impedance relations of the proposed active inductors Simulator Impedance Realized Inductance ( eqL ) Equivalent Resistance ( eqR ) Type Tunability Matching Requirement GIS-1 eqL 1 1 2 m 1 2 SC R R g (R +R ) - Pure Yes No GIS-2 eqL 1 1 2 m 1 2 SC R R g (R +R ) - Pure Yes No GIS-3 eqL 1 1 m SC R 2g - Pure Yes No GIS-4 1 1+ eq eqL R 1 2 m SC R g 1R L in parallel with R Yes No GIS-5 1 1− − eq eqL R 1 2 m SC R g − 1R− -L in parallel with -R Yes No GIS-6 +eq eqL R 1 2 m SC R g 2 1 m R R g L in series with R Yes No M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 102 3 The proposed inductor simulators and universal filters The proposed inductor simulators using a single EXC- CTA and grounded passive elements are shown in Fig. 3(a-f ). A simple analysis of the circuits reveals that the GIS-1 to GIS-3 realize pure inductance. The GIS-4 and GIS-5 implements lossy parallel RL inductors. It is note- worthy that the value of the parallel resistor in GIS-4/5 can be set using resistor R1 independent of the induct- ance value that is set by R2 and gm which is an advan- tage. Finally, the GIS-6 realizes lossy series RL inductor. The series resistance in GIS-6 can be altered by chang- ing R1 without affecting the inductance. All the presented inductor simulators use only ground- ed passive elements which is advantageous for inte- grated circuit implementation. The use of grounded capacitor saves chip area and also minimizes noise effects. Furthermore, all the simulators are free from components matching constraints and tunable via bias current of the OTA. The impedance relations of the in- ductors are given in Table 2. Next, the proposed VM universal filter is presented in Fig. 4. The filter structure is obtained by modifying the proposed series inductor GIS-6. The SIMO filter uses ca- nonical number of passive components and can realize low pass (LP), high pass (HP), band pass (BP), notch pass (NP) and all pass (AP) responses. Among the two capaci- tors one is always grounded which is an advantage. The features of the filter includes use of single active block, low output impedance, tunability and provision for in- dependent control of quality factor and pole frequency. The transfer function, expression of -3dB cutoff frequen- cy, quality factor and bandwidth of the filter are given in Equations 12-14. The output can be tapped from Y ter- minal or low impedance XN terminal. The combination of filter input modes and applied input voltages for real- izing all the five filter responses is summarized in Table 3. 2 1 2 2 2 2 1 2 3 1 2 1 2 2 2 2 1 1 m m out m m S C C R SC RV V V g g RV S C C R C RS g g R + + = + + (12) 1 2 2 m o g C C R ω = (13) 1 1 2 2 mC gQ R C R = (14) Table 3: The activation sequence of the filter Response Inputs V1 V2 V3 LP 0 0 1 HP 1 0 0 BP 0 1 0 NP 1 0 1 AP 1 -1 1 The MISO CM filter is shown in Fig. 5. The filter employs three grounded passive elements and can realize all LP, BP and HP responses simultaneously. The AP response can be obtained by summing the HP, BP and LP re- sponses. All the responses are available at high imped- ance nodes except the HP response which is available through the capacitor . The HP current can be sensed using a simple current follower. The features of the filter includes use of single active element, grounded pas- sive elements and tunability. The transfer functions for five filter responses are given in Equations 15(a)-15(e). Figure 5: The proposed CM SIMO filter 2 1 2 1 2 1 1 1 LP in m I S C C RI SC R g −= + + (15a) M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 4: The proposed VM mode MISO filter 103 2 1 2 1 2 1 2 1 2 1 1 mHP in m S C C R gI S C C RI SC R g − = + + (15b) 2 1 2 1 2 1 2 1 1 BP in m I SC R S C C RI SC R g = + + (15c) 2 1 2 1 2 1 2 1 2 1 1 1 NP m in m S C C R I g S C C RI SC R g − − = + + (15d) 2 1 2 1 2 1 2 1 2 1 2 1 1 1 mAP in m S C C R SC R gI S C C RI SC R g − − + = + + (15e) 1 2 1 1 2 m o gf C C Rπ = (16) 1 2 1m CQ g C R = (17) 4 Non-Ideal analysis In this section the Non-idealities of the EXCCTA are con- sidered and their influence on the proposed inductors and filter circuits is analyzed. A simplified non-ideal model of EXCCTA is presented in Fig. 6 for analysis. The most important aspects contributing to the deviations in frequency performance are the non-ideal frequency dependent current and voltage transfer gains, αi(s) and βi(s) respectively, where αi(s) = α0i/(1 + s/ωαi) and βi(s) = β0i/(1 + s/ωβi). Ideally, α0i = β0i = 1 and ωαi = ωβi = ∞. An- other important performance parameter is the associ- ated parasitics at the X nodes which can be quantified as ZXP = ZXN = RX(N,P) + sLX(N,P). The parasitic resistance and capacitance associated with the Y and Z nodes are RZP, RZN and RY. While the associated capacitances are CZP, CZN and CY. There ideal values being equal to zero.The γ represents the transconductance transfer inaccuracy of the OTA, while Ro and Co are parasitics at the OTA out- put. If the effect of the non-ideal gains is considered the V-I relations of the EXCCTA will be modified to IY = 0, VXP = βp(s)VY, VXN = βN(s)VY, IZP+ = αp(s)IXP, IZP- = αp´(s)IXP, IZN+ = αN(s)IXN, IZN- = αN´(s)IXN, I0+ = γgmVZP+, I0- = γ´gmVZP+. The modified expressions of inductance Leq of the ac- tive inductor simulators taking into account the non- ideal current and voltage transfer gains of the EXCCTA is given in Table 4. Table 4: Modified inductance Leq of the active inductor simulators for non-ideal case GIS-1 ( ) 1 1 2 1 2 eq m P P N N SC R RL g R Rγ α β α β+′ = GIS-2 ( ) 1 1 2 1 2 eq m P P N N SC R RL g R Rγ α β α β+′ = GIS-3 ( ) 1 1 eq m P P N N SC RL gγ α β α β+′ = GIS-4 ' 1 2 1 m P P N N eq gL SC R R γ α β α β +′= GIS-5 1 2 1 m P P N N eq gL SC R R γ α β α β− = − GIS-6 21 2 m m 1 SC R g g N N eq P P RL R α β α β γ γ = + ′ ′ The expressions of transfer function, pole frequency and quality factor including the non-ideal gains for the VM and CM filters are presented in Equations 18-23, re- spectively. 2 2 21 2 2 1 2 3 1 2 2 21 2 2 1 N P m m out N N P P m m SC RS C C R V V V g g RV C RS C C R S g g R α α γ γ γ α β α β γ γ + + = + + (18) 1 2 2 1 2 m P P o gf C C R α β π = (19) 1 1 2 2 P P m N N g CQ R C R α β γα β= (20) 2 '1 2 1 2 1 N NLP in N N m I S C C RI SC R g α β α β γ − = + + (21a) 2 1 2 1 2 '1 2 1 2 1 mHP in N N m S C C R gI S C C RI SC R g γ α β γ − = + + (21b) M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 104 2 1 2 '1 2 1 2 1 BP in N N m I SC R S C C RI SC R g γ γ α β γ + + ′ = (21c) ' 1 2 1 1 2 m N N o gf C C R γ α β π = (22) ' 1 2 1 N N m CQ g C R α β γ = (23) The sensitivity analysis of both the VM and CM universal filters is also carried out. The Equations 24-26 give the active and passive sensitivities of the VM filter and Equa- tions 27-28 present the sensitivities of the CM filter. 1 2 2 1 2P P mg C C R S S S S S S Sω ω ω ω ω ω ωα β γ= = = = − = − = − = (24) 1 1 N N Q Q Q RS S Sβ α= = = (25) 1 2 2 1 2P P m Q Q Q Q Q Q Q C g C RS S S S S S Sα β γ= = = = = − = − = (26) ' 1 2 1 1 2N mN g C C R S S S S S S Sω ω ω ω ω ω ωβ γα = = = = − = − = − = (27) ' 1 2 1 1 2N mN Q Q Q Q Q Q Q C g C RS S S S S S Sβ γα = = = − = − = − = − = (28) It can be seen that the active and passive sensitivities are not greater than one which is desirable. Figure 6: Non-ideal model of EXCCTA 5 Simulation results In order to establish the workability of the proposed extra X current conveyor transconductance amplifier (EXCCTA). It was designed in 0.18μm parameters from TSMC. The circuit was simulated in spice to measure the important design metrics. The aspect ratios of the transistors are given in Table 5. The supply voltages are kept at VDD = -VSS = 0.9V. The bias current was fixed at Ibias = 100μA. The bias current of OTA was set at 60μA which resulted in a trans- conductance of gm = 0.334mS. The performance param- eters of the EXCCTA are summarised in Table 6. Table 5: Aspect ratios of the transistors Transistor Width (W μm) Length(L μm) M1- M4 3.06 0.72 M5- M7 9 0.72 M9- M23 14.4 0.72 M24- M28 0.72 0.72 M29-M32 3.6 1.8 M33-M40 7.2 1.8 The operation of the inductor simulators is evaluated next. The GIS-1 inductor simulator is tested, the passive component values are selected as R1 = R2 = 4kΩ, C1 = M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 8: Monte Carlo result of GIS-1for 10% deviation in capacitance value Figure 7: Magnitude and phase response of GIS-1 105 50pF and Ibias = 60μA resulting in the inductance of Leg = 0.3mH. The magnitude response of the ideal and simu- lated inductor is given in Fig. 7. To study the effect of pro- cess variability on the performance of the inductor simu- lator Monte Carlo analysis is performed for 10% variation in the capacitance value with Gaussian distribution for 100 runs. It can be inferred from Fig. 8 that there is only slight deviation in the inductance value. To further as- certain the inductor’s performance transient analysis is performed to verify the phase difference between cur- rent and voltage waveforms. The phase difference was found to be 87.2o as given in Fig. 9 which further verifies the behaviour of the synthetic inductor. Figure 9: Transient analysis of GIS-1 The parallel inductor is now designed. The value of the passive elements are selected as R1 = R1 = 4kΩ, C1 = 50pF and Ibias = 60μA resulting in the inductance of Leq = 0.3mH in parallel with Req = 4kΩ. It is to be noted that by ap- propriately selecting the value of R1 the value of parallel resistor can be set without affecting the inductance. The magnitude response of GIS-3 is given in Fig. 10. Figure 10: Magnitude response of GIS-3 6 Applications of the proposed inductance simulators To examine the applicability and feasibility of the pro- posed inductor simulators in practical applications they are utilized in numerous applications. The pure inductor simulator GIS-1 is utilized in the design of third order But- terworth ladder filter [5] as shown in Fig. 11. The transfer function of the filter is given in Equation 29. The passive elements of the filter are selected as C1 = C2= 0.1 nF, Rs = 1kΩ, RL = 1kΩ and L1 = 60 uH. The resistors Rs and RL are the source and load resistances, respectively. The induc- tor in the passive implementation is replaced by the ac- tive GIS-1 Fig 3(a). The components of GIS-1 are selected as R1 = R2 = 4kΩ and C1 = 10 pF to get Leq = 60uH for the active inductor. The Ideal and simulated filter response are given in Fig.12. It can be deduced that the ideal and simulated curves bear close resemblance. A current mode multifunction filter [27] is also de- signed using the GIS-1. The parallel passive RLC filter is shown in Fig. 13. The filter is designed for -3dB cutoff frequency of 2.054 MHz by selecting components val- ues as Cf = 10pF, Rf = 10kΩ and Leq = 0.6 mH. The pas- Figure 11: The third order Butterworth filter (29) M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Table 6: Performance metrics of EXCCTA in Fig. 6 Voltage Gain 1.005 Current Gain ( /ZP XPI I+ ), ( /ZN XNI I+ ), 0.9998 Current Gain( /ZP XPI I− ), ( /ZN XNI I− ), 0.964 Voltage Transfer Bandwidth 756.83MHz Current Transfer Bandwidth ( ,P NZ Z+ + ) 774.46 MHz Current Transfer Bandwidth ( ,P NZ Z− −) 711.21 MHz DC Voltage Range ±650mV DC Current Range ( , P NZ Z ) ±140μA DC Current Range ( ,P NZ Z− −) ±60μA X Node Impedance (RX) 39.940Ω X Node Inductance (LX) 2.285μH ( , P NZ Z ) Node Impedance 186.547kΩ ( ,P NZ Z− −) Node Impedance 176.554kΩ 106 sive inductor in the filter is replaced by active inductor GIS-1. The components of GIS-1 Fig. 3(a) are selected as R1 = R2 = 4kΩ and C1 = 100 pF to get Leq = 0.6 mH. The ideal and simulated frequency response of the filter is given in Fig. 14. Figure 14: Frequency response of current mode multi function filter 1 2o eq f f L Cπ = (30) The two passive elements based inductor simulator GIS-3 is utilized in the design of voltage mode second order high pass filter as presented in Fig. 15. The trans- fer function and expression for frequency of the filter are given in Equations 31-32. The passive element val- ues for the passive filter are selected as Cf = 80 pF, Rf = 2kΩ and Leq = 0.6 mH which corresponds to -3dB cutoff frequency of 726.439kHz. To realize the required in- ductance the passive elements of the GIS-3 Fig. 3(c) are chosen to be R1 = 4kΩ and C1 = 100 pF to get L=0.6mH for GIS-3. The ideal and simulated response of the filter are given in Fig. 16. Figure 15: Voltage mode HP filter 2 2 1 1 out in f f eq f V S V S S C R L C = + + (31) 1 2o eq f f L Cπ = (32) Figure 16: Frequency response of Voltage mode filter Now the lossy parallel RL inductor GIS-4 is used in the design of second order current mode HP filter. The pas- sive prototype of the filter is presented in Fig. 17 and the transfer function and pole frequency is given in Equations 33-34. The filter is designed for -3dB cutoff frequency of 918.88 kHz by choosing Cf = 50 pF, Req = 4kΩ and Leq = 0.6 mH. The parallel Req∥Leq in the passive prototype are replaced by parallel RL active inductor simulator GIS-4 Fig.3 (d). The GIS-4 is designed with R1 = R2 = 4kΩ and C1 = 100 pF. The ideal and simulated values are given in Fig. 18. To test the signal processing M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 12: The response of third order Butterworth filter Figure 13: Current mode multi function filter 107 capability of the filter transient analysis is performed. A sinusoidal current signal with 80μA p-p is applied to both filters with ideal passive elements and filter with simulated RL. The results are shown in Fig. 19. It is clear that the ideal and simulated curves follow each other closely verifying the correct functioning of the GIS-4 simulator. 2 2 1 1 out in f f eq f I S I S S C R L C = + + (33) 1 2o eq f f L Cπ = (34) Figure 17: Current mode high pass filter Figure 18: Frequency response of Current mode high pass filter Figure 19: Transient analysis of Current mode high pass filter 7 Verification of the Proposed Universal Filters The proposed MISO VM filter is tested. The filter is de- signed for -3dB cutoff frequency of 2.054MHz by select- ing C1 = 20 pF, C2 = 20 pF, R1 = 5kΩ and R2 = 5kΩ. The resulting quality factor of the filter is found to be 1.29. The response of the filter is presented in Fig. 20. The re- sponse of the AP filter is given in Fig. 21. The simulated pole frequency of the is found to be 1.998MHz which translates in to 3.21% error this is due to parasitic ele- ments discussed above. To investigate the signal pro- cessing capabilities of the filter transient analysis is also performed for the BP configuration. It can be inferred from the Fig. 22 that the filter performs well. The total harmonic distortion(THD) of the filter for band pass configuration is also calculated which is found to be perfectly within acceptable limit for wide input voltage range as shown in Fig. 23. The THD remains within 1% till 200mV input voltage. Figure 20: Simulated characteristics of the MISO VM filter Figure 21: Simulated characteristics of the MISO VM AP filter M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 108 The effect of process variations on the proposed filter is studied by performing Monte Carlo analysis of the HP response of the filter. The analysis is carried out for 10% deviation in the two capacitor values adopting the Gaussian distribution. The result for 50 runs given in Fig. 24 shows that the filter functions well with minute deviations that can be accommodated by adjusting the bias current of the OTA for precise frequency control. Figure 24: Monte Carlo analysis of the HP filter for 10% deviation in capacitance values Table 7: Comparison of MISO filters available in the literature with the proposed filter S. No. Type of Filter Active Block Used(No.) No. of R+C No. of grounded C+R Matching Condition Electronic Tunability Inverting Input Needed Low output Impedance [29] MISO (VM) CCII+ (3) 2+2 0+0 No No No (Except for AP) No [30] MISO (VM) DVCC (3) 4+2 2+3 No (Except for AP) No No No [31] MISO (VM) CCTA (1) 2+2 0+0 No Yes No No [32] MIMO (VM) DVCC (1) 2+2 0+0 Yes No No No [33] MISO (VM) DOCCCII (2) 0+2 0+0 No Yes No (Except for AP) No [34] MISO (VM) VD-DIBA 1+2 0+0 No Yes No No [35] MISO (VM) CDBA (2) 4+2 0+0 Yes No No Yes [36] MISO (VM) DDCC (2) 2+2 2+1 No No No No [37] MIMO (VM) FDCCII (1) 3+2 1+1 No No No (Except for AP) No [38] MISO (VM) DDCC (3) 2+2 2+2 No No No Yes Proposed MISO (VM) EXCCTA (1) 2+2 1+0 No Yes No (Except for AP) Yes M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 23: Total harmonic distortion of the band pass filter configuration Figure 22: Transient analysis of the band pass filter 109 Tunability is an importance feature of filters [28], this at- tribute enables a filter to be useful at different frequencies without requiring any alteration in the passive compo- nents values. The pole frequency of the proposed filter can be adjusted by varying the bias current of the OTA. The LP response of the filter is plotted for different bias currents as shown in Fig. 25. It can be seen from the figure that the bias current slightly effects the quality factor of the filter as can be deduced from Equations (13-14) . To realize a unity quality factor the resistance R1 should be adjusted accord- Figure 26: Simulated characteristics of the MISO VM BP filter for different quality factors Table 8: Comparison of CM SIMO filters available in the literature with the proposed filter S. No. Type of Filter Active Block Used(No.) No. of R+C No. of grounded C+R Matching Condition Electronic Tunability High output Impedance [39] Fig. 3 SIMO (CM) CBTA (1) 2+2 2+2 No Yes No [40] SIMO (CM) CDTA (1) 2+2 2+0 No Yes No [41] SIMO (CM) DV-DXCCI (1) 2+2 2+2 No No Yes [42] SIMO (CM) UCC (3) 2+2 2+2 No No Yes [43] SIMO (CM) CCCII (3) 0+2 2+0 No Yes Yes Proposed SIMO (CM) EXCCTA (1) 1+2 1+2 No Yes Yes M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 27: Simulated characteristics of the SIMO CM filter Figure 28: Simulated characteristics of the SIMO CM AP filter Figure 25: Simulated characteristics of the MISO VM LP filter for different bias currents 110 ingly. The quality factor of the proposed filter can also be tuned independent of the pole frequency by varying the resistance R1 as can be seen in Figure 26 which gives the plot of Q for different values of resistance R1. A comparison is provided in Table 7 to compare the proposed VM MISO filter with the other state of the art filter structures. Lastly, the CM SIMO filter is validate by designing it for -3dB cutoff frequency of 2.204MHz by selecting C1 = 20 pF, C2 = 20 pF, R1 = 3.61 kΩ and OTA bias current of 50μA. The frequency response of the filter is given in Fig. 27 and the AP response is shown in Fig. 28 The filter is compared with other exemplary SIMO filter topolo- gies to highlight its advantages as shown in Table 8. 8 Experimental Results The EXCCTA can be easily implemented using commer- cially available integrated circuits AD844 and LM13700. The possible implementation of GIS-1 using only two AD844 and one LM13700 IC is shown in Fig. 29. The ICs are supplied with a bias voltage of ±10V, the Ibias of the OTA is fixed at 372µA. The passive components values are chosen to be R1 = R2 =1kΩ and C1 = 10 nF result- ing in the inductance of L=672μH. To test the circuit a triangular waveform with 2V p-p at 17kHz is applied through R2 and R3 to convert it in to corresponding in- put triangular current. A square wave form is obtained across the inductor. The oscilloscope output is shown in Fig. 30 which validates the correct functioning of the active inductor. Figure 29: Implementation of the GIS-1 from the com- mercially available ICs To further validate the VM filter it is implemented on breadboard using AD844 and LM13700 ICs. The filter implementation is given in Fig. 31 (a-b). The filter is de- signed for -3dB frequency of 343.199kHz by selecting M. Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 Figure 31: Experimental setup of the VM filter from the commercially available ICs (a) Block Diagram (b) Bread board implementation (b) (a) passive components values equal to R1 = R2 =1kΩ, C1 = C2 =1nF and Ibias = 232.5µA. The ideal and experimen- tally calculated response of the filter is presented in Fig. 32. The measured frequency of the filter is found to be 321kHz leading to an error of 6.46%, this discrepancy arises due to non-idealities present in the EXCCTA and also due to the parasitics introduced by connecting leads and breadboard, nonetheless it verifies the prac- tical feasibility of the proposed VM filter. Figure 30: The experimental result of the inductor simulator 111 Figure 32: The ideal and experimental results of the VM MISO filter Figure 33: Time domain analysis of LP response (a) 1kHz (b)321 kHz (c) 600 kHz (a) (b) (c) signal of 60mV p-p at frequencies of 1kHz, 321kHz and 600kHz. The filter output obtained on the oscilloscope for LP configuration is presented in Fig. 33 (a-c). 9 Conclusion In this research, a new active element namely EXCCTA is proposed. The EXCCTA is used to design six topolo- gies of lossy and lossless active inductors. Additionally, to further elaborate its versatility two universal VM and CM filter structures employing a single EXCCTA are also proposed. The inductor simulators make use of single EXCCTA, grounded passive elements, requires no pas- sive components matching and are perfectly tunable. The voltage mode filter is obtained by slightly modify- ing the proposed series inductor. The VM filter makes use of canonical number of passive elements and has low output impedance. The CM filter is SIMO type and utilize only three grounded passive elements for imple- mentation. Both the proposed filter structures enjoy low sensitivities, inbuilt tunability and orthogonal con- trol of quality factor and pole frequency. The non-ideal analysis of the inductor simulators and filter structures is also performed. The simulations are performed in 0.18μm parameters from TSMC to verify the theoreti- cal analysis. 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Faseehuddin et al; Informacije Midem, Vol. 48, No. 2(2018), 97 – 113 114 115 Original scientific paper  MIDEM Society The Design of Broadband LNA with Active Biasing based on Negative Technique Gang Wang, Jiarui Liu, Shiyi Xu, Jiongjiong Mo, Zhiyu Wang, and Faxin Yu School of Aeronautics and Astronautics, Zhejiang University, Hangzhou, China Abstract: In this paper, we present a broadband LNA based on an improved negative feedback design. With the adjustment of the negative feedback inside the chip, the LNA achieves a planarized gain and an optimized operating bandwidth from 0.2 GHz to 4 GHz. To guarantee the good performance stability under severe environments, an active biasing is used inside the chip. As a result, effective compensations for the fluctuation of the supply voltage and the temperature variation are achieved. The LNA chip uses GaAs pHEMT at 0.25-μm technology node and SIP package technique. This broadband LNA shows good performances, including gain of about 15 dB, gain flatness of less than 1dB, and noise figure of less than 1.5 dB. The packaged size of this broadband LNA is 3 mmX3 mmX1 mm. Keywords: feedback network; broadband LNA; active biasing; SIP package Načrtovanje širokopasovnega LNA z aktivnim napajanjem na osnovi negativne tehnike Izvleček: Članek predstavlja širokopasovni LNA na osnovi izboljšane negativne povratne zanke. Nastavljiva negativna zanka v čipu omogoča LNA doseganje ojačenja in optimalne pasovne širine med 0.2 in 4 GHz. Za doseganje dobrih lastnosti v neugodnem okolju je uporabljeno aktivno napajanje v čipu. Doseženo je efektivna kompenzacija fluktuacij napajalne napetosti in temperature. LNA čip uporablja GaAs pHEMT v 0.25 μm tehnologiji in SIP ohišje. LNA izkazuje dobre lastnosti vključno z ojačenjem 15 dB, stabilnostjo ojačenja pod 1 dB in šumom pod 1.5 dB. Velikost ohišja je 3 mmX3 mmX1 mm. Ključne besede: povratno omrežje; širokopasovni LNA; aktivno napajanje; SIP ohišje * Corresponding Author’s e-mail: jrliu@zju.edu.cn Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), 115 – 120 1 Introduction With the rapid evolution of wide-bandwidth technol- ogy, more attentions are drawn by the design of wide- band receivers which are able to cover a wide range of frequency standards [1]. The main difficulty in designing a wideband LNA is to achieve high gain, low noise figure and excellent lin- earity simultaneously. There were various architectures reported in the literature to achieve wideband LNAs, including distributed LNAs, balanced LNAs, common gate LNAs and feedback LNAs. The first three share fea- tures of small input and output reflection coefficient while they have disadvantages such as low gain and high power dissipation [2, 3]. The feedback is featured for tradeoff among several performance specifications, which is popular in wideband LNA designs. There are many researches which have designed wideband LNAs utilizing feedback technology. However, only LNA die is considered in their works, and no parasitics of bonding wire and package are taken into account. Biasing cir- cuit also has influence on the performance of LNA. The current mirror with temperature compensation is the most popular biasing, but it does not take the fluctua- tion of power supply into consideration [4]. In this paper, we report a broadband LNA with an ac- tive biasing based on an improved negative feedback. In order to extend the bandwidth, a feedback unit is used between the drain and gate, and a RC cell is add- ed at the source. The influence of external parasitics is introduced by applying equivalent circuit elements of bonding wire and ESD circuits. The stable performanc- es under different severe conditions are achieved via an active biasing inside LNA die, which can compen- 116 G. Wang et al; Informacije Midem, Vol. 48, No. 2(2018), 115 – 120 sate the fluctuation of environmental temperature and the supply voltage variation. The LNA described in this paper exhibits a broad band- width of more than 20 octaves, from 0.2 GHz to 4 GHz, covering several communication standards like GSM, GPS, TD-SCDMA, WCDMA, and Bluetooth. 2 Design principle and approach As the circuit diagram showed in Fig. 1(a), the wide- band LNA in this paper is composed of Cascode ampli- fier, feedback circuit, active biasing circuit, ESD circuit, source degeneration inductance, input and output matching networks. We choose the Cascode topology for priority to eliminate miller effect and to increase re- verse isolation [5]. A load capacitor Cg is added at the gate of M2 to improve power gain. And a resistor Rg is added in series in order to minimize the deterioration of stability due to the introduction of Cg. The equiva- lent element of bonding wires (b1, b2, b3), pads(p1, p2, p3) and the ESD circuits are also considered in our simulation. (a) (b) Figure 1: (a) The electric circuit diagram of LNA Ampli- fier (b) A novel active biasing circuit The active biasing circuit of the presented LNA is shown in Fig. 1(b). Q2 and Q5 work as switching transistor. When VEN is set at low voltage, the switching transistor is in off-mode, and only an infinitesimal current exists in biasing circuit. While in on-mode when VEN is set at high voltage, DC bias is supplied for the operation of LNA. Q6 works as diode for voltage stabilization. E-mode transistor Q1 and Q3, resistor R1, R2 and R3 form the temperature compensation circuit. When the ambient temperature decreases, the drain current of Q1 increases. As a result, the potential at point A de- creases. Thereby, the gate-to-source voltage and the source current of Q3 decrease. And the voltages on R3 which is also the gate-to-source voltage of Q1 would decrease. This results in the restriction of the drain cur- rent growth of Q1, which benefits the performance stability of the LNA. Similar temperature compensation phenomenon can be achieved when ambient temper- ature increases. The temperature compensation circuit also works as a supply voltage regulation circuit. When Vbb decreases, potential would decrease at point A and B. Therefore the gate-to-source voltage of Q3 would decrease, which as we mentioned above, results in a decreasing of gate-to-source voltage of Q1.Then the drain current of Q1 would increase, which restricts the decrease of potentials at point A and B. In conclusion, the active biasing circuit can compensate the temperature and voltage fluctuations effectively. Therefore, a stable output voltage can be achieved and stable performance at different severe conditions is guaranteed. According to the feedback circuit of LNA, traditional negative feedback circuit is composed of a single resis- tor between drain and gate, which couples part of sig- nal from output to input, and enhances the bandwidth along with the sacrifice of gain [6, 7]. In our design, we exhibit an improved negative feed- back to further extend the bandwidth and improve the high-frequency performance of the LNA. As shown in Fig. 2(a), a capacitor Cf is introduced for the isolation of DC signal. And an inductor Ld is added at drain for the compensation of the capacitive portion of output impedance at high frequency, which extends the oper- ating frequency range. For simplification, we analyze the contribution of Zd and Zp, respectively. The simplified equivalent circuits are shown in Fig. 2(b) and 2(c). RFin Vdd RFout VEN Li Lp Vbb Active Biasing RfCf Cg Rg Ld Lo Co RpCp M2 M1Vgb Vgtb1 b3 b2 p1 p3 p2 Ci ESD ESD Circuit Vdd ESD R1 R2 R3 R4 Q2 Q3 Q4A B Q1 Q5 Q6 Vbb Vgb VEN VEN Vdd Vgt R5 R6 VEN VEN Q7 Q8 117 Figure 2: (a) Improved negative feedback amplifier (b) The equivalent circuit of LNA with Ld (c) The equivalent circuit of LNA with Ld and RC cell From Fig. 2(b), we know // f in out gs s f Z V V Z Z Z = + (1) ( )[ // ]out out ds s gs fV I i Z Z Z= − + (2) ( )( // )ds d gs s fout out out m f ds ds d Z Z Z Z ZVR I g Z Z Z Z + + = = + + (3) Where 1 / /ds ds ds Z R sC = (4) The inductor Ld (Zd in equation (3)) is introduced to effectively eliminate the capacitive parts of load resist- ance, and as a result to achieve a broad bandwidth, as shown in curve B in Fig. 3. As shown in Fig. 2(c), Zp at source consists of an induc- tor Lp and a RC parallel cell. The degeneration induc- tor Lp is introduced to reduce the difference between optimum impedances of NFmin and Gainmax, and to improve the LNA performance on NF and Gain simulta- neously. As for the RC cell, the capacitor Cp behaves as open at low frequency and gain attenuation exists due to the resistor Rp. While at high frequency, the imped- ance of Cp is close to short and no signal flows through Rp. Therefore the gain flatness of LNA is improved. The EM simulation of the presented LNA with novel negative feedback circuit is carried out using ADS. The gain performance comparison with traditional nega- tive-feedback LNA as a function of frequency is shown in Fig. 3. Compared with curve A, operating from 0.2 GHz to 2.1 GHz, the bandwidth of curve B is extend- ed pronouncedly, covering 0.2 GHz to 3.6 GHz, due to the introduction of Ld. From the comparison between curve B and C, the latter attains more ideal gain flatness covering 0.2 GHz to 4 GHz due to the gain attenuation at low frequency by the introduction of paralleled RC cell at source. Figure 3: The Gain characteristic of LNA with various feedbacks, in which A: traditional feedback, B: feedback with additional Ld, C: presented novel feedback 3 Implementation and measurements The proposed LNA is constructed by an LNA die and several lumped elements including the output imped- ance matching inductor and capacitor, a decoupling capacitor and a DC blocking capacitor. SIP technique is used for integration. Based on the tradeoff between gain and output power linearity, we use a pair of 16  40 μm GaAs pHEMT with Cascode configuration on the LNA die. Rf RFin Vdd RFout Cf Ld Zf Zp Cp Rp Lp Zf RFin RFout gmv1 ZLZs Iin Iout + - VoutVin + - Zd Zds ids Zgsv1 + - Zpv2 + - Zf RFin RFout gmv1 ZLZs Iin Iout + - VoutVin + - Zd Zds ids Zgsv1 + - (a) (b) (c) G. Wang et al; Informacije Midem, Vol. 48, No. 2(2018), 115 – 120 118 The broadband LNA die is fabricated by 0.25-μm GaAs pHEMT process with the size of 0.8 mm  0.75 mm, including all RF and DC pads, as shown in Fig. 4(a). In the design of LNA layout, ESD circuits are introduced at each DC supply pads for electrostatic protection. The substrate of the SIP package consists of 4 metal lay- ers. On the bottom metal layer there locates the LGA (Land Grid Array) pads, which have smaller parasites compared to traditional pins [8]. The second and third metal layers are patterned for biasing DC signal. The top layer is for RF signal. The total size of substrate is 3 mm  3 mm. (a) (b) Figure 4: (a) Layout of LNA die (b) Packaged LNA In order to minimize the size of the LNA chip, we use an inductor as the input matching element on the LNA die and put the input block capacitance, the output matching network which consists of a low-pass LC cell, an inductor Lo, and a capacitor Co on the package sub- strate. When packaging is finished, we measure the LNA in detail under the bias condition Vdd=3.3 V and Vbb=3.3 V at room temperature. Fig. 5(a) shows the measured S-parameters. From 0.2 GHz to 4 GHz, LNA shows no- less-than 15 dB small signal gain, and less than -10 dB reflection loss at both input and output. The gain flat- ness within operating frequency band is about 1.2 dB. Fig. 5(b) shows the measured NF, P-1dB and IIP3. The NF of the LNA is less than 1.6 dB, while P-1dB is 17 dBm. The OIP3 is 19 dBm, from which we deduct the gain with 15 dB, therefore the IIP3 is 4 dBm. (a) (b) Figure 5: (a) The S-parameter of LNA. (b) The NF, P-1dB and OIP3 of LNA. To explore the advantages of the biasing circuit inside the LNA die, we measure the S-parameters and the NF at different temperature conditions (-40℃, 25℃, 85℃), as shown in Fig. 6(a) and 6(b). With the variation of tem- perature from -40℃ to 85℃, the fluctuation of gain and NF are both within ±0.4 dB, which validates the tem- perature compensation of the active bias. The comparison of published measurement results of wideband LNAs and this work is shown in Table 1. The bandwidth of this work is up to 20 octaves while main- taining a superior gain flatness, a low NF and a good linearity. 4 Conclusion This paper presents a broadband LNA based on the im- proved negative feedback design. GaAs pHEMT at 0.25- G. Wang et al; Informacije Midem, Vol. 48, No. 2(2018), 115 – 120 119 obtained. The presented LNA can be applied in severe conditions to cover several communication standards like GSM, GPS, TD-SCDMA, WCDMA, and Bluetooth. 5 Acknowledgment This work was supported by the National Natural Sci- ence Foundation of China under Grant 61604128. 6 References 1. 2. Cho, Kang Fu, and S. Wang, ‘’A 0.4~5.3GHz wideband LNA using resistive feedback topolo- gy,’’ IEEE Mtt-S International Conference on Numeri- cal Electromagnetic and Multiphysics Modeling and Optimization (2016) 1. 3. P. Bousseaud, M. A. Khan and R. Negra, “Induc- torless wideband LNA with improved input Matching using feedforward technique,” 2016 46th European Microwave Conference (EUMC), pp. 1027-1030, 2016. 4. Wang, Minghua, et al. “A power reduction tech- nique for wideband common gate low noise am- plifers.” IEEE, International Midwest Symposium on Circuits and Systems IEEE ,pp. 969-972, 2014. 5. Weinberg, Elena K., and M. R. Stan. “SymmTop: A Symmetric Circuit Topology for Ultra Low Pow- er Wide Temperature-Range Applications.” Vlsi IEEE:585-590, 2015. 6. S. N. I. S. Zulkepli and T. Z. A. Zulkifli, “Asymmetric T-coil, resistive feedback cascode low noise am- plifier for ultra wideband receiver,” 2015 IEEE Inter- national Circuit and Symposium (ICSyS), PP. 11-16, 2015. 7. A. P. Kulkarni and S. Ananthakrishnan, “1 to 3 GHz Wideband Low Noise Amplifier design,” Comput- ers and Devices for Communication (CODEC), 2012 5th International Conference, pp. 1-4, 2012. Figure 6: (a) The S-parameter of LNA. (b) The NF, P-1dB and OIP3 of LNA. (a) (a) Table 1: Performance comparison of wideband LNA Ref Device Tech Freq(GHz) G (dB) NF(dB) ΔG (dB) VDC (V) P-1dB (dBm) IIP3 (dBm) Pdiss (mW) [9] 0.5 μm GaAs pHEMT 2.5~5 17 2.4~3 1.6 1.5 -2 2.3 33 [10] 0.18 μmCMOS 0.9~1.1 10.7 1.3 None 2.5 18.4 3 50 [11] 0.18 μmCMOS 2.5~6.8 11.5 4.2 4 1.8 None None 8.1 This Work 0.25 μm GaAs pHEMT 0.2~4 15 1.6 1.2 3.3 17 4 33 μm technology node and SIP package technique are applied. The LNA consists of a pair of 16  40 μm GaAs pHEMTs with Cascode configuration and a novel nega- tive feedback circuit between drain and gate which re- markably extends the operation bandwidth. An active biasing technique is applied to effectively compensate the fluctuation of the supply voltage and the tempera- ture variation. The designed LNA has achieved a broad bandwidth of up to 20 octaves from 0.2 GHz to 4 GHz while maintaining a gain flatness of less than 1.2 dB. A low NF of less than 1.6 dB and a good linearity are also G. Wang et al; Informacije Midem, Vol. 48, No. 2(2018), 115 – 120 120 8. Z. Zhang, A. Dinh and L. Chen, “A 2 GHz band- width LNA using resistive feedback with added inductor,” 2012 IEEE International Conference on Ultra-Wideband, pp. 375-378, 2012. 9. J. Y. Jeon, S. G. Kim, Y. S. Eo and S. H. Jung, “A Trans- former feedback wideband CMOS LNA for UWB application,” 2015 Asia-Pacific Microwave confer- ence (APMC), pp. 1-3, 2015. 10. Y. Peng, K. Lu, W. Sui, et al, “A low power 2.5-5GHz low-noise amplifier using 0.5μm GaAs pHEMT technology,” Journal of Semiconductors, 33(10): vol. 33, no. 10, 2012. 11. B.-K. Kim, D. Im, J. Choi , and K. Lee, “A 1 GHz 1.3 dB NF + 13 dBm output P1dB SOI CMOS low noise amplifier for SAW-less receiver ,”in Proc. IEEE Ra- dio Freq. Integr. Circuit Symp. Dig. Montral, QC, pp. 9-12, Jun.2012. Arrived: 24. 02. 2018 Accepted: 22. 05. 2018 G. Wang et al; Informacije Midem, Vol. 48, No. 2(2018), 115 – 120 121 Original scientific paper  MIDEM Society Real-Time Random Number Generation with Ring Oscillator Based Double Physically Unclonable Function Seda Arslan Tuncer Firat University, Department of Software Engineering, Elazig, Turkey Abstract: Integrated Circuit (IC) is a semiconductor wafer that is fabricated for millions of components. Although it is accepted that the same chemical properties are observed in the same type of ICs produced within the processes of wafer production, masking, etching, doping, atomic diffusion, ion implantation, metallization and packaging steps, these properties differ at microscopic levels. For example, the propagation delay is different in two logic elements in the same integrated circuit, and the silicon distribution in each LE is not equal. These differences have created the concept of Physically Unclonable Function (PUF). PUF is a function that creates values specific to the physical environment in which it operates. This article presents the implementation of a ring oscillator- (RO) based PUF design in two different ICs to generate random numbers. Two different FPGA (Field Programmable Gate Array) cores were used in the proposed structure, and PUF structures were implemented on these hardware elements. The raw random numbers obtained by the generated system were post-processed to be used in applications (e.g. encryption, game programming). The study used Von Neumann and hash functions for post-processing. NIST and Autocorrelation tests were also administered to check the validity of the obtained random numbers. Keywords: Random number generation; Field programmable gate arrays; physically unclonable function. Generator naključnih števil v realnem času z dvojno funkcijo nekloniranja na osnovi obročnega oscilatorja Izvleček: Integrirana vezja so narejena na polprevodniški rezini. Kljub enakim kemijskim postopkom izdelave se lastnosti integriranih vezij na mikro nivoju razlikujejo. Na primer, enaki logični elementi imajo različne zakasnitve in drugačno razporeditev silicija. Te razlike so ustvarile koncept fizikalno neklonirane funkcije (PUF). PUF generira vrednosti glede na okolje delovanja. Članek predstavlja obročni oscilator na osnovi PUF v dveh različnih integriranih vezjih za generacijo naključnih števil. Za demonstracijo sta bila uporabljena dva FPGA jedra s PUF strukturami. Za uporabo v aplikacijah so bila naključna števila post procesirana na osnovi Von Neumann študije. Opravljeni so bili tudi avtokorelacijski testi in NIST. Ključne besede: generacija naključnih števil; FPGA; fizikalno neklonirane funkcije. * Corresponding Author’s e-mail:satuncer@firat.edu.tr Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), 121 – 128 1 Introduction 1.1 Background The physically unclonable function (PUF) generates a response to the given challenge signals. The basic fea- ture of the PUF is that the generated response is ran- dom and unpredictable. In other words, the response is random because the characteristics of the basic hard- ware (such as LE–Logic Element) used in PUF imple- mentations are different from those of the other struc- tures. Even if a PUF design uses the same challenges, it receives a different response, which indicates that the PUF hardware is unclonable [1]. There are two main implementation categories for PUF: authentication and secret key generation [2]. Au- 122 S. A. Tuncer; Informacije Midem, Vol. 48, No. 2(2018), 121 – 128 thentication is performed in two steps. In the first step, the function generates a response against challenges, and stores it in a database. This phase is called enrol- ment. The second phase is verification. In this step, the response generated by the PUF for a challenge in the database is compared with the one stored in the data- base. The secret key generation has two stages: initiali- zation and regeneration. In initialization, responses are generated against challenges, and the same challenge is applied to the PUF in regeneration. In the second phase, a key is generated to create the same response using a hash function and a decoding operation like BHC (Bose–Chaudhuri–Hocquenghem) based on the value generated in the first phase. There are several PUF structures that have been pro- posed in the relevant literature. Generally, PUFs are in- vestigated under four groups: arbiter, memory-based, optical, and ring oscillator (RO)-based. The underpin- ning idea of the arbiter PUFs is to measure the delay times between two signals. The Arbiter PUF structure transmits a pulsing signal to the output via two different routes. There are key blocks such as mux on the route. Although the researcher spent effort to design the two routes symmetrically, the delays in these routes have different times due to the production differences and characteristics. The arbiter gives the output 0 or 1 by examining the route that first sends the pulsing signal [3]. The static random-access memory (SRAM) type PUF is the most common memory-based PUF structure. The SRAM cell outputs consist of two inverters that are par- allel to each other. The researcher gave the same char- acteristics to these inverters to the best ability. Due to manufacturing differences, the output value created by the SRAM cell will be different every time it receives power. These properties enabled SRAM cells to be used as PUF [4]. In optical PUF structure, which is also known as Physical One-Way Functions (POWFs), bubble-filled transparent epoxy is applied on the wafer. The pattern that emerges in this process is polished with laser. Be- cause this pattern depends on the wavelength as well as laser angle, wafer material, wafer thickness and the characteristic of epoxy, each integrator has a unique pattern, and accordingly, a unique identity or signature [1, 5]. The RO-based PUF structure was proposed by Suh et al. [2]. This scheme simply generates a response specific to each challenge input based on the signals addressing the input of delay elements. This difference results from different physical and chemical properties of delay elements that emerge during the production. It is possible to perform key generation in real random numbers with all PUF structures mentioned above. However, there are certain criteria (e.g. reverse engi- neering, emulation, man-in-the-middle attack, recon- figuration) that must be satisfied for random key gen- eration to be used in computer science [6]. Past studies have proposed many RO-based PUF structures [6–8]. Indeed, the RO-PUF has very favorable statistical prop- erties (output bias, intra-uniqueness and steadiness) when implemented in both FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit) [7]. A relevant study proposed an RO-based PUF that performed number generation with the help of [9] and Gray coding by counting RO outputs with a counter. There are also other RO-based PUF struc- tures in the literature that aim to increase the qual- ity of random numbers by introducing periodic and non-periodic signals to challenge inputs. Chaos-based maps were used for non-periodic signals while Linear Feedback Shift Register (LFSR) structures were used for periodic signals [6, 10]. In this study, the researcher has suggested an alternative grouping based RO-PUFs for the classic RO-based PUF structure. The output genera- tion mechanism of these systems depends on the fre- quency order of ROs of a group with two phases [11]. Another study presented a transient effect ring oscilla- tor- (TERO) based PUF structure, and proved that this structure guaranteed high stability [12]. The double PUF structures proposed in the literature are based on arbiter PUF [13-15]. A double PUF struc- ture was proposed to improve the unpredictability of responses [13]. In this study, the researcher used N-XOR Arbiter PUFs for unpredictable structures to sample the numbers from each arbiter PUF output with R-S type flip-flops, and then give them as inputs to an n-input XOR circuit. There were different output functions proposed for n = 2, n = 3 and n = 4 values. Steadiness, randomness, and cost were evaluated for each random number sequence. Another study sampled a double ar- biter PUF structure using R-S type flip-flops and gave it as input to a two-input XOR circuit [14]. The difference between this study and the study presented in [13] was that this study applied Von Neumann post-processing to the produced numbers. The study also used Die- hard test suite to measure the randomness of obtained numbers. A previous study [15] suggested a random number generator that had more than two PUF struc- tures. This study has compared the outputs of each PUF circuit in a separate evaluation unit that did not include post processing, and performed number generation. 1.2 Motivation and contribution This article, unlike the studies in literature, presents a design for random number generation by a RO-based Double PUF structure. The PUF circuits in the proposed structure were implemented on two separate FPGA cores. It is recommended that the characteristics of the Double PUF structure should be investigated so that the generated random numbers can be used as a key. 123 Thus, researchers should meet the requirements in Ta- ble 1. The study administered Diehard, NIST, and FIPS tests in addition to Scale index and autocorrelation to meet these requirements. In order to meet these requirements, the study ap- plied Von Neumann and hash-based post-processes to the random numbers that were generated by the new structure. The statistical weaknesses of generated numbers were determined by post-processing applica- tions. NIST test suite and autocorrelation coefficients enabled the researcher to examine the quality of the numbers produced in this study. The contributions of this study to the literature are summarized as follows: - Random number generation with PUF on two dif- ferent FPGA. - Transformation of the RO-based PUF structure into Double PUF structure - Unlike the multi-PUF structures suggested in the literature, Von Neumann and hash-based post- processing procedures were used and the statis- tical properties of generated numbers were im- proved. - Double PUF structure revealed better perfor- mance than the PUF structure. Table 1: The Necessary Security Requirements for The Random Number Generator (RNG) R1 Random numbers should not show any statisti- cal weakness. R2 Knowing the sub-array of random numbers should not allow the calculation or estimation of initial and consecutive random numbers. R3 If the internal state value of the RNG is known, or even if it is unknown, it should not be pos- sible to calculate previous random numbers with the possibility of being estimated. R4 If the internal state value of the RNG is known, or even if it is unknown, it should not be possi- ble to calculate next random numbers with the possibility of being estimated. 1.3 Study organization Section 2 presents the basic components for real ran- dom number generation and the RO-based PUF struc- ture. The double PUF structure that is proposed in the study as well as its implementation are presented in Section 3 while Section 4 describes the post processing operations. The results of implementation are given in Section 5. In the last section, the researcher evaluated the results. 2 True Random number generation In real random number generators, random numbers are generated with the help of a physical noise source. The properties and randomness of random numbers generated by true random number generator (TRNG) depend on the randomness of physical processes. The physical noise source is random and its behavior is unpredictable, both of which reveal that the numbers produced are also random and unpredictable. How- ever, the produced bit array may not show high ran- domness stability, and it may involve statistical weak- ness. To eliminate these weaknesses and produce more stable random numbers, the study maintained post- processing on the bit array. Post-processing operations reduce the amount of bit and eliminate weaknesses. The disadvantage is that TRNG is slow and costly, and it depends on random noise sources. However, TRNGs are frequently used in key generation because they are unpredictable and non-reproducible, and also achieve good statistical properties required for cryptographic applications [16]. Figure 1 shows the basic structure for generating real random numbers. First, the structure samples the signal obtained from the noise source, and then generates the pure random number by subject- ing it to post-processing. Post-processing component is usually benefited to fill the deficiency of DAS( Digi- tized Analog Signal) in TRNG systems. Figure 1: Basic components for TRNG In RO-based random number generators, the study used propagation delay differences of integrated cir- cuits as the noise source. Figure 2 presents the basic structure of a ring oscillator. RO which consists of an odd number of inverters includes a NAND gate to ob- tain the delay of the signals given from the input to the output. This structure proposed by Knuth requires a sampling and post processing circuit to produce true random numbers [17]. The quality of random numbers generated by TRNGs depends on the number of oscil- lators, sampling frequency, and number of inverters in oscillators [17]. Figure 2: Ring oscillator Previous studies in the relevant literature proposed RO- featured PUF structures to generate random numbers S. A. Tuncer; Informacije Midem, Vol. 48, No. 2(2018), 121 – 128 124 [2, 3]. Figure 3 presents the typical RO-PUF content. The system has two 64x1 multiplexers, sixteen counters of 16-bit, one-comparator and one hundred twenty- eight-ring oscillators. Depending on the characteristics of each inverter, such as temperature and propagation delay, inverter outputs have a random quality. Because of these features, ROs create unpredictable variations even when inverters are implemented on the same integrated circuit. If the frequency of RO oscillations is too high, counters may not count oscillations. For this reason, it is necessary to adjust the number of invert- ers in each RO to ensure proper oscillation frequency. In the RO-PUF design, the frequencies of the output signals with each multiplexer’s challenge can be set f1 and f2. The oscillation numbers of these frequencies are counted by the counter1 and the counter2 in the system. As a result of counting, the comparison circuit gener- ates 0 or 1 according to Eq.1 [18]. 1 21 0ab if f f r otherwise > =   (1) Figure 3: RO-PUF structure 3 Proposed double RO-PUF and implementation Among all the PUF types, an RO-based PUF structure is most suitable for implementation on an FPGA [17]. Ring oscillator design with inverter and nand gate ele- ments was presented by Sunar el al. Ring oscillators de- veloped for random number generation consist of one NAND gate and 13 inverters. The number of inverters set to 13 so that the entropy of the numbers generated in their designs is high [19]. The 13th inverter output is given to the NAND gate as an input by feedback. The first input of the NAND gate is driven by a multiplexer hardware. With an externally applied excitation signal to the multiplexer’s challenge, the RO output becomes a square wave signal. Figure 4 presents the design of a ring oscillator (in a RO-based PUF structure that was ex- plained in Figure 3) in an FPGA environment. Because the propagation delays of the inverters used in each RO are different, each RO output generates a signal at dif- ferent frequencies. Previous studies implemented the RO-based PUF using 64 or 128 RO. The present study sent the signals obtained from ROs to Mux inputs. The select inputs of the mux are given signals called chal- lenge. The numbers are counted by counters, and the generation of random numbers is completed with a simple comparison. Figure 4: Implementation of RO in the FPGA In this study, random number generation was imple- mented in real time using the RO-PUF structure that is described above in general. The proposed system in this study includes two RO-based PUF structures, as shown in Figure 5.a. Each RO-based PUF contains 64 RO and 64x1 Mux as shown in figure 5. b. Each RO-based PUF was implemented on EP4CE115FC7 and EP4CE22 FPGA cores. Challenge Response R1 R2 CC Random Number, 0/1 Post Processing R1≠R2 a) b) Figure 5: a) The suggested structure b) The PUF1 struc- ture S. A. Tuncer; Informacije Midem, Vol. 48, No. 2(2018), 121 – 128 125 The frequency of the signals given to challenge inputs enabled sampling the numbers that each PUF would generate at the f1 and f2 frequencies. The signals given to the challenge inputs act as the LFSR structures with the characteristic equation x15+x+1. The obtained num- bers were subjected to post-processing to strengthen their statistical properties and use them as a key. The study administered Von Neumann and hash-based post processing to achieve this goal. The new structure proposed in this study is simple, but very effective. Al- though the same challenge signals are given to each PUF structure, they produced different responses. The reason of this difference is the chemical properties (e.g. the properties of germanium and silicium elements, and the changes of their atoms in the cubic lattice structure) and the physical properties during integra- tion of the logic elements (the geometry of transistors, oxide thickness, width) that are the main elements of the FPGA hardware. The researcher recorded the generated numbers in the memory circuit to determine their statistical proper- ties. Also, the system used a 16-bit counter to write the generated numbers on each address of the memory. In each sampling operation, the counter shows the next address of the memory, and a random number is re- corded into this address. The sampling frequency and counter frequency in the system were 50 MHz for each. Quartus software allows the system to save the num- bers in the memory units into a file with the mif or hex extension. The numbers were recorded in a file with the mif extension. Thus, is was an easy procedure to calcu- late the statistical properties of these numbers. Figure 6 shows the designed memory hardware. Figure 6: Recording of generated number into the memory unit 4 Post processing 4.1 Von Neumann Post Processing Post-processing is the oldest and simplest method to eliminate the irregularities in the generated number array. The number generators to which Von Neumann post processing method is applied can generate nor- mally distributed 0 and 1 numbers. The researcher took into consideration the simultaneous pairs that were generated in this post-processing method. If the num- ber is (1, 0), the system generates 1. On the other hand, it generates 0 when the number is (0, 1). (0, 0) and (1, 1) number arrays are ignored. Figure 7 presents the ap- plication of Von Neumann post-processing to the gen- erated random numbers. The entropy of the numbers created by this operation is close to the ideal value. However, this method has a disadvantage, which is the slow rate of number generation due to the elimination of the produced bit arrays. Figure 7: Von Neumann post-processing 4.2 Hash-based Post-processing The H function is based on XOR gate and a post-pro- cessing that achieves more successful results than the XOR. It processes randomly-generated numbers in groups of 16 bits with a base of 2. It subjects the first 8 bits of each 16 bits to the XOR processing. The first eight bits are shifted one left. The result of this opera- tion is subjected to the XOR with the last 8 bits. These operations produce an 8-bit output. The generated number array for post-processing can be accepted D0, D1... D15 and considered 16 bit. Then, 16 bit is divided into two blocks; the first 8 bit being A1 while the last 8 bit being A2. The A1 number array is sub- jected to the XOR by shifting the A1 by one bit to the left. The resultant array is subjected the XOR with the A2 number array and the number generation is achieved. Eq.2 shows the hash function. H(A1,A2)=XOR(XOR(A1,rotateleft(A1,1)),A2) (2) D=0110111011110100, A1=01101110, A2=11110100 rotateleft(A1,1)=11011100, H(A1,A2)= ((11011100 XOR 01101110) XOR 11110100)= 01000110 S. A. Tuncer; Informacije Midem, Vol. 48, No. 2(2018), 121 – 128 126 Figure 8 demonstrates the implementation of Hash post-processing function. The example in this section decreases the number generation rate by 50% with the hash function post-processing. Figure 8: The post-processing of the H function 5 Implementation results The new double RO-based PUF structure proposed in this study is capable of generating infinite random numbers. The generated numbers were stored in the memory to determine their statistical properties. Fig- ure 9 shows the real-time generated numbers that are stored in the memory as a result of the hash-based post-processing while Figure 10 shows the actual num- bers obtained from the output of the memory hard- ware. Figure 9: Real-time generated numbers stored in the memory Figure 11 shows the resource utilization report ob- tained for the PUF1 implemented in the FPGA. The to- tal numbers of LUTs consumed are 1110. Table 2 shows the comparison of the proposed approach with the lit- erature according to FPGA resource utilization. The re- source consumption of the proposed method accord- ing to the table.2 is acceptable average level. Figure 11: FPGA resource utilization of PUF1 Table 2: FPGA resource utilizations Reference Type FPGA resource utilization [20] RO PUF 4096 LUTs [21] LUT based on PUF 1280 LUTs [22] Arbiter PUF 1428 LUTs [23] RO PUF 1288 LUTs [24,26] SR Latch PUF 1024 LUTs [25] SR Latch PUF 2048 LUTs [27] RO PUF 732/1084/1436 LUTs [28] RO PUF 1024/1280/2048/ 2560 LUTs Proposed Double PUF RO PUF 1110 LUTs The study investigated the statistical properties of the numbers generated by both Von Neumann and hash- based post-processing according to NIST test suite. P- value is known as randomness measure in the NIST Test suite. If P-value is 0, numbers are not random at all. it is desirable that this value is greater than 0.01 in com- puter science. With the proposed system according to Table 3, random numbers have produced. Table 3: The results obtained according to NIST test suite   Von Neumann Hash Raw bits Frequency Monobit Test 0.715 0.0458 Failure Frequency Test with a Block 0.709 0.478 Failure Figure 10: The numbers obtained from memory out- put S. A. Tuncer; Informacije Midem, Vol. 48, No. 2(2018), 121 – 128 127 Runs Test 0.141 0.964 Failure Longest Run of Ones in a Block 0.285 0.715 Failure Binary Matrix Rank 0.826 0.229 0.642 Discrete Fourier Transform 0.516 0.433 Failure Non-Overlapp. Temp. Matching 0.611 0.622 Failure Overlapping Template Matching 0.208 0.738 Failure Universal Test 0.214 0.696 Failure Linear Complexity 0.606 0.905 0.393 Serial Test 0.792 0.271 Failure Approximate Entropy 0.137 0.33 Failure Cumulative Sum 0.929 0.073 Failure Moreover, the numbers generated by these procedures were subjected to autocorrelation test. Correlation in- dicates a linear relationship between two or more vari- ables, and takes values between +1 and −1. If it is equal to or close to 0, there is no linear relationship between the variables. The purpose of this test is to control the correlation between the produced bit array bi and its shift version. When n has bit array length, d will be a constant integer and 1 ≤ d ≤ (n/2). The mathematical definitions of the test are given in Eq.3 and 4 [14]. ( ) 1 1 n d i i d i A d b xor b − − + = = ∑ (3) ( ) ( ) 5 2A d n d X n d − − = − (4) If {bi} is a real random array and n→ ∞, this random variable has a normal distribution N(0, 1). If |X5|<1.6449 (α=0.05), then the test is successful. Table 4 shows the autocorrelation test results. Table 4: Autocorrelation Test Results d Double Puf Result Autocorrelation 8 0.0249 Passed 10 0.0316 Passed 6 Conclusion It is important to use random numbers in authentica- tion and secret key generation. PUF structures are used for low-cost authentication and in the key generation for symmetric and asymmetric encryption. In such applications, random numbers that are generated for key and authentication are the most important param- eters that determine the security of the application. With these issues in mind, we proposed a double PUF structure in this study, which is a unique structure in the relevant literature. We used RO-based PUF content for the new structure because it was suitable for being implemented on FPGA. The system was implemented on two different FPGA cores that were manufactured with 65 nm technology. Used FPGA boards have dif- ferent characteristics because of core manufacturing conditions. In this case, the proposed system will not be cost-effective. To overcome this disadvantage, we suggest that the system should be implemented with two different cores on a single integrated circuit. The study employed Von Neumann and hash-based post- processing to remove the bit irregularities in the gen- erated random numbers. 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Güneysu, “On the prob- lems of realizing reliable and efficient ring oscilla- tor PUFs on FPGAs,”  2016 IEEE International Sym- posium on Hardware Oriented Security and Trust (HOST), McLean, VA, 2016, pp. 103-108. Arrived: 06. 01. 2018 Accepted: 29. 05. 2018 S. A. Tuncer; Informacije Midem, Vol. 48, No. 2(2018), 121 – 128 129 Original scientific paper  MIDEM Society Doktorske disertacije na področju mikroelektronike, elektronskih sestavnih delov in materialov v Sloveniji v letu 2017 Doctoral theses on Microelectronics, Electronic Components and Materials in Slovenia in 2017 Univerza v Ljubljani / University of Ljubljana Fakulteta za elektrotehniko / Faculty of Electrical Engineering 1 Avtor Jan Medvešek Author Naslov Metode izboljšanja natančnosti in zanesljivosti lokalizacije v zaprtih prostorih Title Methods for improving the accuracy and reliability of indoor localisation Mentor Prof. dr. Stephen Hailes Somentor Izr. prof. dr. Andrej Trost Supervisor Co-Supervisor 2 Avtor Mario Vukotić Author Naslov Električni motor z moduliranim magnetnim poljem Title Electric motor with modulated magnetic field Mentor Prof. dr. Damijan Miljavec Supervisor 3 Avtor Gašper Korinšek Author Naslov Razpoznavanje vrstno-specifičnih vibracijskih signalov škržatkov samcev vrste A. bicincta “Dragonja” in reprodukcija odgovorov samice v realnem času Title Recognizing species-specific vibrational signals of A. bicincta “Dragonja” males and reproducing female replies in real time Mentor Prof. dr. Tadej Tuma Somentor Doc. dr. Meta Virant- DoberletSupervisor Co-Supervisor 4 Avtor Luka Mesarec Author Naslov Stabilnost membranskih nanostruktur Title Stability of membrane nanostructures Mentor Prof. ddr. Aleš Iglič Supervisor Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 2(2018), 129 – 132 130 5 Avtor Peter Naglič Author Naslov Modeliranje širjenja svetlobe v sipajočih medijih za reflektančno spektroskopijo z optičnimi sondami Title Modeling of light propagation in turbid media for fiber optic reflectance spectroscopy Mentor Izr. prof. dr. Miran Bürmen Supervisor 6 Avtor Gregor Ergaver Author Naslov Raziskava elektromagnetnih sevalnih emisij elektronskih naprav za avtomobilsko področje Title Research of electromagnetic radiated emissions for automotive electronic devices Mentor Prof. dr. Janez Trontelj Supervisor 7 Avtor Rok Vrtovec Author Naslov Napredno krmiljenje vrat močnostnih tranzistorjev Title Advanced gate control of power transistors Mentor Prof. dr. Janez Trontelj Supervisor 8 Avtor Marko Jošt Author Naslov Proces izdelave in karakterizacija nanotekstur za upravljanje svetlobe v fotonapetostnih in optoelektronskih elementih Title Fabrication and characterization of nanotextures for light management in photovoltaic and optoelectronic devices Mentor Prof. dr. Marko Topič Supervisor 9 Avtor Ahmed Samir Abdel Ghani Atia El Azerk Author Naslov Fluorimetrične sonde iz večjedrnega optičnega vlakna Title Multi-core fiber-optic fluorometer probes Mentor Doc. dr. Boštjan Batagelj Supervisor 10 Avtor Milan Kovačič Author Naslov Načrtovanje in optimizacija naprednih fotonskih struktur za tankoplastne optoelektronske elemente z uporabo optičnega modeliranja Title Design and optimization of advanced photonic structures for thin-film optoelectronic devices by means of optical modelling Mentor Prof. dr. Janez Krč Supervisor Doktorske disertacije/Doctoral theses; Informacije Midem, Vol. 48, No. 2(2018), 129 – 132 131 11 Avtor Karel Flisar Author Naslov Visokoenergijska naprava za reverzibilno in ireverzibilno elektroporacijo celične membrane Title High-energy device for reversible and irreversible electroporation of the cell membrane Mentor Prof. dr. Damijan Miklavčič Somentor Prof. dr. Danjel Vončina Supervisor Co-Supervisor 12 Avtor Grega Logar Author Naslov Modeliranje in ocenjevanje smučarskega skoka iz podatkov nosljivega merilnega sistema Title Modeling and evaluation of ski jump from data acquired with wearable measurement system Mentor Prof. dr. Marko Munih Supervisor 13 Avtor Marko Šajn Author Naslov Močnostni podnanosekundni svetlobni vir Title Subnanosecond power light source Mentor Prof. dr. Matjaž Vidmar Somentor Izr. prof. dr. Rok Petkovšek Supervisor Co-Supervisor Univerza v Mariboru / University of Maribor Fakulteta za elektrotehniko, računalništvo in informatiko / Faculty of Electrical Engineering and Computer Science 1 Avtor Vedran Budinski Author Naslov Optičnovlakenski senzorji za točkovne in kvaziporazdeljene meritve rotacij in kotov zasuka z enojnim dovodnim vlaknom Title Fiber optic sensors for point and quasi-distributed twist/rotation measurements, constructed on a single lead fiber Mentor Prof. ddr. Denis Đonlagić Supervisor Univerza v Nova Gorica / University of Nova Gorica 1 Avtor Jinta Mathew Author Naslov Stiki grafena z organskimi polprevodniki: Morfologija in transport električnega naboja Title Graphene/organic semiconductor systems: morphology and charge transport Mentor Prof. dr. Gvido Bratina Supervisor Doktorske disertacije/Doctoral theses; Informacije Midem, Vol. 48, No. 2(2018), 129 – 132 132 Mednarodna podiplomska šola Jožefa Stefana / Jožef Stefan International Postgraduate School 1 Avtor Mateja Košir Author Naslov Thermoelectric materials based on ZnO Title Termoelektrični materiali na osnovi ZnO Mentor Prof. dr. Slavko Bernik Supervisor Bold font is used for the original title of the thesis (and language in which the thesis is written), normal font for title translation. Doktorske disertacije/Doctoral theses; Informacije Midem, Vol. 48, No. 2(2018), 129 – 132 Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Marko Topič, University of Ljubljana, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Iztok Šorli, MIKROIKS, d. o. o., Ljubljana, Slovenija Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenija MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Darko Belavič, HIPOT-RR d.o.o., Otočec, Slovenia Dr. Slavko Bernik, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Đonlagič, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University Wroclaw, Poland Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Leopold Knez, Iskra TELA d.d., Ljubljana, Slovenia mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Prof. Dr. Miran Mozetič, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia prof. dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, Ljubljana, Slovenia Court of honour | Častno razsodišče Emer. Prof. Dr. Jože Furlan, Slovenia Dr. Marko Hrovat, Slovenia Dr. Miloš Komac, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si