238 Original scientific paper  MIDEM Society Advanced gate control system for power MOSFET switching losses reduction with complete switching sequence control Rok Vrtovec, Janez Trontelj University of Ljubljana, Faculty for Electrical Engineering, Ljubljana, Slovenia Abstract: To meet strict EMC requirements for power electronics applications driving an inductive load, it is often necessary to mitigate current and voltage transition slopes. Using the conventional MOSFET control method, the slope mitigation is commonly performed by modifying a series gate resistance, which results in high switching losses, long turn-on and turn-off delays and long final gate charging and discharging durations affecting the overall application efficiency. In order to improve this, a novel MOSFET control method is developed and presented in this paper. It enables a complete control over all intervals of the switching sequences utilizing the gate current shaping principle. Switching losses, delays and final gate charging and discharging durations can be kept as low as possible, as the method allows to mitigate only the critical transition. The design of the system allows its implementation in a broad spectrum of applications regardless of the current or voltage rating and with a minimal impact on the application design. The paper presents the detailed description of the proposed system operation and its realization as an integrated circuit. The efficiency measurements of the conventional and the advanced gate control methods are reported as well, showing significant advantages of the proposed system. Keywords: Power MOSFET switching behavior; advanced gate control; gate current shaping; switching losses reduction; EMC in power electronics Napredno krmiljenje vrat močnostnih MOSFET tranzistorjev za zmanjševanje preklopnih izgub z nadzorom nad celotno preklopno sekvenco Izvleček: Za doseganje elektromagnetne skladnosti moramo v močnostni elektroniki pri napravah z induktivnim bremenom pogosto zmanjšati naklon toka ali napetosti med preklopi. Pri konvencionalni krmilni metodi to storimo s spreminjanjem serijske upornosti v vratih MOSFET tranzistorja. Slednje se odraža v povečanju preklopnih izgub, podaljševanju zakasnitev vklopa in izklopa ter podaljševanju trajanja končnega polnjenja in praznjenja vrat. Našteto zmanjšuje zmogljivost celotne naprave. Navedene pomanjkljivosti konvencionalne metode ublažimo z uporabo nove napredne krmilne metode, ki je predstavljena v tem članku. Deluje na principu spreminjanja toka, ki teče v vrata MOSFET tranzistorja ter omogoča nadzor nad dogajanjem v vsakem intervalu preklopne sekvence. Ker lahko na tak način omilimo le kritični naklon, sistem omogoča vzdrževanje minimalnih preklopnih izgub, zakasnitev in trajanj končnega polnjenja in praznjenja vrat. Sistem je zasnovan tako, da ga lahko vgradimo v širok spekter naprav, ne glede na napetostno ali tokovno zmogljivost in z minimalnim poseganjem v zasnovo same naprave. V članku je detajlno opisano delovanje predstavljenega sistema ter njegova realizacija v obliki integriranega vezja. Predstavljene so tudi meritve učinkovitosti konvencionalne in napredne kontrole vrat. Rezultati so občutno boljši v primeru uporabe predstavljenega sistema. Ključne besede: Preklopi močnostnega MOSFET tranzistorja; napredno krmiljenje vrat; oblikovanje toka v vrata tranzistorja; zmanjševanje preklopnih izgub; EMC v močnostni elektroniki * Corresponding Author’s e-mail: rok.vrtovec@fe.uni-lj.si Journal of Microelectronics, Electronic Components and Materials Vol. 46, No. 4(2016), 238 – 249 239 1 Introduction The tradeoff between switching losses and electro- magnetic emissions is often of great concern during the design of power electronic applications with an in- ductive load. Fast transitions of voltage and current at power switch (in this paper we are focusing on power MOSFETs) cause excessive emissions and oscillations, while slow transitions cause significant switching loss- es. To meet strict EMC requirements, slopes must often be limited, which is obviously done at the expense of increased switching losses. Power MOSFETs are commonly driven via series gate resistor (Rg). Transition slopes are adjusted by changing Rg value but such approach is not the most effective. The problem is that changing Rg resistance influences all intervals of the switching sequence instead of miti- gating only the critical transition that is responsible for emissions. This produces excessive switching losses, introduces long turn-on and turn-off delays and ex- tends final gate charging and discharging durations. To improve this process, a different gate control method should be used to allow control over transition in each interval of the switching sequence independently. Several papers [1–10] report improvements of the conventional control method with a gate resistor or propose entirely new control approaches that differ in functionality, complexity, efficiency and cost. For example, the methods presented in [1], [2], [4], [7] focus only on the mitigation of turn-off voltage over- shoot and the following oscillations, which are often an issue especially among IGBT circuits. Papers [5], [8] introduce the combined control over turn-off voltage and turn-on current transition. The latter is usually of great concern, as the current slope impacts reverse re- covery severity, it may induce oscillation and it strongly impacts the emissions rate. The method [9] focuses on the acceleration of turn-on voltage fall and minimiza- tion of the turn-off delay. The most comprehensive ap- proaches are reported by Rose [3], Park [6] and Lobsi- ger [10] demonstrating current and voltage transition control during the turn-on and the turn-off. None of the presented methods, however, addressed control over the whole duration of the switching sequence. The presented control methods are based on signifi- cantly different principles for the operating point de- tection of the controlled MOSFET (or IGBT), which is an essential part of any advanced control method. Certain methods [2], [6], [7], [10] use capacitor or special dif- ferentiator circuit connected to the transistor drain (or collector) terminal. Despite being simple and low-cost, such approach may be susceptible to noise [4] and os- cillations that potentially mask the actual voltage tran- sition resulting in an inappropriate control procedure. On the other hand, methods [3], [4], [6], [10] exploit in- trinsic inductances from the physical circuit to detect the current transitions. Such system may be found dif- ficult to implement, taking into account diverse layout topologies, current slopes and ratings. Gate control approach as presented in this paper aims to enable control over transitions in all intervals of the switching sequences and to use such operating point detection principle that allows system implementation in various applications regardless of voltage or current ratings and with a minimal impact on the circuit layout design. Presented system is also a subject of PCT patent appli- cation. Paper is organized in the following order: section 2 presents the inductive load switching sequence, switching losses and EMC overview and provides an explanation about the conventional gate control draw- backs; section 3 describes the concept of the proposed gate control system; section 4 presents system realiza- tion as an integrated circuit; section 5 presents system measurements, results and discussion, while section 6 concludes the paper. 2 Switching sequences, switching losses and EMC A short insight into a well known switching behaviour of a MOSFET with a clamped inductive load is given first in order to present switching losses and electro- magnetic emission (EM) generation and to underline the importance of the advanced gate control introduc- tion. A clamped inductive load circuit, presented in Figure 1, is comprised of MOSFET M1, inductive load (Lload), free- wheeling diode (Dfwd, which is the intrinsic diode of per- manently closed MOSFET M2), driving circuit (Vgg and Rg), MOSFET M1 intrinsic capacitances (Cgs and Cgd) and supply voltage source Vbat. The corresponding switch- ing waveforms of M1 turn-on and turn-off sequences are shown in Figure 2 [11]. Just before the t0, the initial conditions in the circuit are as follows: vgg=0 and vgs=0, so M1 is switched-off (id=0); due to previous excitations, inductor Lload drives current I0 through Dfwd (ifwd=I0), and since Dfwd is forward-biased, vds equals Vbat. R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 240 Figure 1: Clamped inductive load circuit The turn-on sequence starts with the interval T1 (turn- on delay) at t=t0, when Vgg turns-on (vgg=Vgg) and starts charging Cgs (Figure 2a). As vgs reaches the threshold voltage Vth at the beginning of the interval T2, M1 starts conducting (Figure 2b) and taking over the load cur- rent I0 from Dfwd. When id rises to I0, ifwd falls to zero, so Dfwd can be reverse-biased; the reverse-recovery process takes effect manifesting as M1 drain current overshoot. During the whole interval T2, the forwardly biased Dfwd clamps vds to Vbat level. In the interval T3, vds drops as Cgd is discharged (Figure 2c). The total current from Vgg is now diverted to Cgd, causing vgs to remain constant at the Miller plateau (Vµ). After vds drops to Vds,on (a conse- quence of M1 channel resistance), Cgs starts charging again and vgs is rising again towards Vgg in T4. The turn- on is thus accomplished [11] [12]. The turn-off occurs in a similar manner. It begins with Vgg going low at t=t0’, followed by a turn-off delay interval T4’, in which vgs falls to Miller plateau, as Cgs is discharged (Figure 2e). Beyond vgs=Vµ, further Cgs discharging re- quires drain current reduction, which is impossible at that moment, since Dfwd is reverse biased (Vbat>vds) and cannot take over load current (I0) yet. Therefore, vds rises first in T3’ (Figure 2g). When vds meets Vbat, I0 can eventu- ally be diverted to Dfwd, so M1 drain current (id) falls in T2’ (Figure 2f ). At vgs=Vth, M1 closes (id=0, ifwd=I0) and only vgs remains to drop to zero in T1’, thus terminating turn-off sequence [11]. The review of the switching sequences shows that the current (id) transitions in T2 and T2’ occur at the full volt- age (vds) on M1. Similarly, voltage (vds) transitions in T3 and T3’ occur at the maximum drain current. This results in high power dissipation, psw=id∙vds. The integrals of psw over T2 and T3 for turn-on (1) and over T2’ and T3’ for turn-off (2) determine the turn-on (Esw,on) and turn-off (Esw,off) switching losses (Figure 2d and h) [11] [12]. , 0 2 3 2, 3 1( )dt ( ) 2sw on sw batT T E p t I V T T= = +∫ (1) , 0 2 3 2', 3' 1( )dt ( ' ') 2sw off sw batT T E p t I V T T= = +∫ (2) The dissipated energy, manifested as heat, is the root cause of several engineering challenges. Most im- portantly, it is necessary to provide adequate heat sinking, which often results in a bulky and expensive design and presents a limit for the application imple- mentation. Moreover, elevated application tempera- ture results in increased degradation rate of assembly components and impact general system reliability. As switching losses may present an important source of heating, their minimization is of great concern [13]. It is also well established that current and voltage tran- sitions in T2, T2’ and T3, T3’ are the main source of elec- tromagnetic emissions in power applications. High di/dt and dv/dt rates in conjunction with inductive and capac- itive coupling cause conducted (and indirectly also ra- diated) differential (DM) and common mode (CM) emis- sions. Moreover, di/dt and dv/dt could excite oscillations and overshoots in resonant circuits (formed by parasitic inductances and capacitances), producing additional emissions and affecting the system reliability. There are several mechanisms available to mitigate emissions and oscillations (to meet EMC standards), each with its own trade-offs. One possibility is obviously to decrease di/ dt and dv/dt rates (i.e. extend intervals T2, T3, T2’ and T3’) and eliminate the emissions origin, but at the expense of additional switching losses. We can furthermore tweak layout or insert additional components, such as snubber circuits or blocking capacitors, which usually involves a lot of prototyping and has only limited effect. Another possibility is the implementation of CM and DM filters, which is an effective but bulky and expensive solution. Most designs require to utilize all of the above, each in the scope of its own trade-offs and affected application characteristics [13][14]. On the other hand, any improve- ment of the described mechanisms eases the applica- tion design and boosts its efficiency. This paper presents one of such improvements, which deals with the MOSFET control circuit and increases slope adaptation mechanism efficiency. The main drawback of the conventional method employing a series gate resistor Rg is that increasing the gate circuit resistance in order to reduce critical current or voltage slopes prolongs all inter- vals in corresponding switching sequence. First, it causes excessive switching losses in T2, T2’, T3 or T3’, as it extends both current and voltage transitions. Moreover, an exten- sion of T1 and T4’ has a negative impact on applicability of some control algorithms, as it requires longer dead-times and in turn also produces higher diode Dfwd losses [12]. Ex- tension of T4 or T1’ affects the system reliability in terms of the unintentional turn-on / turn-off immunity. R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 241 Introduction of the advanced gate control system pre- sented in this paper, which allows setting the duration of each interval of the switching sequence separately, extends the margins where slope adaptation effective- ly improves the application efficiency. Figure 2: Switching sequence waveforms 3 Advanced gate control system Figure 3 depicts the block diagram of the advanced gate control system presented in this paper. The system is constructed of two main units, namely the current sources unit and the control circuit unit. The role of the first is to feed the power MOSFET gate, while the sec- ond unit monitors the power MOSFET operating point, detects the ongoing switching sequence interval and produces control signals for the current sources unit. Each unit operation is explained in detail in the follow- ing sections. Figure 3: Advanced gate control system block diagram 3.1 Current sources unit The advanced gate control system (Figure 3) is based on the power transistor gate current shaping (ig) princi- ple, implemented using two controlled current sources (Ig,on and Ig,off ) that charge and discharge the transistor input capacitance during its turn-on and turn-off. Each source amplitude can be individually set in each inter- val of the switching sequences. By adjusting the gate current (ig) in each interval, the charge flow rate to the gate is governed and hence the rate of change of each interval transition can be indi- R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 242 vidually controlled. We can therefore adjust each cur- rent and voltage slope (di/dt and dv/dt) in intervals T2, T3, T2’ and T3’ and also minimize turn-on and turn-off delays in T1 and T4’ and the duration of the final gate charging and discharging in the intervals T4 and T1’. An example of the advanced gate control operation is shown in Figure 4. Figure 4: By shaping gate current ig drain current slope is being controlled The presented gate control approach can improve the conventional gate control drawback where all interval transitions are influenced simultaneously with Rg adap- tation. Determining the optimal point of the trade-off between switching losses and electromagnetic emis- sions is thus much more effective. In most situations, less switching losses are produced for the same rate of electromagnetic emissions. Delays and final gate charging and discharging durations can also be mini- mized. The ig amplitude adjustment throughout the switch- ing intervals is performed by the amplitude manager system. It enables the user to set the desired interval amplitude levels and control the Ig,on and Ig,off current sources. The operation of the amplitude manager is based on the information about the ongoing interval, which is obtained from the control circuit unit. Ampli- tude managers and current sources are implemented as current mirrors, described in detail in section 4. The current sources are supplied with voltages (Vcc) equal to gate-source voltage (vgs) required for power transistor full turn-on (typically 12V for common power MOSFETs). 3.2 Control circuit unit The role of the control circuit unit is to detect borders between the intervals of the switching sequence and to subsequently send information about the ongoing interval to the current sources block. It consists of three subunits, namely the signal conditioning unit (CIR1), interval detection unit (CIR2) and logic circuit for the current sources control (CIR3). 3.2.1 Signal detection and Signal conditioning unit The signal conditioning unit (CIR1) accepts signals vds and vgs from the MOSFET and the control signal vgg (usu- ally from a microcontroller). To understand why it is nec- essary to monitor vds and vgs, we must first take a look at the interval detection principle. The interval borders are associated with specific events, marked with points N0, N2, N3 and N4 for turn-on and F0, F4, F3 and F2 for turn- off in Figure 5 and explained in Table 1. As evident from Figure 5, the points are located on vds, vgs and vgg, which means that these signals provide full information about the ongoing interval. It should be emphasized that the points are located exclusively on the voltage signals that are commonly present in each inductive load circuit. This is an important advantage of the presented system, as it enables an implementation in various power applica- tions regardless of voltage or current rating. Table 1: Interval border points explanation Point Start of interval Associated event N0 T1 Start of TURN-ON sequence, vgg starts rising N2 T2 vgs reaches threshold voltage Vth N3 T3 vds starts falling N4 T4 vds drops to the final value Power transistor is ON F0 T4’ Start of TURN-OFF sequence, vgg starts dropping F4 T3’ vds starts rising F3 T2’ vds rises to the final value F2 T1’ vgs drops to the threshold voltage Power transistor is OFF Before point sensing and interval detection, the input signals vds and vgs are processed by the signal condi- tioning unit (Figure 6). Signals must be filtered first to eliminate high-frequency oscillations that commonly occur during the power transistor switching. The filters must be carefully designed to keep their time constant small compared to the switching sequence interval durations. The control signal vgg, which is a logic signal, must be voltage-matched to meet the comparator in- put requirements. 3.2.2 Interval detection unit After filtering, the signals are passed to the interval de- tection unit (CIR2) that outputs the signals s2, s3 and s4 R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 243 (Figure 5 d), which provide full information about the ongoing interval (by forming a unique combination in each interval) in conjunction with vgg. Each of the three signals is set high and then low at two points: s2 at N2 and F2, s3 at N3 and F3, and s4 at N4 and F4 respectively (Figure 5). Since each point pair detection and corre- sponding output signal generation follows the same principle and utilizes an identical circuit (depicted in Figure 7), a common explanation is applicable hereaf- ter, where the input signal stands for vgs’ and vds’ and the output signal for s2, s3 and s4. For s2, the input signal is vgs’, while for s3 and s4 generation, the input signal is vds’. Since vgg’ is a logic signal, the detection of points N0 an F0 does not require utilizing the circuit from Figure 7. The vgg’ transition detection is carried out in the logic circuit for current sources control unit (CIR3). As evident from Figure 7, the input signal vgs’ or vds’ crossing a certain level at points Ni or Fi is sensed by the comparator (U1 and U2). The point levels are user-con- figured by adapting the input voltage dividers (R1-R2) and (R3-R4). In case that a voltage signal at a compara- Figure 7: Interval detection unit (CIR2) – one out of three identical circuits is depicted. R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 Figure 5: Switching sequence with N and F points Figure 6: Signal conditioning unit (CIR1) 244 tor input exceeds its rating, the Zener diodes Z1 and Z2 start clamping to protect the comparator inputs. To ensure that Ni and Fi points are detected exclusively during turn-on and turn-off sequences and to prevent flip-flop mistriggering, the AND gates U3 and U4 with applied ngg’ and 'ggv inputs are inserted to generate a sequence-matching window for passing compara- tor output signal. When a point crossing is detected, a SR flip-flop input is triggered: S input at Ni and R input at Fi point detection, which generates a Q signal that matches the desired output signal waveforms s2, s3 or s4, Figure 5. Using flip-flops for the interval detection is also impor- tant to ensure the immunity to oscillations, as SR flip- flops react only on the first input triggering. Therefore, comparator input signal oscillation around Vref (which results in comparator output alternating) has no effect on the s2, s3 or s4 waveforms. 3.2.3 Logic circuit for current sources control The signals s2, s3 and s4 are passed to the logic circuit CIR3 (Figure 3) that together with the signal vgg’ pro- duces the controlling signals A1 to A6 for the current sources unit. The operation of this unit follows the selected current sources control scheme, which is de- scribed in detail in the next section. 4 System implementation The system is implemented as an IC in a 250 nm TSMC technology (Figure 10). The circuit integration is essen- tial for an efficient system embodiment. First, it ena- bles short propagation delay of the controlling circuit, which is crucial to be small in comparison to the inter- val durations allowing the management of switching transients. To make our system implementable in ap- plications with expected switching transient durations of 100ns, it is considered that signal propagation delay must not exceed 10 ns, which is likely unachievable us- ing discrete components. Furthermore, the integration allows an efficient realization of current sources and amplitude managers in the form of integrated current mirrors. An important integration benefit is also mini- mization of the system physical dimensions. The purpose of the system implementation presented in this work is to prove the concept of the described system. In order to simplify the system development and future research, only the crucial parts are integrat- ed. According to Figure 3, these are the current sources unit with the exception of resistors the Rref1 to Rref6 (Fig- ure 8), logic circuitry for controlling current sources and the interval border detection unit with the exception of input voltage dividers (R1, R2 and R3, R4 in Figure 7). The system is supplied with two voltage levels, 5 V for the controlling circuit and 12 V (Vcc) for the current sources unit. 4.1 Current sources unit realization Figure 8 presents a realization of the current sources unit with integrated current mirrors. The transistors Mh0 and Ml0 present a physical implementation of the cur- rent sources Ig,on an Ig,off (from Figure 3), while the rest of the circuit embodies the corresponding amplitude managers. The unit is divided into a high-side and low- side subcircuit, each consisting of three channels (two of them depicted dimmed) that enable setting differ- ent ig,on and ig,off amplitude levels and shape the gate current (ig) during switching sequence intervals. The amplitude levels are user-defined by adjusting the Rref1 to Rref6 resistor values (not part of IC) that determine current mirror reference currents for each channel (ir1, ir2, ir3 and ir4, ir5, ir6). The reference currents are mirrored to ih2, ih2’, ih2’’ and il2, il2’, il2’’. A single mirror is required for the high side subcircuit, while the low side requires two mirroring stages for the Ig,on and Ig,off source and sink realization. The mirrored currents are then combined into ih1 and il1 (ih1=ih2+ih2’+ih2’’ and il1=il2+il2’+il2’’) that pre- sent the reference currents for the Mh1-Mh0 and Ml1-Ml0 current mirrors and in turn determine the ig,on and ig,off waveforms. Each output current therefore consists of three components and can be defined as (3) and (4), where M indicates the total current mirror multiplica- tion factor. In this design, M equals 1000. , 1 2 3( ) ( ) ( ) ( )g on r r ri t M i t M i t M i t= ⋅ + ⋅ + ⋅ (3) , 4 5 6( ) ( ) ( ) ( )g off r r ri t M i t M i t M i t= ⋅ + ⋅ + ⋅ (4) To set the ig amplitude in each interval separately, the transistors Mh3, Mh3’, Mh3’ and Ml3, Ml3’, Ml3’’ are utilized, controlled by the A1 to A6 signals from the logic circuit for current sources control CIR3 (Figure 3). The transis- tors act as switches and take over the reference currents ir1 to ir6 from Mh2, Mh2’, Mh2’’ and Ml2, Ml2’, Ml2’’. This causes zero current mirroring in the corresponding channels and consequently zero ih2, ih2’, ih2’’, il2, il2’ or il2’’ contribu- tion in the formation of the ih1 and il1 currents, which, as presented, impact the ig,on and ig,off amplitudes. To put it briefly, the gate current ig shaping is embod- ied by the switching signals A1 to A6 throughout inter- vals which define the appropriate current components from the expressions (3) and (4) to form the ig,on and ig,off currents at a given time. The ig,on and ig,off amplitude lev- els are set by adjusting the reference currents by the external Rref1 to Rref6 resistors. R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 245 Figure 8: Schematic of current sources unit and corre- sponding amplitude managers (High side subcircuit for Ig,on and Low side subcircuit for Ig,off) 4.2 Current sources controlling scheme In each interval, a particular A1 to A6 signal combination is provided by logic circuit for current sources control (CIR3) to ensure fast and smooth current shaping. The resulting ig,on and ig,off current composition of multiplied reference currents (M∙ir1 to M∙ir6) is presented in Figure 9. As evident, the ig,on and ig,off components M∙ir2 and M∙ir6 are present during the whole turn-on and turn-off se- quences. Regarding the turn-on, in the intervals T1 and T4 M∙ir1 is added to M∙ir2 to minimize the delay and final gate charging duration. During T2, only M∙ir2 is available – the power transistor current slope is usually the one requiring the strongest mitigation and therefore re- quires the lowest gate current. The voltage slope in T3 is managed by M∙ir2 and M∙ir3. A similar operation refers to the turn-off: M∙ir6 and M∙ir4 in T4’ minimize the turn-off delay, and M∙ir6 and M∙ir5 deter- mine the voltage slope in T3’. Only M∙ir6 component is pre- sent during the current transition in T2’. Since the duration of the input capacitances discharging in T1’ is already lim- ited by the low power transistor vgs voltage and intrinsic resistances, only the M∙ir6 component is provided. During the turn-on sequence, ig,off equals zero, and simi- larly, ig,on equals zero during the turn-off. Figure 9: composition of ig,on and ig,off currents Figure 10: A microphotograph of the advanced gate control ASIC. IC dimensions approx. 1502 um x 2430 um R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 5 Testing, results and discussion 5.1 Test setup To investigate the efficiency, the advanced gate control system is compared to the conventional control meth- od with the series gate resistance. The test is carried out using a common inductive load circuit, as depicted 246 in Figure 11 (the circuit basic operation is already de- scribed in Section 1). Between the gate and the source terminals of MOSFET M1, a 10 kΩ resistor and a 10 nF ca- pacitor are inserted to emulate realistic conditions. The two components are often inserted in power circuits to improve immunity against unintentional turn-on and to mitigate the Miller effect consequences. MOSFET M1 can be driven with the advanced or conventional con- trol method, while the drain-source voltage (vds), the gate-source voltage (vgs) and the drain current (id) are monitored with the oscilloscope. To measure the id cur- rent, a Rogowski coil is utilized. The MOSFETs M1 and M2 are both Infineon IPB010N06N. Figure 11: The test circuit schematics The waveform generator Vgg (Agilent 33500B) is pro- gramed to produce a pulse shown in Figure 12. During the interval Tcharge, M1 is open. In this interval, the cur- rent through Lload rises up to the desired value I0, in this case 40 A. After that, M1 is switched off and id is diverted into M2’s diode, which produces the required initial conditions to observe the turn-on and turn-off switch- ing sequences at the following vgg fronts. The time be- tween the last three changes of vgg is kept low (20 us) to produce only minimal change in id. The advanced gate control from Figure 11 as such is de- scribed in previous sections. In the signal conditioning unit, first order low-pass filters are employed compris- ing of 10 kΩ resistor and 1 pF MLCC capacitor. Resistors Rref1 to Rref6 are trimmer potentiometers with 2 MΩ track resistance. The conventional control is composed of a special driver (IR AUIRS2191S) and the series gate resis- tor Rg. The efficiency of the two methods is observed by com- paring turn-on and turn-off switching losses, delays, and final charging / discharging durations at different values of the drain current rise or fall time. This figure of merit is chosen, as the current transitions are considered the most critical, since they are usually faster than volt- age transitions and their mitigation produces greatest amount of surplus switching losses. Moreover, the com- parison of current rise and fall times are more accurate, since the current transitions are not affected by parasitic elements in such extent as the voltage transitions. Definitions of the observed parameters are shown in the Table 2. Table 2: Parameters definitions Parameter Definition Current rise time (tid,rise) id=10% I0 to id=90% I0 Current fall time (id,fall) id=90% I0 to id=10% I0 Voltage rise time (vds,rise) vds=10% Vbat to vds=90% Vbat Voltage fall time (vds,fall) vds=90% Vbat to vds=10% Vbat Turn-on delay vgs=10% Vcc to id=10% I0 Turn-off delay vgs=90% Vcc to vds=10% Vbat Turn-on final charging vds=10% Vbat to vgs=90% Vcc Turn-off final discharging id=10% I0 to vgs=10% Vcc Turn-on switching losses (Esw,on) 2 1 , t sw on d ds t E i v dt= ∫ t1 when id=10% I0 t2 when vds=10% Vbat Turn-off switching losses (Esw,off) 2 1 , t sw on d ds t E i v dt= ∫ t1 when vds=10% Vbat t2 when id=10% I0 R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 Figure 12: vgg and corresponding id waveforms 247 5.2 Measurements and results Figure 13 first shows an example of the advanced gate control operation. The graphs present three turn-on switching sequence waveforms (id, vds and vgs). Each time a different setting for iref3 is applied (by adjusting Rref3 trimmer resistor) in order to manipulate vds fall time. Specifically, the iref3 current is set to 1.7 mA, 706 µA and 63 µA, while the currents iref1 and iref2 are constant in all three cases and set to 370 µA and 39 µA respectively. It should be noted that the voltage drop that occurs during the current transition (while M∙ir2 is active) is a consequence of the voltage induction on parasitic in- ductances due to the relatively high di/dt rate being present and cannot be manipulated with the advanced gate control system. However, the last part of vds drop that can be influenced clearly underlines the system key advantage. While keeping the drain current rise time constant (at around 200 ns), the voltage drop rate could be boosted (in regards to the emission genera- tion) thus reducing switching losses. To compare the two methods, the efficiency measure- ments are performed first with the conventional gate driving method using different gate resistor Rg values. For the turn-on, 39 Ω, 68 Ω, 90 Ω, 120 Ω and 150 Ω are used, which results in the following id rise times: 156 ns, 208 ns, 245 ns, 300 ns and 357 ns respectively. Similarly, for the turn-off, 47 Ω, 82 Ω, 100 Ω, 120 Ω and 150 Ω Rg values are applied, producing 141 ns, 201 ns, 246 ns 277 ns and 346 ns id fall times. The corresponding turn-on and turn-off parameters from Table 2 are obtained by processing waveforms acquired from the oscilloscope. Similar measurement is carried out using the advanced gate control system. This time, trimmer resistors Rref1 to Rref3 for the turn-on and Rref4 to Rref6 for the turn-off from Figure 8 are adjusted to manipulate switching se- quence transitions. Such resistor values are chosen that vds rise and fall times, delays and final charging and dis- Figure 14: Comparison of the conventional and the ad- vanced gate control methods, turn-on R. Vrtovec et al; Informacije Midem, Vol. 46, No. 4(2016), 238 – 249 Figure 13: Advanced gate control operation, turn-on sequence oscillograms. Different tvds,fall are applied at the same tid,rise. 248 charging durations are kept as low as possible, while id rise and fall times are matched to the values obtained using Rg control method. Again, turn-on and turn-off parameters from Table 2 are obtained by processing waveforms acquired from the oscilloscope. The results of the comparison of the two methods are presented in Figure 14 and Figure 15. Figure 14 and Figure 15 show that the extending drain current (id) rise and fall times produce notably less switching losses, shorter turn-off delay and shorter fi- nal charging and discharging durations when using the advanced gate control. Switching losses reduction is in this case a consequence of keeping vds rise and fall time as small as possible. Figure 15: Comparison of the conventional and the ad- vanced gate control methods, turn-off The only parameter without a significant improvement is the turn-on delay, where the results of both methods are comparable. The reason for the advanced control method to be inefficient in this case is presumably the fact that the low reference current ir2 must first charge parasitic capacitances formed by connections on the test PCB and bond pads. This delays the establishment of adequate conditions in current mirrors in interval T2 for proper mirroring (in which only M∙ir2 is supposed to form ig,on). This causes that the current ig,on to equal zero for a period of time, resulting in id current rise delay. The described effect is also evident in Figure 13. Just after M∙ir1+M∙ir2 are active, there is a period of vgs stagnation, which is a consequence of zero ig,on. It is considered that the full integration of the amplitude manager (by using a different method for reference current setting instead of external Rref1 to Rref6 resistors) would eliminate the de- scribed problem. 6 Conclusion The presented advanced gate control method effi- ciently reduces switching losses, as well as enables the minimization of the turn-off delay and final charging and discharging durations. This conclusion is obtained by comparing the advanced gate control with the con- ventional method. For illustration, in case of setting MOSFET drain current rise and fall times to 250 ns, the switching losses reduction is approximately 50% for turn-on and turn-off. Furthermore, the delays are re- duced for 15% (turn-on) and 240% (turn-off ), the turn- off final gate discharging duration is reduced for 50% while the turn-on final gate charging is as much as 10 times shorter. The system effectiveness increases with the current or voltage slope mitigation rate. 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