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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 55, No. 2(2025) Content | Vsebina Original scientific papers Izvirni znanstveni članki A. D. S. Sindhu, C. A. Kumar: 77 A. D. S. Sindhu, C. A. Kumar: Coati Optimized Hybrid Neural Network for Coatijevo optimizirano hibridno nevronsko Efficient Network Slicing in 5 Generation Network omrežje za učinkovito rezanje omrežja v omrežju petih generacij L. Dongdong, J. Tiantian: 87 L. Dongdong, J. Tiantian: Design and Efficiency Enhancement of Oblikovanje in povečanje učinkovitosti polarnega Polar Encoder Based on Universal Logic dekodirnika na osnovi univerzalnih logičnih vrat z Gates Utilizing QCA Technology uporabo tehnologije QCA M. Kunaver: 95 M. Kunaver: Introducing EIS Circuit Elements in Vpeljava elemementov EIS v SPICE simlator vezij SPICE Simulator Environment A. Bose, S. Biswas, S. Sengupta: 103 A. Bose, S. Biswas, S. Sengupta: Development of an Improved Zinc Oxide Razvoj izboljšanega tankoplastnega tranzistorja iz Thin Film Transistor for Next-Generation cinkovega oksida za naslednje generacije tehnologij Smartphone Display Technologies za predvajanje na pametnih telefonih V. S. Yobuamalan, R. Subramaniam, 115 V. S. Yobuamalan, R. Subramaniam, S. S. Sureshkumar, C. Sivathanu: S. S. Sureshkumar, C. Sivathanu: Dual Band Reflectarray for Transmitter/Receiver Dvopasovni odsevni niz za oddajnik/sprejemnik Ground Station Drone Tracking Applications zemeljske postaje za sledenje dronov B. G. G. Alexander, A. Rino, A. R. Anthonymuthu: 127 B. G. G. Alexander, A. Rino, A. R. Anthonymuthu: An efficient Spotted Hyena Optimizer based Učinkovito zaznavanje več uporabnikov za polarni Multi-user Detection for Polar Encoder kodirnik na osnovi Spotted Hyena optimizatorja Announcement and Call for Papers: 137 Napoved in vabilo k udeležbi: 60th International Conference on Microelectronics, 60. mednarodna konferenca o mikroelektroniki, Devices and Materials with the napravah in materialih z delavnico o upravljanju z Workshop on Energy Management energijo in obnovljivih virih energije and Renewable Energy Sources Front page: Naslovnica: 3D pattern of receiver bands 3D vzorec sprejemnih pasov (Viwin Singh Yobuamalan et al.) (Viwin Singh Yobuamalan et al.) 75 76 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.201 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 2(2025), 77 – 86 Coati Optimized Hybrid Neural Network for Efficient Network Slicing in 5 Generation Network Ayya Dhurai Suceelal Sindhu1, Chellappan Agees Kumar2 1Department of Electronics and Communication Engineering, Rajas Institute of Technology, Nagercoil, Tamil Nadu, India. 2Department of Electrical and Electronics Engineering, Arunachala College of Engineering for Women, Vellichanthai, India. Abstract: Network slicing (NS) divides the physical network into many logical networks in order to support the variety of new applications with higher performance and flexibility needs. As a result of these applications, a massive amount of data has been generated with a huge number of mobile phones. Due to this, NS performance has been greatly impacted and extreme challenges have been created. To efficiently handle the challenges, this paper proposes a novel Optimal Network slice Classification Using Deep learning (ONE-CLOUD) technique, which integrates the Coati Optimization Algorithm (COA), GhostNet, and Gated Dilated Convolutional Neural Network (CNN). COA optimizes features such as user device type, packet loss ratio, and delay rate, employing GhostNet model, and Gated Dilated CNN for network slice classification. The proposed method classifies network slices into enhanced Mobile BroadBand (eMBB), Ultra-Reliable and Low-Latency Communications (URLLC), and massive Machine-Type Communications (mMTC). The effectiveness of the suggested approach has been evaluated using the 5G-SliciNdd dataset, utilizing evaluation criteria like accuracy, precision, recall, sensitivity, specificity, throughput, and reduced latency. The overall accuracy of the proposed method is 5.78%, 2.78% and 4.70% higher than the existing DQN-E2E, DRL, and AAA techniques respectively. Keywords: Network Slicing; Deep learning; GhostNet; Gated Dilated CNN; Coati Optimization. Coatijevo optimizirano hibridno nevronsko omrežje za učinkovito rezanje omrežja v omrežju petih generacij Izvleček: Razrez omrežja (NS) razdeli fizično omrežje na več logičnih omrežij, da bi podprl različne nove aplikacije z večjo zmogljivostjo in prilagodljivostjo. Zaradi teh aplikacij se je z velikim številom mobilnih telefonov ustvarila ogromna količina podatkov. To je močno vplivalo na zmogljivost omrežja NS in povzročilo izjemne izzive. Za učinkovito obvladovanje teh izzivov članek predlaga novo tehniko optimalne klasifikacije omrežnih rezin z uporabo globokega učenja (ONE-CLOUD), ki združuje algoritem COA (Coati Optimization Algorithm), GhostNet in gated dilated konvolucijsko nevronsko mrežo (CNN). COA optimizira lastnosti, kot so vrsta uporabniške naprave, stopnja izgube paketov in stopnja zamude, pri čemer uporablja model GhostNet in Gated Dilated CNN za klasifikacijo omrežnih rezin. Predlagana metoda razvršča omrežne rezine v izboljšano mobilno širokopasovno omrežje (eMBB), izjemno zanesljive komunikacije z nizko zakasnitvijo (URLLC) in množične komunikacije strojnega tipa (mMTC). Učinkovitost predlaganega pristopa je bila ocenjena z uporabo podatkovne zbirke 5G-SliciNdd, pri čemer so bila uporabljena merila za ocenjevanje, kot so natančnost, točnost, priklic, občutljivost, specifičnost, prepustnost in zmanjšana zakasnitev. Skupna natančnost predlagane metode je za 5,78 %, 2,78 % in 4,70 % višja od obstoječih tehnik DQN-E2E, DRL in AAA. Ključne besede: Rezanje omrežja; globoko učenje; GhostNet; Gated Dilated CNN; Coati optimizacija. * Corresponding Author’s e-mail: ageeskumar12@outlook.com How to cite: A. D. S. Sindhu et al., “Coati Optimized Hybrid Neural Network for Efficient Network Slicing in 5 Generation Network", Inf. Midem-J. Micro- electron. Electron. Compon. Mater., Vol. 55, No. 2(2025), pp. 77–86 77 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 1 Introduction are gathered initially from the various users or de- vices in the 5G network. Network slicing is an innovative architype for building - After collecting these features, Coati Optimiza- system services that 5G networks have promoted with tion Algorithm (COA) is employed to select fea- the growth of Software-Defined Networking (SDN) and tures from the collected attributes. Subsequently, Network Function Virtualization (NFV) [1]. 5G systems the selected features are output in the form of face immense demand due to mobile tech growth optimal weighted features. and app diversity. They must bolster Quality of Ser- - The NS prediction is achieved by hybridizing vice (QoS) for multiple sectors like virtual reality, aug- GhostNet and Gated Dilated CNN through the mented reality, and remote healthcare, necessitating AND operation, using the newly extracted weight unprecedented advancement [2,3]. optimized features. The output categorizes the network slices into three types: eMBB, mMTC, and In 5G systems, NS defines autonomous, cohesive net- URLLC. works composed of a blend of dedicated and commu- nal resource instances, including system equipment, The remainder of the research is described as follows: radio spectrum, and VNF [4]. 5G system is designed to Section II examines the study using the literature as a be a versatile, multi-service infrastructure that accom- guide. Section III thoroughly explains the suggested modates a diverse range of services, including eMBB, system. Section IV shows the result and discussion, URLLC, and mMTC [5]. One of the utilization cases for whereas Section V shows the conclusion. future 5G, low-inactivity correspondence, is supposed to be upheld by MEC, a basic 5G improvement inno- vation [6]. It brings far-off systems administration, 2 Literature survey storage, and public distributed computing capacities nearer to the edge of the organization [7]. Several studies have utilized several techniques to NS in recent years. The following section covers a few of A network slice contains different organization compo- the current evaluation approaches along with their dis- nents, for example, the terminal, access organization, advantages are as follows: center organization, and transport organization, which can be used by numerous administrators [8]. Unique in In 2020, Li, T., et al., [14] suggested an E2E system slicing relation to other network slices, a network slice has de- source distribution system that operates in multi-slice voted or potentially shared assets [9]. Portable network and multi-service scenarios, based on Deep Q-Networks slice administrators will deliver diverse network slices (DQN). This system dynamically allocates resources to bundled into one product for business clients with optimize by considering both the fundamental system varying requirements, including a single network slice slices and the radio access network slices. To the access type catering to different verticals [10,11]. side’s ideal allocation approach, the typical access rate is enlarged by 9% for slices with delay limitations and To effectively establish and manage network slices that by 5% for slices with rate constraints. In 2021, He, Y., meet QoS requirements amid changing conditions, et al., [15] recommended a multi-chain 5G NS facility handling extensive data swiftly proves challenging for value computation model to ascertain the characteris- humans [12,13]. The automatic method for managing tics of the NS service quality. The Cosi protocol features network slices is critical because manual slice assign- lower traffic consumption and a steady calculation cost ment is inefficient when dealing with the vast amount as compared to other protocols. Ultimately, the practi- of data and dynamic conditions in 5G networks. Au- cality and effectiveness of the multi-chain 5G NS facil- tomatic classification enhances resource allocation ity value computation architecture is demonstrated by by quickly adjusting to changing user demands and security analysis and experimental outcomes. network conditions, thereby ensuring optimal perfor- mance without the delay and potential human error In 2022, Suh, K., et al., [16] suggested a deep reinforce- associated with custom manual assignments. It also ment learning (DRL)-based NS method to determine supports the scalability required to manage the com- the source provision strategy that maximizes long- plexity and diversity of modern 5G applications, such term amount in B5G systems while meeting QoS stand- as VR, AR, and remote healthcare . To address this is- ards. The suggested method is shown to be efficient sue a novel Optimal Network slice Classification Using in addressing the coexistence of use cases in B5G en- Deep learning (ONE-CLOUD) technique, has been sug- vironments and optimizing long-term throughput by gested. The main contributions are as follows: numerical findings. In 2023, Dangi, R. and Lalwani, P., - Packet loss ratio, delay rate, speed, device type, [17] suggested a successful hybrid learning algorithm- slice type, user bandwidth, and other attributes based network-slicing technique to enhance QoS and 78 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 maximize NS, the results produced by the suggested up to ten times faster than DE and PSO when taking model are contrasted with those of current deep learn- into account 30 nodes. The suggested method using ing, machine learning, and optimization methods. It AAA demonstrated an improvement of more than 60% proves that the suggested model performed better in an implementation time that was ten epochs faster. than the others and identified the right network slices to provide top-notch services. The aforementioned techniques have a number of is- sues with NS, including low accuracy, high Latency. To In 2023, Hu, Y., et al., [18] recommended neural network- overcome these challenges a novel ONE-CLOUD tech- based carrying technique. This paper provides a power nique has been proposed and discussed in next sec- 5G slicing service carrying mechanism based on neural tion. networks. Through simulation verification, proved that the properties of electric power services are retrieved, classified, matched, and compliant with the 5G power NS. In 2023, Botez, R., et al., [19] suggested a modified 3 Optimal network slice classification A* algorithm Targeting services with low or extremely using deep learning low latency requirements, it offers a better way to NS in 5G backhaul networks. According to experimental In this section, a novel Optimal Network slice Classifica- data, the suggested technique improves processing tion Using Deep learning (ONE-CLOUD) technique has time by an order of magnitude. These outcomes show been proposed to optimize resource utilization, and how well our method works in 5G backhaul networks enhance the flexibility and efficiency of 5G and beyond to achieve URLLC. In 2024, Gomes, R., et al., [20] sug- networks. Initially, various attributes like bandwidth, de- gested the Artificial Algae Algorithm (AAA) as a 5G- vice type, speed, slice type, packet loss ratio, and delay specific NS solution for the VNE problem. The runtime rate are gathered from different devices or users in the presentation of AAA is independent of the number of 5G network. These features undergo COA for selection, simulated nodes this results in execution times that are resulting in optimal weighted features. GhostNet is hy- Figure 1: Overall workflow of Proposed ONE-CLOUD Method 79 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 bridized with Gated Dilated CNN using the AND op- interlude 0,1, Zj is the location of the jth coati in hunt eration to predict NS, leveraging the newly optimized space, and LWi and UPi are the inferior and superior features. The output classifies network slices into three bounds of the jth choice variable, correspondingly. The types: eMBB, mMTC, and URLLC. The overall proposed subsequent medium Z, known as the population ma- ONE-CLOUD’s workflow is depicted in Figure 1. trix, is used to numerically depict the inhabitants in the COA which is given in Eqn (2) 3.1 Feature extraction In NS, feature extraction is the process of locating and obtaining pertinent data or attributes from the collec- tion of features linked to each slice. (2) 3.1.1 Feature Extraction The COA [21] is a recently developed bioinspired opti- mization technique influenced by the natural behavior of coatis, presents a novel approach for feature extrac- Two of coatis’s natural activities are modeled in order tion in NS. COA is based on the essential idea of imitating to update coatis’s position (feature solutions) in the two important coatis’ behaviors: (i) chasing and fighting COA. Among these behaviors are: i) The method used iguanas and (ii) running away from predators. The COA by coatis to attack iguanas and ii) The coatis’ method of is considered the most suitable technique for network avoiding predators. Consequently, there are two steps slicing feature extraction since its bioinspired mecha- to the updating of the COA population. nisms mimic coatis’ hunting and evasion behaviours. These behaviours enable more effective exploration and Phase 1: Strategy for hunting and attacking iguanas exploitation of the solution space. The COA is especially (exploration phase) well-suited for challenges like network slicing, which de- mands for dynamic adaptability to changing conditions The first phase updates the coati population by simu- and limits, as it has proven to perform well in balancing lating their iguana-attacking strategy. Some climb global search capability and local search precision. When trees to scare iguanas, while others wait below. Half compared to other optimization algorithms like particle climb trees, and the rest wait for the iguana to drop. Swarm Optimization (PSO) and Cuckoo Search Optimi- The mathematical simulation of the climbing coatis’ lo- zation (CSO), COA’s dual strategy allows for a more thor- cation is expressed by Eqn. (3). ough exploration of potential solutions and reduces the probability of getting trapped in local optima. This COA behaviour facilitates more efficient resource distribution (3) in complicated 5G scenarios. Performance measures like latency and throughput are improved by COA’s ability to manage high-dimensional features such as device type, Following its release to the ground, the iguana is placed packet loss, and delay rates in network slicing of 5G. Be- arbitrarily throughout the search area. Eqn (4), (5).is cause the mentioned algorithms might not provide the used to approximate the random position that causes same balance between exploration and exploitation coatis on the pounded to transfer in the hunt space. needed for network slice optimization, this helps in our decision to choose the COA algorithm. The coatis’s origi- IgC : Igcnal location in the hunt space is determined at random i  LWi  k  UPi  LWi  , i 1,2,....,n (4) using Eqn. (1) at the initial stage of the COA implementa- tion. If each coati’s new position increases the value of the objective function, it is permitted for the update pro- (1) cess; if not, the coati stays in its previous place. Eqn (6) determines the simulated values of j = 1, 2, .... m, to which this update condition is applicable. where m is the amount of coatis, n is the amount of choice variables, k is a chance actual amount in the  z j.i  k   Igi  I  z j ,i  ,E E IgC  j Z po1 : z po1  j j.i  z . k z Igc , fo m 1,m (5)  j i   ji  i  r j   ,m and i 1,2,n  2 2 80 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 Z po1,E po1  z j j E from the feature extraction process. The description of j various features used in NS is given in Table 1. j    (6)  z j , else Table 1: Overall summary of various features used in where k is an arbitrary real number in the range [0, 1], network slicing Jg stands for the iguana’s location in the hunt area, Z po1 j Features Feature Description is the original location estimated for the jth coati, z po1 j.i is User device type Properties describe characters and its ith dimension, and E po1 j is its neutral role worth. Jgi is parts of a device its ith measurement; Figure 2 shows the coati optimiza- Packet loss rate Percentage of packet vanish with tion algorithm’s initial phase. respect to packet transmitted Bandwidth Fastest transfer of information rate Figure 2: Coati Optimization Algorithm’s initial phase: possible with an internet connec- (a) Half of the coatis attacking the tree-dwelling iguana, tion and (b) the remaining coatis hunting the fallen iguana Delay rate The time frame before an event occurs Speed Dimensions of location variation 3.2 Network slicing with the commitment of ghostnet and gated dilated CNN Network slicing employs GhostNet and Gated Dilated CNN for efficient classification, enhancing performance and optimizing resource allocation in diverse network environments. The proposed technique combines the GhostNet and Gated Dilated CNN in network slicing, Phase 2: The procedure of running away from an as- which addresses the challenges in classification, espe- sailant (the exploitation stage) cially in handling large and distinct data from 5G net- work slices. The second phase updates coatis’ search space position by modeling their natural behavior when facing preda- 3.2.1 GhostNet Model tors. When attacked, coatis escape, strategically mov- The fundamental unit of GhostNet is a stack of Ghost ing to a safe spot near their current position, showcas- bottlenecks, of which the Ghost modules are the ing COA’s effective local search exploitation ability. To building hunks. The primary layer is a standard con- replicate this behavior, a random position is generated volutional layer with 16 filters, followed by a series of near each coati’s location using Eqns. (7) and (8). Ghost bottlenecks with increasingly more channels. Using a convolutional layer and global average pool- ing, the feature maps are ultimately transformed into LW loc LWi ,U Ploc UP  i i j  , where d 1,2,,D (7) d d a feature vector for the final classification. The Optimal weighted features are given as input to the GhostNet. It Z po2 : z po2 o l c oc j j.i  z j.i  1 2k   LW l c i  k  UP o l i  LWi  (8) is suitable for classifying network slices where resource constraints are common and its input is an optimal The recently computed position is deemed suitable if weighted feature. The convolution operation in a Ghost it enhances the objective function value, a condition Module is given in Eqn (10): simulated by employing Eqn. (9). qi  v y jI j j (10) Z po2 ,E po2 z  j j  E i  j j  (9)  z j , else Here p be the input to the Ghost Module, and q be the output, i indexes the output channels, Sj is the set of indices corresponding to the output channels, Vj is the Here, Z po2 j is the original location determined for the ith weight associated with input channel yi and yi is the in- coati using another stage of COA; z po1 j.i is its ith dimen- put feature map. The Ghost Module introduces a ghost set Gi of randomly selected indices from the set Ii, and sion; E po2 j is its impartial role value; k is a chance amount the convolution operation is given in Eqn (11) within the break [0, 1]; COA to help categorise the weight function, and optimal weight features are the output 81 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 qi  v p is the input sequence. Two gates are used in the gat- iG j j (11) i ing mechanism: the reset gate (rg) and the update gate (ug). Eqn (16) & (17) is used to calculate the update gate The ghost set Gi is dynamically sampled during each (z) and reset gate (r) using sigmoid activation functions. forward pass, leading to parameter-efficient training. With reference to intrinsic feature maps, X ′∈b′×v′×n ug   Vug a,hs1 (16) can be generated by Eqn (12), j′òe×r×r×n is the con- volutional filters. Nevertheless, as Eqn (13) illustrates, rg   Vrg a,hs1 (17) partial convolutional operations are performed, and the remaining feature maps are produced via a linear The Contender concealed state ( is then figured using operation. reset gate, which is given in the Eqn (18). Finally, the ac- tual concealed state ( is figured Using the update gate X   Y * j  b (12) to combine the candidate hidden state with the cur- rent hidden state, which is given in Eqn (19) X  ' j ,i  j ,i X j  , j 1,,n, i 1,,h, (13) hs  tan h Vh rg hs1,a (18) Where, X ' j is the j-th inherent feature map in X ′, θ j ,i the direct process for generating the i-th ghost feature hs  1ug  hs1  ug hs (19) map X j ,i . The outputs from all the ghost branches are aggregated to obtain the final output Q which is given Here, Vug , Vrg , and Vh are weight matrices, is the sig- in Eqn (14). moid activation function, ⊙ indicates multiplication of elements, and tanh is the hyperbolic tangent activation function. If L describes the output of the last layer be- Q M  Z j1 j (14) fore the softmax activation, the final output (Op) can be computed as in Eqn (20) Where, is the total number of ghost breaches. As an improvement, we used the AND operation to opti- O mize the weight function after receiving the output Q p  softmax L (20) from GhostNet. GhostNet model is highly efficient in Finally, the output of two models is merged by AND extracting features from high-dimensional data with operation and classifies the NS types into 3 classes fewer parameters, making it suitable for real-time and such as eMBB, mMTC and URLLC. The Gated Dilated resource-constrained environments such as 5G net- CNN is integrated to capture long-range dependen- works. GhostNet’s ability to generate additional fea- cies in the data. 5G networks often generate complex ture maps through simple linear transformations helps temporal sequences, and traditional CNNs may fail to in reducing the computational burden while retain- exploit these patterns fully. The dilated convolutions ing critical information for classifying network slices in the Gated Dilated CNN allow the model to handle (eMBB, mMTC, URLLC). Utilizing fewer convolutional long-range dependencies efficiently by expanding operations ensures that the model is lightweight, mak- the receptive field without increasing the number of ing it ideal for environments with limited computation- parameters. This mechanism is particularly effective in al power. classifying diverse network slices, as it captures both short-term and long-term dependencies in the data, 3.2.2 Gated dilated CNN model which is crucial for optimizing network performance Gated Dilated Convolutional Neural Networks are a in real time. By combining GhostNet and Gated Dilated type of DL architecture that combines the concepts of CNN through the AND operation, the proposed ONE- dilated convolutions and gated units to capture long- CLOUD technique ensures optimal feature extraction range dependencies in input data. Dilated convolution and classification, addressing both the computational that introduces gaps between the weights. Eqn (15) efficiency and the complexity of network slicing clas- provides the expression for the dilated convolution op- sification. eration on a 1D sequence. a f   j  S   a  j  dr  s  f s (15) s1 4 Results and discussion where indicates the convolution process, is the dila- The proposed ONE-CLOUD technique’s simulation tion rate, is the filter size, is the filter or kernal, and outcomes are obtainable in this section to assess the 82 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 efficiency of the proposed technique. Performance scrutiny and execution of the suggested 5G NS were conducted in MATLAB. Figure 3: Overall Performance comparison in terms of accuracy, precision, and recall The effectiveness of the technique was assessed us- ing the 5G-SliciNdd dataset. The dataset used in this work has been split into training, validation, and test- ing sets, which has been divided into 80%, 10%, and 10% of the entire dataset. The dataset split has been done randomly which ensures that each class is repre- sented proportionally in each subset to prevent class imbalance. The training set has been used to train the network, validation set has been used to fine tune the hyperparameters of the network, and the test set is used to test the network and its performance in NS. Figure 4: (a) Accuracy Curve; (b) Loss Curve With this splitting, we can ensure that the network can reduce overfitting of training data which results in gen- eralization. Additionally, the separate test set will help training and validation losses tend to be downward, ac- in evaluating the generalizability and robustness of cording to the Loss Curve in Subfigure (b). proposed ONE-CLOUD technique. This ensures that the results state the actual performance of the network on test data. The proposed ONE-CLOUD model’s effectiveness is contrasted with DQN-E2E [14], DRL [16], and AAA [20] in terms F1-score, accuracy, sensitivity, specificity, precision, throughput and latency. In Figure 3, a com- prehensive evaluation of overall performance is pre- sented, comparing accuracy, precision, and recall of NS against existing DQN-E2E, DRL, and AAA techniques. The assessment provides insights into how effectively the proposed ONE-CLOUD NS approach performs in comparison to established methods. This comparison Figure 5: Comparison in terms of accuracy aids in gauging the efficacy of NS in comparison to ex- isting techniques. Figure 5 illustrates a focused comparison in terms of accuracy with 100 epochs between the proposed ONE- Figures 4(a) and 4(b) show the training and test data CLOUD technique and existing DQN-E2E, DRL, and AAA sets, as well as the accuracy and loss curves. The Ac- methods. curacy Curve in Subfigure (a) shows how the model’s correctness upsurges on both the training and authen- The graph offers a visual representation of how well tication sets during the course of training epochs. Both the new approach performs in terms of correctness 83 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 Figure 6: Slice acceptance ratio with variable slice traf- fic load Figure 8: Comparison in terms of sensitivity and speci- compared to established techniques. Comparing the ficity accuracy of the suggested ONE-CLOUD method to the current DQN-E2E, DRL, and AAA procedures, it is 5.78%, 2.78%, and 4.70% higher. In Figure 6, the slice receiving ratio is presented along- side variable slice traffic loads, linking the presentation of the proposed ONE-CLOUD technique with existing DQN-E2E, DRL, and AAA methods. This figure allows for an assessment of how well the proposed method adapts to varying levels of network demand compared to established techniques. Figure 9: Comparison in terms of throughput Figure 9 presents a comparison of throughput between the existing AAA, DRL and DQN-E2E techniques and the proposed ONE-CLOUD method for NS. This graph ena- bles an assessment of how the proposed NS method performs in terms of data transmission efficacy associ- Figure 7: Revenue-to-cost ratio with variable slice traf- ated to the existing system, providing valuable insights fic load into the potential improvements in throughput offered by the proposed ONE-CLOUD approach. Figure 7 illustrates the revenue-to-cost ratio in rela- tion to mutable share traffic loads for both the existing Figure 10 illustrates a latency comparison between the DQN-E2E, DRL, and AAA methods and the proposed proposed ONE-CLOUD method and existing AAA, DRL ONE-CLOUD technique for NS. A higher revenue-to- and DQN-E2E techniques. The proposed method dem- cost ratio indicates improved cost-effectiveness, high- lighting the potential benefits of implementing the proposed NS method in comparison to the conven- tional system Figure 8 presents a comparative analysis of sensitivity and specificity between the existing system and the proposed ONE-CLOUD method for NS. The specificity and sensitivity of the proposed ONE-CLOUD method are 3.90%, 9.25%, 12.44% and 5.02%, 4.18%, 6.27% greater than the existing AAA, DRL and DQN-E2E tech- niques respectively. Figure 10: Comparison in terms of latency 84 A. D. S. Sindhu et al.; Informacije Midem, Vol. 55, No. 2(2025), 77 – 86 onstrates superior latency performance compared to 2. A. Ahilan, M.A. Rejula, S.N.Kumar, and B.M. Kumar, current methods. This comparison offers valued visions “Virtual Reality Sensor Based IoT Embedded Sys- into the effectiveness and efficiency of the proposed tem for Stress Diagnosis,” IEEE Sensors Journal. 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Karimidehkordi, “Multi-Service Radio Resource and Gated Dilated CNN models, combined via AND op- Management for 5G Networks”. 2019. eration, boosting accuracy in classifying eMBB, mMTC, 6. P. Mor, S.B. Bajaj, “Enabling Technologies and Ar- and URLLC network slices. The evaluation of the pro- chitecture for 5G-Enabled IoT,” Blockchain for 5G- posed ONE-CLOUD method, conducted using the 5G- Enabled IoT: The new wave for Industrial Automa- SliciNdd dataset. The proposed ONE-CLOUD method tion, pp. 223-259, 2021, outperforms existing techniques, in terms of precision, https://doi.org/10.1007/978-3-030-67490-8_9. accuracy, latency, sensitivity, specificity, throughput, 7. W. Yu, F. Liang, X. He, W.G. Hatcher, C. Lu, J. Lin, X. and recall. The overall accuracy of the proposed ONE- Yang, “A survey on the edge computing for the CLOUD method is 5.78%, 2.78% and 4.70% higher Internet of Things,” IEEE access, vol. 6, pp. 6900- than the existing DQN-E2E, DRL, and AAA techniques 6919, 2017. respectively. Future work could explore the scalability https://doi.org/10.1109/ACCESS.2017.2778504. and applicability of the proposed technique in large- 8. X. Zhou, R. Li, T. Chen, H. Zhang, “Network slicing scale network environments, as well as its adaptability as a service: enabling enterprises’ own software- to emerging communication technologies beyond the defined cellular networks,” IEEE Commun. Mag., scope of 5G. vol. 54, no. 7, pp. 146-153, 2016, https://doi.org/10.1109/MCOM.2016.7509393. 9. R. Li, Z. Zhao, X. Zhou, G. Ding, Y. Chen, Z. Wang, H. Zhang, “Intelligent 5G: When cellular networks 6 Acknowledgments meet artificial intelligence,” IEEE Wireless Com- mun.., vol. 24, no. 5, pp.175-183, 2017. The author would like to express his heartfelt gratitude https://doi.org/10.1109/MWC.2017.1600304WC. to the supervisor for his guidance and unwavering sup- 10. P. Govender, “Dynamic quality of service enabled port during this research for his guidance and support. network slicing for fifth generation core network (Doctoral dissertation, University of Johannes- burg)”. 2023. 7 Conflict of interest 11. T. Irshad, “Design and implementation of a test- bed for network slicing”. 2018. The authors declare that they have no known compet- 12. F. Firouzi, B. Farahani, and A. Marinšek, “The con- ing financial interests or personal relationships that vergence and interplay of edge, fog, and cloud in could have appeared to influence the work reported in the AI-driven Internet of Things (IoT),” Inf. Syst., this paper. vol. 107, pp.101840, 2022, https://doi.org/10.1016/j.is.2021.101840. 13. M. El Rajab, L. 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Arrived: 13. 07. 2024 Accepted: 24. 11. 2024 86 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.202 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 2(2025), 87 – 94 Design and Efficiency Enhancement of Polar Encoder Based on Universal Logic Gates Utilizing QCA Technology Liu Dongdong*, Ji Tiantian School of Computer and Information Engineering, Fuyang Normal University, Fuyang, China Abstract: Nano-scale circuit designs can be implemented using a transistor-free method called Quantum-dot Cellular Automata (QCA). QCA circuits are denser, quicker, and need less energy than the commonly used transistor-based technologies. In QCA technology, like in many other technologies, it is crucial to send and receive information securely. The QCA-based polar encoder circuit is one of the circuits that makes this possible. There are some drawbacks to the polar encoders circuit in QCA technology, and a strong design with high speed and low cell count is also strongly required. This paper presents three new and largely used circuits for QCA- based polar encoders. The G2 (2-bit) design is a single-layer structure with 16 cells only and a total area of 0.02 μm2, while its delay is 0.5 clock cycles. A suggested G4 design would be 121 cells, requiring a total size of 0.16 μm2 with a delay of 1.50 clock cycles. The G8 design has a delay of 3.5 clock cycles at a total size of 0.8 μm2 with 564 cells. All designs are simulated using QCADesigner. The tests and the simulations prove the supremacy of the proposed circuits over the best previous circuits in terms of speed, number of cells, and space used for implementation. Keywords: Polar Encoder, Quantum-Dot, Cellular Automata, QCADesigner, Nano Communication. Nano Electronic. Oblikovanje in povečanje učinkovitosti polarnega dekodirnika na osnovi univerzalnih logičnih vrat z uporabo tehnologije QCA Izvleček: Zasnove vezij v nanometrskem merilu je mogoče izvesti z metodo brez tranzistorjev, imenovano kvantni celični avtomati (QCA). Vezja QCA so gostejša, hitrejša in potrebujejo manj energije kot običajno uporabljene tehnologije, ki temeljijo na tranzistorjih. Pri tehnologiji QCA je tako kot pri številnih drugih tehnologijah ključnega pomena varno pošiljanje in sprejemanje informacij. Polarno kodirno vezje, ki temelji na QCA, je eno od vezij, ki to omogoča. Vezje polarnih kodirnikov v QCA-tehnologiji ima nekaj pomanjkljivosti ter potrebuje močno zasnovo z visoko hitrostjo in majhnim številom celic. V tem članku so predstavljena tri nova in večinoma uporabljena vezja za polarne kodirnike, ki temeljijo na QCA. Zasnova G2 (2-bitna) je enoplastna struktura s 16 celicami in skupno površino 0,02 μm2, njena zakasnitev pa je 0,5 takta. Predlagana zasnova G4 bi imela 121 celic, za kar bi potrebovali skupno površino 0,16 μm2 , zakasnitev pa bi bila 1,50 takta. Zasnova G8 ima zakasnitev 3,5 takta pri skupni velikosti 0,8 μm2 in 564 celicami. Vse zasnove so simulirane s programom QCADesigner. Testi in simulacije dokazujejo premoč predlaganih vezij nad najboljšimi predhodnimi vezji glede hitrosti, števila celic in prostora, porabljenega za izvedbo. Ključne besede: polarni kodirnik, kvantne točke, mobilni avtomat, QCADesigner, nano povezljivost, nanoelektronski * Corresponding Author’s e-mail: cheenxf@163.com 1 Introduction technologies [1-3]. Because transistor-based tech- Broadly, research has been the hallmark of years gone nologies have reached their physical limit, they result by in finding a proper alternative to transistor-based in many pathologies, such as short-channel effects, How to cite: L. Dongdong et al., “Design and Efficiency Enhancement of Polar Encoder Based on Universal Logic Gates Utilizing QCA Technology", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 2(2025), pp. 87–94 87 L. Dongdong et al.; Informacije Midem, Vol. 55, No. 2(2025), 87 – 94 design variance, and heat. One of the most promising I. Offering the designs of single layer 2-bit, 4-bit, and alternatives is Quantum-dot Cellular Automata (QCA) 8-bit polar encoders in QCA; technology [4, 5]. These are due to the remarkable fea- II. Assessing the size, latency, cell counts, and logic tures and benefits of QCA, such as rapid switch speed, gate counts of suggested circuits; operation frequency in the terahertz rate, high device III. Evaluating the quantum cost and energy dissipa- density, and low power dissipation [6, 7]. It is because tion of suggested circuits. of the fantastic characteristics and advantages of QCA, including its rapid switch speed, terahertz operating As a result, a novel polar encoder circuit design and im- frequency, extremely high device density, and very low plementation were given in the current research. Sec- power dissipation [7, 8]. A number of different imple- tion 2 gives an overview of earlier efforts as well as the mentations, including atoms, molecules, and semicon- history of QCA. Section 3 presents the suggested polar ductors that have been studied based on electrostatic encoder circuit’s design, implementation, and simula- interactions, have been proposed to replicate bistable tion results. Section 4 provides comparison and evalu- and local QCA paradigm interactions. In addition, sev- ation charts and tables for significant QCA parameters, eral experimental gadgets have been built and success- and Section 5 presents this article’s conclusions. fully tested [9]. Due to the novelty of this technology, many researchers have presented different designs for different circuits, such as encoder circuits, adders, cal- culating units, subtractors, and polar code circuits [10]. 2 Backgrounds and related work Polar codes significantly reduce block error probability, with an asymptotic error exponent upper bound. How- 2.1 Preliminaries for QCA ever, the number of studies on polar encoders is rare, and there is a need to design faster circuits with fewer Recently, nano-designs have gotten much attention in cells and optimal space consumption [11]. Polar encod- many fields [14-16]. QCA provides a new idea in nano- ers are relatively new, having been first introduced in scale. The most fundamental unit of a QCA component is 2009 by E. Arikan [12]. A polar encoder is one that has K a cell. In a cell, there are two free electrons and four free inputs and N outputs (N,K). Its fundamental premise is quantum dots. Two free electrons are allowed to travel channel polarization to separate the noiseless channel freely amongst the four quantum dots and, through from the noisy channels [12]. electrostatic interaction, can achieve two stable states [17]. The binary “1” and binary “0” can be represented by In QCA technology, the role of a polar encoder has not the two stable states. Figure 1 depicts the fundamental been taken so serious, and there was a need to present components of the QCA technology [18]. Normal cells new circuits that realize the issue of a polar encoder as and rotated cells are two categories of QCA cells. The a critical aspect of this technology [13]. Ensuring reli- 2 stable states of QCA cells are shown in Figure 1 (a). ). able data transmission and securing the information Each cell in a mathematical sense can be described by of the users are very crucial. This demands presenting polarization P, whereby (Here p1, p2, p3, and p4 will be the function of a polar encoder in this technology. QCA the probabilities of the electron across the dots.): technology will be able to increase its potential in es- tablishing a safe transfer of data so that the important  p1 p3   p2 p4 information of the users can be protected by highlight- p   (1) ing the design of new circuits and appreciating the  p1 p2 p3 p4 worth of this topic. A polar encoder is to be designed in order to meet the growing demand of reliable data Figure 1 (b) shows a three-input majority gate, and transmission and strong protection of information in Figure 1 (c) depicts an inverter [11]. The inverter can QCA technology. It means that with respect to QCA reverse an input signal, whereas the 3-input majority technology, there are problems in the polar encoder gate can produce an output based on majority rules circuit, data transfer, and reliable information protec- [19]. We are aware of four different QCA models. There tion; apparently, what is demanded is sturdy designs at are numerous theories for each of the four schemes. fast speeds and few cells. In such a paper, the authors Both magnetic and molecular QCA cells can operate have proposed low-cell QCA-based polar encoder cir- steadily at room temperature [20]. The majority gate is cuit architecture at the nano-scale level. The designs regarded as the basic logic gate in QCA, defined by the are simple, adaptable, and realized in a single layer. The function: primary structural component of the circuit is the ma- jority gate. The suggested circuits are built and tested Majority (Input1, Input2, Input3)= using QCADesigner-E, a program for modeling QCA cir- = (Input1×Input2) + (Input1×Input3) + (Input2 × Input3) (2) cuits. The important contributions are as follows: 88 L. Dongdong et al.; Informacije Midem, Vol. 55, No. 2(2025), 87 – 94 This function provides the majority value of between Das and De [25] provided a QCA-based circuit for a polar inputs Input1, Input2, and Input3. The inverter is a simple encoder. Using a bottom-up approach, they designed gate that makes an inversion of the input state: a QCA-based polar encoder circuit that consumes low power at the nano-scale level. They also explored the Inverter (IN) = ( Out ) (3) impact of stuck-at-fault errors on generating valid po- lar codes and proposed test vectors to ensure proper circuit implementation. Notably, the proposed circuit boasts low energy dissipation, fast circuit latency, and a small device area. The results confirmed the circuit’s accuracy. However, this design suffers from inadequate performance and excessive cell usage. Figure 1: QCA Assemblies; (a) primary cells, (b) major- Finally, Ahmed, et al. [26] proposed a design of a QCA- ity gate, (c) inverter gate. based cost-efficient polar encoder. The use of polar en- coders in secure communication was discussed exten- The architecture of the QCA circuit heavily relies on the sively in this article, leading to the creation of a polar QCA clock mechanism. First off, it supplies the required encoder utilizing QCA technology. This encoder had an power to QCA circuits [21]. Second, it aids in data trans- area of 0.1944 μm2 on one layer and contained 600 cells. mission pipelining. In QCA, there are four clock zones The total area for implementing this circuit was 0.7225 (Zones 0-3), each of which is driven by a four-phase μm2. Due to the large number of cells, and also very clock signal [22]. Each clock zone has one of four phase high hardware implementation space, this design can- states, including Switch, Hold, Release, and Relax, using not be used practically, and the unavailability of easy (π/2) phase-shifted signals. The Switch state marks the access to the inputs and outputs is one of the impor- start of computation, whereas the Hold state maintains tant limitations of this circuit. polarization. The QCA cell is ready for the following computation during the Release and Relax stages [17]. 2.1 Related works 3 Polar encoder design The polar encoder represents a variety of fault correc- In this section, important encoder circuits in QCA tech- tion codes in communication systems that increase the nology are examined. reliability of data transmission. These codes are of great importance and a must due to their tremendous supe- Salimzadeh, et al. [23] proposed the design and imple- riority in transferring data without faults and their per- mentation of a fault-tolerant priority encoder. In this formance superiority compared with other methods. In study, a fault-tolerant priority encoder was designed, the polar encoder method of data encryption, informa- with a primary focus on providing a new fault-tolerant tion is divided into several blocks that are then mapped majority gate. Simulations were conducted using the to a set of binary symbols. This set of symbols then QCADesigner software V. 2.0.3, revealing improved per- combines the data with varying levels of confidence formance of the proposed structure. The problem with [27]. Finally, the data is transmitted through commu- this method is the use of many cells and its low speed. nication channels, and after receiving the information, the receiver extracts and sorts the data using a polar Also, Safoev, et al. [24] proposed a QCA-based priority decoder. These codes increase speed, reduce complex- encoder using the Toffoli gate. In the paper, it is sug- ity, and provide better security in public communica- gested that a reversible priority encoder be designed, tion channels. In general, it can be supposed that polar which has played a key role in addressing encoding encoders and decoders are very promising solutions for and decoding processes. This research pays attention safe communications at the nano level and in complex to QCA technology as a new technology for imple- circuits, and with new designs, their use will increase. menting reversible priority encoder circuits. This paper presents a new architecture for a reversible encoder. Figure 2 shows the schematic or block diagram of a A low-cost design for the Toffoli gate is presented to polar decoder and encoder for communication at the facilitate the implementation of the proposed revers- nano level. The schematic diagram includes various ible encoder circuit. The circuit has been tested with sections such as input and output values, communica- the QCADesigner simulation tool. The result shows it to tion channel, polar decoder section, and polar encoder have a correct operation. However, the problem in this section. In this schematic, to create a polar encoder, circuit is using the Toffoli gate since this gate is an old several GN bits are selected as information input, and gate with a low speed for generating the output. the rest of the inputs remain fixed. The frozen bits can 89 L. Dongdong et al.; Informacije Midem, Vol. 55, No. 2(2025), 87 – 94 be assigned a value of either “1” or “0”, but usually, they Table 1: The truth table for QCA-based G2 circuit are fixed at “0”. I1 I2 O1 O2 A straightforward recursive rule defines GN. G2 is cre- 0 0 0 0 ated initially, then G4 is formed by concatenating G2 0 1 1 1 units, and G8 is constructed by concatenating G2 and G4 units. To construct G2N, N copies of G2 and two copies of 1 0 1 0 G 1 1 0 1 N are utilized. The XOR gate is the fundamental build- ing block of polar encoder structures, specifically G2, G4, and G8. G2 requires only one XOR gate to produce the The implemented G2 circuit is used to create the G4 output, which has two inputs and two outputs. Table 1 circuit and this circuit is shown in Figure 4. This circuit presents the truth table for this gate. The design of G2 in uses 121 quantum cells in an area of 0.16 μm2 and has a QCA is shown in Figure 3, and it is created and simulat- latency of 1.50 clock cycles. It is also worth mentioning ed in the QCADesigner tool. The design is a single-layer that this circuit has 4 inputs and 4 outputs. As shown in structure with only 16 cells and a total area of 0.02 μm2, Figure 5, the G8 circuit has 8 inputs and 8 outputs and and it has a latency of 0.5 clock cycles. is implemented by combining 4, G2 circuits and 2, G4 circuits. Also, according to Figure 6, the G8 circuit is de- Figure 2: Data communication with Polar encoder [26] signed and implemented in one layer based on QCA technology and has accessible and convenient inputs and outputs. With a total of 564 cells, the proposed de- sign occupies a total area of 0.8 μm2 and has a latency of 3.5 clock cycles. Figure 3: The proposed QCA design for the G2 circuit Figure 5: The applied G8 block diagram The (8,4) polar encoder has the same structure as G8, but I1, I2, I3, and I5 are held at logic “0” as frozen bits. Fig- ure 7 illustrates the QCA layout for this structure, and its performance parameters are identical to those of the G8 structure. Consequently, this configuration includes four information bits (I4, I6, I7, and I8) and eight output bits. The design consists of a total of 560 cells, occupies an area of 0.8 μm2, and has a latency of 3.5 clock cycles. Figure 4: The proposed QCA-based G4 circuit The G2 polar encoder circuit with QCA uses the least num- ber of cells implementing a XOR gate that is necessary in 90 L. Dongdong et al.; Informacije Midem, Vol. 55, No. 2(2025), 87 – 94 3. Relaxation time: 1.00e-015 s 4. Time step: 1.00e-016 s 5. Total simulation time: 7.00e-011 s 6. High clock: 9.80e-22J 7. Low clock: 3.80e-23J 8. The clock’s amplitude factor: 2.0000 9. Permittivity relative: 12.900 10. The impact radius: 80 nm 11. Layer separation: 11.5 nm Figure 8 displays the simulation waveform, which ena- bles effortless verification of the structure’s functional- ity. Take, for instance, the scenario where I1 has a value Figure 6: The proposed QCA implementation of G of 0 and I2 has a value of 1. Under these conditions, the 8 outputs will be O1 = 1 and O2 = 1, with a delay of 0.5 clock cycles. This outcome can be cross-checked with the information in Table 1. The simulation waveform facilitates the equal ease of verification of all input and output combinations. Figure 9 illustrates the simulation waveform, which can be used to examine the simulation results. Suppose in- puts I1, I2, I3, and I4 have values of 1, 0, 0, and 1, respec- tively. In that case, the outputs will be O1 = 0, O2 = 1, O3 = 1, and O4 = 1. The same combination of outputs can be seen in the simulation waveform depicted in Figure 9. The output is generated with a latency of 1.5 clock cycles. All the input and output combinations can be Figure 7: The proposed QCA implementation of the validated similarly using the simulation waveform. proposed (8, 4) polar encoder Figures 10 and 11 depict simulation waveforms for encoding operations. The output of the G2 polar encoder the proposed G8 and polar encoder, respectively. The circuit can thus be expressed for this XOR gate as: simulation results include all possible inputs for both the execution circuit and the expected output, demon- XOR(I1,12)=I1⊕ I2 (4) strating the circuits’ accuracy. Likewise, by examining the simulation waveform, all input and output combi- The G4 and G8 circuits are cascaded from the basic G2 nations are confirmed. units. For the output in case of G4, it can be given by: G4 (I1, I2, I3, and I4 ) = XOR (XOR (I1,12) , XOR(I3,14)) (5) The G8 circuit extends this approach, with four G2 cir- cuits and two G4 circuits: G8 (I1, I2, I3, I4, I5, I6, I7, and I8) = = XOR (G4(I1, I2, I3, and I4),G4(I5, I6, I7, and I8)) (6) 4 Discussions The coherence vector and bistable vector characteristics are utilized in the simulation using the QCADesigner [18]. As described in [4], the simulation considers various parameters for coherence vector-based analysis: 1. Cell height and width: 18nm 2. Operating temperature: 1 K Figure 8: The simulation results of G2 design 91 L. Dongdong et al.; Informacije Midem, Vol. 55, No. 2(2025), 87 – 94 Table 2 provides a complete comparison of the pro- posed circuits and the best previous circuits in terms of cell count, area, and delay. The G2 circuit of the new im- plementation has 16 cells with an area of 0.02 μm2 and produces the final output after 0.5 clock cycles. Also, the G4 circuit of the new implementation has 121 cells with an area of 0.16 μm2 and produces the final output after 1.5 clock cycles. It should be noted that the G8 cir- cuit has 564 cells with an area of 0.8 μm2 and produces the final output after 3.5 clock cycles. Finally, the (8,4) polar encoder circuit has 560 quantum cells and is im- plemented in the space of 0.8 μm2. According to the values of Table 2 and also the complete Figure 12, it can be seen that the circuits provided in all compared cases have provided the best performance and results. Figure 10: The simulation results for QCA-based G8 cir- cuit Figure 11: The simulation outcomes of QCA-based po- lar encoder Table 2: Comparison between the proposed design and other state-of-the-arts Designs Area (µm2) Cells Latency Proposed G2 0.02 16 0.5 Proposed G4 0.16 121 1.5 Proposed G8 0.8 564 3.5 Proposed G (8,4) 0.8 560 3.5 Ahmed, et al. [26] G2 0.016 21 0.5 Ahmed, et al. [26] G4 0.132 133 1.75 Ahmed, et al. [26] G8 0.7225 600 3.75 Ahmed, et al. [26] (8,4) 0.7255 600 3.75 Figure 9: The simulation results of G4 design Das and De [25] G2 0.077 69 1.25 Das and De [25] G45 0.456 322 3.25 Das and De [25] G8 1.915 1188 6.25 Das and De [25] (8,4) 1.915 1188 6.25 92 L. Dongdong et al.; Informacije Midem, Vol. 55, No. 2(2025), 87 – 94 cycles, 564 cells, and an area of 0.8 μm2. Lastly, the 0.8 μm2 size, 3.5 clock cycle delay, and 560 cells were em- ployed in the suggested (8,4) polar encoder design. QCADesigner version 2.0.3 software was used to imple- ment these new circuits and compare them to the best existing circuits. The results showed the superiority of the circuits presented in cell count, area, and latency compared to the most recent circuits. Future works uti- lizing the concepts provided here might involve imple- menting bigger, more bit-intensive circuits through the use of QCA-based polar encoders and decoders, as well as more optimum circuit construction. Data Availability: The article contains all the data. Conflict of interest: No conflict of interest is found amongst the authors. 6 Acknowledgement Natural Science Foundation of Anhui Province (No.2008085MF215), Natural Science Research Pro- ject for Anhui Universities(No. KJ2021A0682, No. J2021A0662). Figure 12: Chart of percentage improvement and comparison of QCA-based polar designs. (a) area, (b) 7 References number of cells, and (c) delay. 1. C. Constantinescu, “Trends and challenges in VLSI circuit reliability,” IEEE micro, vol. 23, no. 4, pp. 14- 5 Conclusion 19, 2003, https://doi.org/10.1109/MM.2003.1225959. Emerging nanotechnology, known as QCA, has several 2. A. Yan et al., “Nonvolatile latch designs with node- noteworthy benefits, including reduced power dissipa- upset tolerance and recovery using magnetic tion, increased circuit density, and quicker speed. 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Raussendorf, “Subsystem symmetries, quan- Arrived: 26. 05. 2024 tum cellular automata, and computational phases of Accepted: 24. 11. 2024 94 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.203 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 2(2025), 95 – 102 Introducing EIS Circuit Elements in SPICE Simulator Environment Matevž Kunaver Faculty of Electrical Engineering, University of Ljubljana, Ljubljana, Slovenia Abstract: This study introduces hypothetical circuit elements, specifically the Constant Phase Element (CPE) and Zeroth-Order Approximation of a RC Circuit (ZARC), into the SPICE circuit simulation environment to enhance Electrochemical Impedance Spectroscopy (EIS) analysis. EIS, a critical method for understanding electrochemical processes in fields such as fuel cell analysis, corrosion studies, and biomaterials, relies on fitting measured impedance curves to Equivalent Electrical Circuit (EEC) models. However, existing approaches require expert knowledge and significant mathematical effort, limiting automation. By integrating CPE and ZARC into SPICE, this work bridges the gap between EIS analysis and advanced automatic circuit design methodologies, enabling efficient model selection and parameter determination. Experimental results demonstrate the accuracy of the implemented elements through a series of case studies, evaluated using Sheppard’s criteria function. This integration marks a significant step toward automated EIS model fitting and optimization, with potential implications for advancing electrochemical and materials research. Keywords: Electrochemical Impedance Spectroscopy, Circuit Simulators, Hypothetical Circuit Elements, Equivalent Electronic Circuits Vpeljava elemementov EIS v SPICE simlator vezij Izvleček: Ta študija uvaja hipotetične vezne elemente, specifično konstantnofazni element (CPE) in ničelni red približka RC vezja (ZARC), v simulacijsko okolje SPICE za izboljšanje analize elektrokemijske impedančne spektroskopije (EIS). EIS, ključna metoda za razumevanje elektrokemijskih procesov na področjih, kot so analiza gorivnih celic, študije korozije in biomateriali, temelji na ujemanju izmerjenih impedančnih krivulj z modeli ekvivalentnih električnih vezij (EEC). Obstoječi pristopi zahtevajo strokovno znanje in znatno matematično delo, kar omejuje avtomatizacijo. Z integracijo CPE in ZARC v SPICE to delo premošča vrzel med analizo EIS in naprednimi metodologijami samodejne zasnove vezij, kar omogoča učinkovito izbiro modelov in določanje parametrov. Eksperimentalni rezultati potrjujejo natančnost implementiranih elementov skozi serijo študij primerov, ocenjenih s pomočjo Sheppardove funkcije kriterijev. Ta integracija predstavlja pomemben korak proti avtomatiziranemu prilagajanju in optimizaciji modelov EIS, z možnimi vplivi na napredek raziskav na področju elektrokemije in materialov. Ključne besede: Elektrokemična Impedančna Spektroskopija, Simulatorji Vezij, Hipotetični Elementi Vezja, Ekvivalentna Električna vezja * Corresponding Author’s e-mail: matevz.kunaver@fe.uni-lj.si 1 Introduction The key technique in EIS is measuring the Imped- With the rapid growth of electrical storage, electric ance response and then fitting the resulting curve to vehicles, advanced materials and other technological a known Equivalent Electrical Circuit (EEC) model. This advancements there is also an increasing demand for approach requires some guesswork as the researcher methods that can offer a quick insight into any ongo- must select one of the known EEC models based on ing process or material to quickly detect and prevent experience and try to fit the model’s impedance curve possible incidents. One of such methods is Electro- to that obtained during EIS measurement. Each EEC chemical Impedance Spectroscopy (EIS) which can be model corresponds to one of the processes encoun- used for fuel cell analysis (in order to detect if a fuel cell tered in the field (so one model for a perfectly working is starting to deteriorate), corrosion science (analyzing fuel cell, one for a deteriorating fuel cell, one for a cell and simulating effects of corrosion on various metals), with corrosion on connectors etc.). If the model repre- Bio medics and process control. sents a good fit for the measured data, we can assume How to cite: M. Kunaver, “Introducing EIS Circuit Elements in SPICE Simulator Environment", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 2(2025), pp. 95–102 95 M. Kunaver; Informacije Midem, Vol. 55, No. 2(2025), 95 – 102 that we are dealing with the process described with the In the context of fuel cells, EIS is employed to analyze selected model. the performance and degradation mechanisms of these energy conversion devices. By applying EIS to The two major disadvantages of this fitting approach fuel cells, researchers can evaluate the impedance at are that it relies on expert knowledge, since only a sea- different frequencies to identify various components of soned observer can reliably select the most appropri- the cell’s resistance, including ohmic resistance, charge ate EEC when seeing the measured impedance curve transfer resistance, and mass transport resistance. This and that the approach also requires a lot of mathemati- allows for a deeper understanding of the fuel cell’s effi- cal work to fit the EEC circuit element values to the ciency, degradation, and overall performance, facilitat- measured data. ing improvements in design and operation. The field of automatic analog circuit design on the 2.2 Equivalent electric circuits and circuit description other hand offers several methods that could be used code to automate this procedure and reduce the required level of expertise. Several advanced techniques could The core of EIS consists of selecting a known circuit and potentially also determine the correct values of EEC el- seeing if it is possible to match its impedance curve to ements. All these techniques, however, face a problem measured data. – EEC circuits consist of several circuit elements (Con- stant Phase Element, ZARC) which do not exist in circuit These circuits are often described using the Circuit simulators used by these approaches. These elements Description Code (CDC) which describes circuits using don’t have a direct physical equivalent in a circuit and their elements (resistor as R, capacitor as C etc.) and are mostly represented by their transfer function. For parenthesis to describe their relation [1]. A CDC with- the purposes of this article we will refer to these ele- out parenthesis would describe all elements being in ments as hypothetical circuit elements to discern from series. Parenthesis denotes elements that are parallel those already implemented in circuit simulators. to each other. The aim of the research presented in this article is to correct this by introducing these hypothetical elements into SPICE circuit simulator and thus enabling future research into combining automatic circuit design tech- niques with the EEC circuits obtained from EIS. Figure 1: CDC example for a simple serial circuit (left) 2 Current state of EIS and a circuit with parallel elements(right) Current EIS techniques rely on a combination of Circuit Each EEC is therefore described with the appropri- Description Code (CDC) [1], circuit model selection and ate CDC code. Once selected it offers a mathematical mathematical modelling techniques such as the Leven- model to be fitted to the input curve. In the case of a berg–Marquardt Algorithm. RCL circuit the fitter would have to determine the cor- rect resistance (R), capacitance (C) and inductance (L) 2.1 Electrochemical impedance spectroscopy of the circuit. One should note that for the purpose of this article, we did not add any additional noise (Gauss- Electrochemical Impedance Spectroscopy (EIS) is a ian or any other model) since we were aiming to create powerful analytical technique used to study the elec- a circuit model that is a perfect fit to the mathematical trical properties of materials and electrochemical sys- model of our hypothetical elements. tems. By applying a small alternating current (AC) signal over a range of frequencies to an electrochemical sys- 2.3 Notable EEC components and their usage in tem and measuring the resulting voltage response, EIS modelling provides insights into the impedance characteristics of the system. This technique is invaluable for characteriz- While there are many different components used in ing the complex behavior of electrochemical reactions, EEC two of them tend to stand out and are used fre- interfaces, and materials. EIS is particularly useful in un- quently in fuel cell analysis. derstanding processes in fuel cells, batteries, corrosion studies, and other electrochemical devices. 2.3.1 Constant phase element (CPE) The CPE element [2] is used for modelling several sim- ple chemical processes in fuel cells such as porous elec- 96 M. Kunaver; Informacije Midem, Vol. 55, No. 2(2025), 95 – 102 trodes, the effect of surface roughness of electrodes, Examples of such techniques are reflective Newton type etc. method [6] and Levenberg-Marquardt algorithm [5]. CPE therefore simulates non-ideal capacitive behavior 2.5 Sheppard’s criteria function and deviations from standard capacitance. The math- ematical model of the element is given by equation 1: Once the mathematical approximation is complete the results are compared with the original impedance Z   1 curve using the selected criteria function. Since this is CPE   (1) Q  jn a curve fitting problem there are many possible criteria functions such as RMSE, MSE and R-square. In the field of EIS however it has been estimated that the Shep- where Q is the CPE constant, ω is the angular frequency pard’s criteria function [7] [1] performs best for the and n the CPE exponent (-1 < n ≤ 1), which describes measured impedance data, especially since it features the deviation from ideal capacitive behavior. A CPE an additional weight [8] to compensate the difference element with n=1, would therefore have the same fre- between imaginary and real data axis. We therefore quency response as an ordinary Capacitor. One should opted to use this function in our research. note that with fuel cells the value of n is usually be- tween 0.5 and 1. At 0.5 the CPE becomes the Warburg The criteria function is calculated using equations 3 element that is often used to study diffusion. In CDC and 4: the CPE element is denoted with the symbol Q. 2.3.2 Zeroth-order approximation of a RC circuit (ZARC) The ZARC element [3] is used for simulating impedance (3) response with multiple RC-like behaviors and complex impedance spectra. The impedance model of this ele- ment is given by equation 2: w 1 i   math 2 Re  math 2 (4) Z   R Zi  Im Z ZARC   (2) i 1 RQ  jn where wi represents the weight calculated from the in- where R is the resistance, Q is the CPE constant, ω is the put impedance data, Z math i represents the impedance of angular frequency and n is the order of approximation, the mathematical model (our target) calculated at the usually between 0.5 and 1, same as with CPE element. i-th frequency point and Z model i the measured imped- In CDC the ZARC element is represented by (RQ). [4] ance of our SPICE circuit at the same frequency point. 2.4 Mathematical modelling One should note that in cases of real measurements, the Z math gets replaced with Z measured Current EIS techniques [5] work by first performing a i i . frequency sweep of the selected process (circuit ele- ment, fuel cell or electrode) and measuring its imped- The result of the criteria function indicates the good- ance. Once the impedance is known the user must se- ness of the fit with lower values indicating a better fit. lect the EEC model that he/she thinks would fit best. In the event of a perfect fit the result would thus be zero. Once the model is selected, the user must also select the estimated starting values of each element in the 2.6 Our alternative approach EEC model (resistance, CPE constants, orders of ap- proximation…). These are then used with the selected The above techniques rely heavily on the user’s exper- mathematical approach to determine the best fit pos- tise and experience in addition to requiring a lot of in- sible for the selected model and the exact element val- put from him/her (the EEC model and its estimates). ues at the same time. If the chosen values are not ap- propriate, the procedure still converges to the correct In the field of circuit designs there are a lot of tools that result but requires more iterations to do so. It can also offer a certain level of automatization for circuit design lead to procedure getting stuck in a local minimum and and could potentially be used to help in this example producing incorrect results. This is a common issue in [9] [10] [11] [12]. Such techniques can be based on ge- EIS data fitting, which is why it is desired for the starting netical programming [13], evolutionary computation values to be close to the optimal values. with a pre-selected element layout [14] or even gram- 97 M. Kunaver; Informacije Midem, Vol. 55, No. 2(2025), 95 – 102 matical evolution [13] [15] [16] where one can create completely new circuits from the given electrical com- Modeling a device in frequency domain involves the ponents. computation of its admittance matrix. For CPE and ZARC this matrix reduces to a single element. Its value The only problem is that all such techniques require ac- can be computed by evaluating the inverse of the el- cess to circuit elements which in case of EIS is not pos- ement’s impedance at the frequency provided by the sible since CPE and ZARC do not yet exist in most cir- simulator. cuit simulators. The only known implementations are approximations using a long chain of RC elements as shown by Lopez [3]. Our aim is to create a single com- pact element that matches the mathematical model 3 Adding new elements to SPICE exactly. Our aim was therefore to take the elements required by We therefore decided to implement and evaluate these EIS (CPE and ZARC) and implement them in the circuit elements in the SPICE circuit simulator with the aim of simulator of our choosing (SPICE). We also considered developing an automatic EIS model selection algo- alternatives such as Verilog-A [17] but found that we rithm in the future. This required rewriting some of the could not use to correctly model the element in the fre- SPICE models and exhaustive testing. quency domain. We have also performed a series of evaluations where 2.7 Challenges with implementation of hypothetical we compared the mathematical model (i.e. the ideal) elements in circuit simulators with the results given by the simulator elements. Ide- ally, they should be as close as possible. In order to Due to the non-integer exponent of jω the transfer remain impartial, we used the same evaluation tech- functions of CPE and ZARC cannot be modeled nique as is used in measuring the fit between the curve with circuit elements like resistors, capacitors, and in- and the mathematical model in EIS – the Sheppard’s ductors. The fractional exponent also complicates the criteria function. simulation of such devices in the time domain where the usual approach is to use convolution with the im- 3.1 SPICE pulse response of the device. The impulse response can be obtained via inverse Fourier transformation of the Developed in the late 1970s at the University of Califor- device’s transfer function. Fortunately, impedance cal- nia, Berkeley, SPICE (Simulation Program with Integrat- culations are performed in the frequency domain ed Circuit Emphasis) [18] provides a comprehensive en- where the evaluation of CPE and ZARC involves only vironment for modeling and simulation of the behavior simple algebraic manipulations of complex numbers. of analog and digital circuits. The internal API of SPICE makes it possible to sepa- At its core, SPICE simulates the electrical behavior of rately describe the behavior of an element for the time circuits by solving the nonlinear differential equations domain and for the frequency domain. The model de- that describe the circuit components and their interac- veloper is responsible for making sure these two de- tions. It models the various elements of a circuit, such scriptions are consistent with each other. If one does as resistors, capacitors, inductors, diodes, transistors, not intend to simulate a device in time domain, it is and operational amplifiers, using mathematical equa- sufficient to provide the description of a device for fre- tions that represent their behavior. quency domain only. One of SPICE’s primary functions is to perform a DC Because CPE, ZARC, and all the EIS equivalent circuits operating point analysis, which calculates the steady- are linear the time domain description of CPE and ZARC state voltages and currents in the circuit. This analysis can be reduced to that of a simple resistor. This descrip- is essential for understanding the circuit’s behavior un- tion is used only in the computation of the operating der constant input conditions. Additionally, SPICE can point. Because the circuit is linear the linearizations of conduct AC analysis to determine the circuit’s response the elements which are used in the frequency domain to small-signal variations across a range of frequencies, analysis do not depend on the operating point. The op- providing insights into frequency response, gain, and erating point computation cannot be skipped thus one stability. has to make sure the simulator computes some operat- ing point that does not even have to reflect any physi- SPICE has become a cornerstone of electronic design cally meaningful behavior. and analysis due to its ability to accurately predict cir- 98 M. Kunaver; Informacije Midem, Vol. 55, No. 2(2025), 95 – 102 cuit behavior before physical prototypes are built. This are compiled with a C compiler and linked into a dy- capability significantly reduces development time and namic library. costs by allowing engineers to test and optimize their designs virtually. For each candidate circuit PyOpus [21] generates the circuit’s netlist comprising its topology and param- In addition to traditional circuit simulation, SPICE has eter values. The netlist also contains the commands been integrated into mixed-signal simulation environ- the simulator must execute to produce the circuit’s re- ments that combine analog and digital circuit analy- sponse. After the netlist is created PyOpus invokes the sis. This integration allows for comprehensive testing Spice Opus simulator which loads the netlist (Figure 2). of systems that involve both types of circuits, such as The dynamic library with the CPE/ZARC model is load- those found in modern microprocessors and digital ed into the simulator with the corresponding simulator communication systems. command (cmload) which is followed by the analysis command. The results are written into a SPICE RAW file In research, SPICE facilitates the exploration of new from which they are loaded by PyOpus for impedance circuit designs, materials, and technologies. Research- extraction and cost function computation. ers use the simulator to model innovative concepts, test hypotheses, and validate theoretical predictions. 3.3 Simulation and Evaluation This capability accelerates the development of cutting- edge technologies and advances the field of electron- The aim of our experiments was to match the theo- ics. retical (i.e. mathematical) circuit elements as closely as possible with simulated circuit elements in SPICE. We 3.2 Implementation of CPE and ZARC in SPICE first used the mathematical impedance model to cre- ate the baseline impedance curve and compared it Adding a new device to the SPICE simulator is a tedious with the SPICE simulation results. process. Fortunately, XSPICE extensions provide a sim- ple mechanism for adding new elements to SPICE. We 3.3.1 Input Data – Mathematical Model used Spice Opus [19] [20] which is based on the origi- For all our experiments we used the mathematical im- nal SPICE3 source code with added XSPICE extensions. pedance model of the selected circuit. We used the Spice Opus makes it possible to describe an element by models described by equations 1 and 2 computed at using the XSPICE API. The description is compiled into given points in the selected frequency range. a dynamic library which is loaded by the simulator at For some of the case studies we also added some runtime. Gaussian noise to the calculated impedance curve to see if it would have any effect on the final evaluation. In XSPICE one describes the behavior of an element in the frequency domain by specifying the real and the 3.3.2 Output Data – SPICE simulation imaginary parts of the transfer functions between ele- Our SPICE simulations used a simple circuit for measur- ment’s terminal voltages and branch currents. Because ing the desired impedance curve. both CPE and ZARC have only two terminals and one branch a single transfer function must be defined. For The system measured the voltage values at both ends CPE the transfer function at a given frequency f is of the subcircuit and then calculated the resulting im- pedance. We used the AC analysis with a frequency H Q 2 f n cos n / 2  iQ 2 f n sin n / 2 (5) sweep from 10-2Hz to 105Hz which is the usual range used in EIS measurements. Similarly, for ZARC we have Our experiment consisted of two circuit files – one for H  R1 1cos n / 2  iR1sin n / 2 (6) the main circuit (as shown on figure 1) and the other for the element setup we wanted to measure. This enabled us to perform a whole series of experiments by simply where Ω = (2π fτ )n and i is the imaginary unit. swapping out the subcircuit files. The element description is provided in two files. One 3.3.3 Evaluation specifies the element’s interface (terminals and param- Since we wanted to be able to compare our results to eters). The other specifies its inner workings. The latter those presented in other EIS articles, we used the same one is written in an extension of the C programming metric that is used by them – Sheppard’s criteria func- language. Both files are preprocessed by the XSPICE’s tion (see 2.5). The only difference is that we compared model compiler (cmpp) upon which the resulting files the impedance curve gained from the mathematical 99 M. Kunaver; Informacije Midem, Vol. 55, No. 2(2025), 95 – 102 Figure 1: Measuring circuit setup model (using equations (1) and (2)) with the imped- ance values obtained from the SPICE simulator. Every- Figure 2: Single CPE thing else remained the same – the lower the number the better our SPICE model matched the theoretical 4.2 Sigle ZARC element (RQ) mathematical model of the EEC element. For the single ZARC element we used resistance value 3.3.4 Experiment flow of 50Ω, CPE constant 0.01 and n value of 0.7 and again The main aim of our experiments was to prove that our added no additional elements to the subcircuit. The re- circuit model matches the theoretical model of each sulting Sheppard value was 7.09*10-13 with the model element. Instead of first calculating the model imped- and simulation data shown in figure 3. ance values for each frequency of interest and then comparing the result with the curve obtained from the SPICE element we made a slight modification. We first ran the SPICE simulation and collected both the impedance values, and the exact frequencies used by the simulator. We then used these points in the mathematical model to ensure a fair comparison. Lastly, we used the Sheppard’s criteria function to get the result. Figure 3: Single Zarc 4.3 Two parallel ZARC elements (R(QR)(QR)) 4 Case studies This was by far the most important experiment since there are a lot of cases where fuel cell measurements We tested three circuits that commonly occur in EIS result in the “double hill” curve which indicates that articles – a single CPE element, a single ZARC element there should be two ZARC elements involved. The EIS and two serial ZARC elements, combined with a resis- model adds an additional serial resistor, so we adjusted tor. The last circuit is also often used in Fuel cell EEC. our subcircuit accordingly. For each circuit, we first calculated the values of the mathematical models using equations 1 and 2. We The first evaluation featured ZARC elements with simi- then created an equivalent subcircuit netlist, ran the lar characteristics and is shown in figure 4. The circuit SPICE simulation and extracted the impedance meas- featured a serial resistor of 10Ω, first ZARC with (R=50 urements. Both the model and the measurements were Ω, CPE constant = 0.01 and n = 0.7) and the second with then used in our final evaluation using the Sheppard’s (R=50 Ω, CPE constant = 0.0001 and n = 0.7). The result- criteria function. One should note that at this stage we ing criteria function value was 2.17*10-12 which again used only mathematical models as input since we had show a good fit. to verify the fit of new circuit elements. It is however rare to have ZARC elements that are so 4.1 Single CPE element (Q) evenly matched, which is why we performed another evaluation and adjusted the second ZARC element to The single CPE element had the CPE constant set to (R=50 Ω, CPE constant = 0.01 and n = 0.45). The result- 0.01 and the n value to 0.8 with no additional elements ing fit is shown in figure 5. The value of the criteria func- in the circuit. As can be seen in figure 2 the model and tion was 2.54*10-12 which means that the fit remains simulation were a perfect match, with a Sheppard val- good despite a noticeable difference from the original ue of 7.1*10-13. curve shown in figure 4. 100 M. Kunaver; Informacije Midem, Vol. 55, No. 2(2025), 95 – 102 7 Conflicts of interest The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the deci- sion to publish the results. Figure 4: Double Zarc Model 8 References 1. B. A. Boukamp, “A Nonlinear Least Squares Fit pro- cedure for analysis of immittance data of electro- chemical systems,” Solid State Ionics, vol. 20, pp. 31-44, 1986, https://doi.org/10.1016/0167-2738(86)90031-7. 2. S. Kochowski and K. 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[Accessed 11 12 2024]. 102 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.204 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 2(2025), 103 – 114 Development of an Improved Zinc Oxide Thin Film Transistor for Next-Generation Smartphone Display Technologies Anindya Bose1, Sayori Biswas2, and Sarthak Sengupta3 1Electronics Engineering Division, 6th Generation of Computing, London, United Kingdom 2Department of Electronics Engineering, Jadavpur University, Kolkata, India 3School of Digital Health, IIHMR University, Jaipur, India Abstract: The study aims to create a portable and highly efficient Zinc Oxide (ZnO) Thin Film Transistor (TFT) on a single crystal Silicon substrate, followed by necessary electrical characterizations. The research explores relevant studies from around the world. The TFT has garnered attention worldwide due to its potential application in flat panel displays. The electrical and optoelectronic properties of ZnO-based TFT have also attracted significant interest. The figure of merit of a TFT is strongly influenced by crucial parameters such as on/off current ratio and field-dependent mobility, both of which are dependent on Transistor geometry, the crystallinity of the active layer, and the quality of the interface (such as semiconductor-insulator interface or metal-semiconductor interface). The growth and processing conditions of different layers impact these variables as well. The study presents the development of a low-powered and efficient bottom gate ZnO TFT on a p-type single-crystal Silicon substrate for next-generation laptop and mobile display segments. In this context, RF magnetron sputtering was used to create a bottom-gate ZnO-based Thin-film Transistor (ZnO-TFT) at room temperature. The ZnO-TFT operates in depletion mode with a threshold voltage of -1.2 V and exhibits a drain current on/off current ratio of 2 x 108. Maximum saturation mobility of 48 cm2/V-sec was recorded at VGS=24.1 V and VDS=10 V. This research study can be an opportunity for future researchers working in flexible smart panel display driving circuits. Keywords: Zinc Oxide, Maskless Lithography, RF Magnetron sputtering, Thin Film Transistor, Future display driver element. Razvoj izboljšanega tankoplastnega tranzistorja iz cinkovega oksida za naslednje generacije tehnologij za predvajanje na pametnih telefonih Izvleček: Cilj študije je ustvariti prenosni in visoko učinkovit tankoplastni tranzistor iz cinkovega oksida (ZnO) na monokristalni silicijevi podlagi, čemur sledijo potrebne električne karakterizacije. V raziskavi so preučene ustrezne študije z vsega sveta. TFT je po vsem svetu pritegnil pozornost zaradi možnosti uporabe v ploskih zaslonih. Električne in optoelektronske lastnosti TFT na osnovi ZnO so prav tako pritegnile veliko zanimanja. Na kakovost TFT močno vplivajo ključni parametri, kot sta razmerje med vklopnim in izklopnim tokom ter od polja odvisna gibljivost, ki sta odvisna od geometrije tranzistorja, kristaliničnosti aktivne plasti in kakovosti vmesnika (kot je vmesnik polprevodnik-izolator ali vmesnik kovina-polprevodnik). Na te spremenljivke vplivajo tudi pogoji rasti in obdelave različnih plasti. Študija predstavlja razvoj nizkozmogljivega in učinkovitega TFT z vrati iz ZnO na p-tipu monokristalne silicijeve podlage za naslednjo generacijo prenosnih računalnikov in mobilnih zaslonov. Pri tem je bilo z magnetronskim brizganjem RF uporabljeno za izdelavo tankoplastnega tranzistorja na osnovi ZnO (ZnO-TFT) z vrati pri sobni temperaturi. ZnO TFT deluje v načinu ponora z napetostjo praga -1,2 V in izkazuje razmerje vklopnega/izklopnega toka 2 x 108. Največja nasičena gibljivost 48 cm2/Vs je bila zabeležena pri VGS = 24,1 V in VDS = 10 V. Ta raziskava je lahko priložnost za prihodnje raziskovalce, ki se ukvarjajo s pogonskimi vezji prilagodljivih pametnih panelnih zaslonov. Ključne besede: Cinkov oksid, litografija brez maske, RF magnetronsko brizganje, tankoplastni tranzistor, element gonilnika zaslona prihodnosti. * Corresponding Author’s e-mail: anindya.nitdgp@gmail.com How to cite: A. Bose et al., “Development of an Improved Zinc Oxide Thin Film Transistor for Next-Generation Smartphone Display Technologies", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 2(2025), pp. 103–114 103 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 1 Introduction (ZnO) film as the active layer. The ZnO TFT, which has a channel width of 60 nm, was fabricated on a single-sid- A conventional technology extensively utilized in ed polished p-type <100> crystal-oriented silicon die new-generation flat-panel displays, laptops, desktop with dimensions of 2 cm x 2 cm. This device exhibits a high on/off drain current ratio of approximately 2 x 108 computers, smartphones, video gaming systems, and personal digital assistants is thin-film transistor (TFT) and a field-dependent saturation mobility of 48 cm²/ technology. Due to this technology, flat screens with Vs. ever-larger dimensions are now possible, revolution- izing video systems: The most common substrates be- A bottom gate TFT is developed where ZnO plays the ing used nowadays for the production of TFT-enabled pivotal role of the active channel layer. A thin layer of liquid crystal display (TFT-LCD) have a diagonal dimen- Silicon dioxide (SiO2) provides an isolation between sion of 164 inches. It took a long time for their fabrica- the p-type Silicon substrate and the conducting ZnO tion technique to advance to the point where it could channel. Source and drain metallic contacts are ap- be utilized in production, even though it has a history plied on the top of the conductive ZnO layer. The gate that is almost as old as CMOS technology [1]. There are contact terminal of the Transistor lies on the top of the three sides to the advancement and development of Silicon layer through which the modulation of charge TFT technology: the enhancement of the semiconduc- carrier concentration takes place inside the ZnO chan- tor layer, the stability of the manufacturing process nel. TFTs are a special class of Field Effect Transistor that for large-scale production, and the advancement of consumes current in the microampere range which is process machinery to create ever-larger devices. The a hundred times smaller than a conventional silicon first factor was primarily what initially slowed down MOSFET. It is also important that the size of the TFT is the massive development of this technology. TFT- much smaller than the conventional silicon MOSFET. LCDs have used this technology since it first appeared. However, some other applications have been critically reviewed over the past 20 years in diverse areas like X- 2 Literature review ray detection [2, 3], microelectronic devices-enabled memory [4, 5], chemical sensing [6], and bio-chemical A review of the literature was collected to explore rele- sensing [7]. The last field has seen a significant contri- vant research articles. TFTs are essentially MOSFET tran- bution from organic thin film transistors (OTFTs) [8]. sistors, and the first TFT was made in 1962, around two years after the first MOSFET [10]. The first TFT-LCD was The display industry makes extensive use of TFTs as demonstrated in 1973, establishing the primary course specific devices for data available in pixel display. TFTs for TFT technology research and development [11]. The also hold promise for flexible 3D ICs and large-area in- manufacture of TFTs and MOSFETs does not share the tegrated circuit applications. A type of flat panel display same challenges. This distinction explains why TFT- also known as Active Matrix LCD was made possible by LCDs took more than 20 years to become commercially TFT technology, which is majorly considered the main viable. The process steps are where the fundamental building block behind the display unit of laptop com- distinction between CMOS and TFT technology exists. puters. Flat panel displays are increasingly being used in place of cathode ray tube (CRT) screens in desktop While TFT technology just requires deposition, CMOS computer systems. Recent advancements in the mobil- technology also includes the steps of implantation and ity and stability of amorphous silicon, along with the layered growth from the substrate. This has significant higher manufacturing costs of polysilicon, have height- ramifications for the source, drain, and channel’s crys- ened interest in oxide semiconductors such as ZnO talline quality: the carrier mobility in CMOS is unques- and indium gallium zinc oxide (IGZO). Although some tionably better than in sin TFTs because of the crystal- special designs of ZnO-TFT with field-dependent satu- linity preservation with the implantation approach, ration mobility higher than 100 cm2/Vs have already whereas deposition only yields amorphous layers. TFT been reported [9] and the manufacturing process of technology, on the other hand, has a significant advan- such devices greatly used pulsed laser deposition (PLD) tage over CMOS technology in that since just a deposi- technique, which could restrict their use in large-area tion procedure is required, transistors may be made on and low-cost applications. RF Sputtering is a desirable virtually any substrate, including transparent materials deposition technique for the high-volume manufactur- like glass and plastic. That is why technology has always ers of oxide semiconductor devices, particularly ZnO, in been chosen for the creation of LCD screens. contrast to PLD. A CdSe TFT was introduced in 1973 [12, 13] after the In this study, we have demonstrated an efficient TFT CdS TFT, which was the first, was introduced. The car- device structure that utilizes an RF-sputtered zinc oxide 104 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 rier mobility of both was above 40 cm2/Vs, which was be used as the pressure sensor [13]. For example, when fairly good mobility. However, the application to LCDs TFTs are made on a flexible substrate utilizing organic never became commercially viable due to challenges TFTs (OTFT), this application of e-skin technology for in the fabrication process, such as the stability of the physical sensors has attracted a lot of interest from the semiconductor quality on a broad surface followed by robotics community [17]. In addition to that the appli- the reliability issues of the devices. cation of TFTs was also found in the field of uncooled infrared sensor arrays for thermal, pollution manage- Due to the invention of hydrogenated amorphous ment, or watching over semiconductor wafers while silicon (a-Si:H) at the beginning of the 1980s, which they’re being processed [18, 19]. significantly enhanced the stability and properties of TFTs, this technology underwent a significant advance- Recent advancements in electronic device design ment, enabling the production of active matrix (AM) emphasize power efficiency, scalability, and stability LCDs, and in 1989 the first TFT-LCD was commercial- across various applications, including IoT and biomedi- ized. Due to the advancement of other materials, the cal devices. For instance, a novel Sense Amplifier-Based semiconducting layer was then improved. A signifi- Flip-Flop (SAFF) demonstrated robust performance un- cant step in further enhancing the properties of TFTs der wide voltage and temperature variations, showcas- was the creation of transparent oxide semiconductors, ing significant power and area efficiency for IoT appli- such as IGZO. Due to the high carrier mobility and the cations [20]. Similarly, a high-performance frequency creation of transparent transistors, the LCDs’ aperture divider utilizing advanced CMOS technology achieved ratio increased while power consumption was further reduced delay and improved precision, making it suit- decreased [14]. Some other groups also reported po- able for biomedical applications [21]. These studies tential TFTs with high K gate dielectrics [15, 16, 25, 28] highlight the importance of innovative methodologies and in both cases, the performance of the device was to enhance device efficiency, scalability, and applicabil- found to be remarkably good in terms of its mobility ity. Building on these principles, this research employs and on/off current ratio. advanced nanofabrication techniques, including RF magnetron sputtering, to develop a ZnO TFT with a Another element of technological growth is product high on/off current ratio and superior field-dependent dimensions. The diagonal measurement of the first mobility, offering a low power solution for next-gener- TFT-LCD to be commercialized was 10.4 inches. The ation laptop and smartphone displays. 10th generation of mother glass, which corresponds to glass substrates as large as 2850 mm by 3050 mm, is now being used in TFT-LCD manufacturing facilities (164 in.). The 11th generation of mother glass, measur- 3 Theory and analysis ing 3200 mm by 3600 mm (189 in.), is now being devel- oped and ought to be put into use soon. Companies The semiconductor industry has experienced tremen- like SHARP, LG, Samsung, and Innolux, among others, dous expansion as a result of the dependence of daily have been working hard to develop stable processes life on its products. Achieving progress necessitates on large-scale substrates and to make progressively the creation of ever more compact devices that are huge equipment for the deposition, lithography, etch- also faster, more adaptable, more efficient, and less ing, and testing of even larger substrates. LCD panels expensive. To fulfill the demands of the expanding are the principal device that uses TFTs. TFTs are never- semiconductor industry, new technologies and materi- theless frequently utilized as sensors in X-ray detectors. als have been developed in response to this demand. In numerous sensing applications, TFT devices are also One of the newest and busiest fields of study is na- used. notechnology, which produces items with very small particles and unique features. Thin-film technology, Resistive pressure sensors are among the most used which enables the deposition of extremely thin layers physical sensors and were created for TFT touch pan- of semiconductor material on a supporting substrate els. Since the start of the 2010s, businesses like LG Dis- (from a few nanometers down to the angstrom level), play, AUO, and JDI have started producing them [12]. is crucial in this regard. Due to surface and quantum OLED and pressure sensor layers have been incorpo- confinement effects, the resultant material has unprec- rated into the TFT array substrate. In the latter, pressure edented mechanical, chemical, optical, and electrical is converted into an electrical signal that is then sent properties after being shrunk to the nanometer scale. to TFTs, which modulate and operate the OLED. A soft ZnO is an attractive material because of its superior polymer containing conductive particles or a pressure- electronic and optoelectronic properties. ZnO is excel- sensitive rubber with resistance that varies with pres- lent for a variety of devices because of its direct and sure, such as poly (methyl methacrylate) (PMMA), can wide band gap (i.e., 3.4 eV) nature along with large 105 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 exciton binding energy [22]. In the tetrahedral geom- etry of the crystal lattice, each Zn atom is surrounded by four O atoms, while each O atom is also surrounded by four Zn atoms. Rock salt, zinc blende, and wurtz- ite are the three crystal forms that ZnO can take. ZnO exists in wurtzite form at ambient temperatures [23]. The growth of ZnO on a cubic substrate can produce Figure 2: Mask Layout Design of a ZnO TFT in Clewin a stable zinc blende phase [24, 25, 26]. The lattice pa- Software rameters for the wurtzite structure are equal, between 3.2475 and 3.5201 angstrom, and between 5.2042 and 5.2075 angstrom. Strong ionic characteristics are seen in the link between Zn and O in the crystal lattice. ZnO is thus categorized as a compound that falls between an ionic and a covalent kind [23]. In this context, a necessary initiative is taken towards the fabrication and characterization of an efficient ZnO-based TFT structure with bottom gate arrange- ment. Fabrication of a TFT is a complex process and it occupies a lot of steps starting from mask layout design to the development of the end device on a single side polished <100> crystalline silicon wafer. Figure 1: Structure of proposed ZnO TFT Figure 3: Process fabrication steps In Figure 1, a two-dimensional design of a TFT is pro- posed where ZnO is the active layer. The Transistor will be developed on a p-type single crystal <100> silicon substrate. Source, Drain, and Gate metal contacts are made up of aluminium. Figure 2 represents the layout design of the ZnO TFT with a W/L ratio of 75/25. The light blue region represents the ZnO layer, and the pink-colored region represents the source and drains metal contacts respectively, and the dark blue region placed at the right side represents the bottom gate metal contact. One might find it confusing to compare Figure 2 with Figure 1. However, the process involved a blanket deposition of SiO2 on top of the silicon wafer. Following this, a square section was completely etched Figure 4: Complete process flow chart of ZnO TFT with away from the SiO2 using UV photolithography, indi- tentative step-by-step design cated by the shaded dark blue area. Later the bottom gate aluminium contact was deposited in that region. wafer. It is highly recommended to clean the silicon wa- fer before doing any process. Therefore, an RCA (Radio In Figures 3 and 4, a step-by-step process fabrication Corporation of America) cleaning was performed fol- method is given. Contamination is a big problem in lowed by a dilute HF dip just before the thermal oxida- the nanofabrication process so to minimize the effect tion process. of contamination a cleaning is a must for a fresh new 106 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 RCA Cleaning: The RCA cleaning is a three-stage clean- organic compound found in the solid form (i.e., a thick ing process and in the first stage the wafer is immersed substance) and upon UV exposure the exposed area in a mixture containing Deionized water, NH4OH, and becomes softer. That part can be removed by using the H2O2 in a ratio of 5:1:1. The solution temperature is kept proper developer solvent. 22 s of development of the constant at 75 °C during the cleaning process. Similarly, wafer in a solution containing MF26A (i.e., usually used the second stage of RCA cleaning was done at 75 °C for the development of positive photoresist-coated with the following quantities present in the mixture silicon wafers) gave the desired output and it was thor- (Deionized water and H2O2 and HCl) in the ratio of 6:1:1. oughly confirmed during a microscopic inspection. The total duration of the first and second stages of cleaning is around 20 mins (i.e., 10 mins for each stage). Wet Chemical Etching: Just after the photolithography The first stage of RCA is used to remove the inorganic process, the wafer was taken to the Chemical Wet etch oxides from the wafer surface and the second stage of bay to execute a SiO2 chemical etch process to remove RCA is used to remove metallic and ionic contaminants the SiO2 from the selective areas where the photoresist from the wafer surface. After the RCA process, one has is not present. A buffered oxide etchant solution was to clean the wafer using a solution containing a dilute used to etch the 200 nm thin SiO2. A wet etchant called Hydrofluoric Acid (i.e., a mixture of HF and wafer in a ra- buffered oxide etchant (BOE) is utilized in microfabrica- tio of 1:50) for 30 s. Silicon tends to react naturally with tion. Its main application is to etch SiO2 or silicon nitride atmospheric oxygen and in this process, a thin layer thin films (Si3N4). BOE contains a combination of Hydro- of native oxide develops on the surface of the silicon fluoric acid (HF) and a buffering agent like ammonium wafer. A dilute Hydrofluoric Acid (HF) dip completely fluoride (NH4F) whose work is to supply the fluorine removes the native oxides from the wafer surface. ion into the solution and to maintain the uniformity in etch rate. The optimized etch rate of the BOE solution Thermal Oxidation: Once after the cleaning process, was found to be 71 nm/minute after testing. The Silicon the wafer should be taken to the thermal oxidation wafer was dipped into the mixture for the desired time chamber without further delay. Dry oxidation is then duration to etch the thermal oxide completely from the performed inside the oxidation chamber at a tempera- selective area. ture of 1100 °C where silicon reacts with oxygen and a thin oxide (SiO2) layer of 200 nm is formed at the sur- Deposition of ZnO: After the completion of the SiO2 face of the wafer. The process duration was around four etching process, the substrate was sent for optical li- hours. thography since a lithography process must be per- formed before the deposition of the transparent ZnO Maskless Lithography: The lithography process used layer through RF (Radio Frequency) magnetron sput- in this study was performed with the Heidelberg μPG tering. The lithography process for ZnO is the same as 501, a direct laser writing tool that operates at a UV discussed before. The minimum feature size was found wavelength of 365 nm. This mask-less lithography to be 300 μm. method enables precise patterning of photoresist- coated substrates by directly writing the desired fea- One of the methods for depositing thin films that are tures without the need for traditional photomasks. This most frequently employed is sputtering. The substance approach offers enhanced flexibility and accuracy, es- from which a film is created or a plate with the mate- pecially for prototype fabrication. rials to be deposited serves as the target. The target often called the cathode, is connected to the nega- A maskless UV photolithography is then performed tive terminal of a DC (Direct Current) or RF power sup- for the selective etching of the thermal SiO2 layer from ply. It typically receives several kilovolts of electricity. the top of the wafer. A UV light source of 365nm wave- The substrate that is exposed to the cathode may be length was projected on the photoresist coated wafer grounded, electrically floating, biased either positive- surface in Figure 2. Laser/LED writing is a photolithog- ly or negatively, heated, chilled, or any combination raphy process that uses a laser beam or LED to create of these. After the chamber has been emptied, a gas the required patterns on the photoresist (direct writ- (typically argon) is added and used as the medium to ing). The Mask Writer’s unique feature is its ability to start and sustain a discharge. Typically, gas pressures generate patterns directly on any substrate using pho- range from a few to 100 mtorr. It is seen that current tolithographic principles, with or without the aid of a flows and a film condense on the substrate after a vis- traditional mask plate. Mask writers are primarily used ible light discharge has been maintained between the to create photolithographic mask reticles and masks electrodes. Of course, there is no current flow and no up to 5 inches in size for the Heidelberg uPG 501 sys- film deposition in a vacuum. Positive ions from the tem. AZ5214 type positive tone photoresist was used discharge interact with the cathode plate under a mi- during this process. A positive tone photoresist is an croscope and use momentum transfer to eject neutral 107 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 target atoms. These atoms enter the discharge region, have already been explained. The minimum feature travel through it, and then eventually deposit on the size of the aluminium mask was found to be 20 μm. All developing film. In addition, the target emits radiation the Photolithography steps included in this fabrication (X-rays and photons) as well as other particles (second- process were done inside a class 100 cleanroom under ary electrons, desorbed gases, and negative ions). yellow light ambient so that the unnecessary polymeri- zation of Chemical Photoresist can be avoided. The RF magnetron sputtering involves a thermal pro- cess where the sample is heated up to 100 °C using Deposition of Aluminium: An Aluminium layer of a halogen lamp. The ZnO deposition was done by RF 100 nm thickness was deposited using the electron magnetron sputtering through rotation mode. The ro- beam evaporation method and the rotation mode of tation mode was chosen to achieve good uniformity of deposition was preferred in our case because of bet- ZnO deposition throughout the desired area. ter uniformity during deposition. The metal is heated in the electron-beam evaporation process so that it can ZnO Lift-off Process: After the deposition process, the be deposited. Thin films are achieved through a con- ZnO-containing wafer was immediately transferred to trolled deposition. Solid sources are capable of deposi- the wet chemical bay for a lift-off process. It is noted tion of metals and dielectrics. The substance is held in that during photolithography a positive photoresist a water-cooled crucible and subjected to the electron was coated all over the wafer or sample and only the beam, which causes it to evaporate and condense on area exposed to UV rays doesn’t contain any photoresist the wafers/samples. The deposition is homogenous after the development. Inside the RF Magnetron sput- because of the planetary substrate rotation system. For tering chamber, the ZnO was deposited all over the wa- substrate heating, radiant heaters are offered. There is fer and it is expected that ZnO to be present only at the also an option for ion etching, ion-assisted deposition, place where it faces a SiO2. In the lift-off process firstly, and ion co-deposition. During the deposition process, the wafer is dipped into an acetone solution, and there- a pressure of 2 x 10−7 torr must be maintained. To re- fore applying extra acetone to the top of the wafer with duce source atom collisions with background material a high velocity. During this process, there was a peel- atoms, a high vacuum is required. off of the Photoresist which was present underneath ZnO. ZnO was also eliminated from the wafer surface Aluminium Lift-off Process: The aluminium (Al) lift- along with the photoresist. Only that part of ZnO will off process was done exactly in a similar way that has be stacked to the wafer which faces the underneath already been discussed in the case of ZnO lift-off, ZnO SiO2 layer. The process is very complex and it requires is exchanged by aluminium in this case. continuous microscope inspection but during micro- scope inspection, the wafer must be transferred into an IPA (Isopropyl Alcohol) solution because the volatile nature of acetone damages the microscope objective. The wafer can only be taken out from the chemical bay when a 100% elimination of the undesired ZnO layer is observed during microscope inspection. Rapid Thermal Annealing: A Rapid Thermal Process was done to establish a bonding between ZnO and Un- derneath SiO2 just after the lift-off process. RTP (Rapid Thermal Processing) technology rapidly heats silicon wafers to high temperatures, reaching up to 1100 °C in just a few seconds. However, to avoid dislocations and Figure 5: A single crystal silicon die containing two wafer breakage brought on by thermal shock, wafer ZnO TFT temperatures must be gradually lowered during cool- ing. Available gases include N2, Ar, O2, and H2. It can be Figures 5 and Figure 6 were captured just after the suc- used for Annealing Contact Alloying, Rapid Thermal cessful aluminium lift-off process, the transparent blue Oxidation (RTO), Rapid Thermal Nitridation (RTN), Den- area in Figure 5 and Figure 6 refers to ZnO and the alu- sification and Crystallization, Silicidation, etc. minium contact looks like a golden-shaded area. After all this process there was a need for aluminium Forming Gas Annealing: The device was subjected to a contact deposition at the source, drain, and gate ter- 15-minute forming gas annealing process at 400 °C in an minal. The photo-lithography process was repeated environment with a 9:1 ratio of nitrogen and hydrogen followed by aluminium deposition and lift-off which before being allowed to leave the clean room facility. 108 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 ZnO TFT’s transfer characteristics and output characteris- tics are shown in Figures 7 and 8, respectively, and an on/ off current ratio that was derived from Figure 7 was found to be in the order of 2 x 108. At VDS = 10 V and VGS = 20 V, the highest drain current was determined to be 1 x 10−3 A, while the minimum drain current was determined to be 0.5 x 10−11 A at VDS = 10 V and VGS = −1.2 V. Calculating the on/off current ratio was done using the data presented above. The Transfer Characteristics plot, however, makes it abundantly evident that our manufactured ZnO TFT is a depletion-type Field Effect Transistor with a negative threshold voltage. Figure 9 explains a functional relationship between the Figure 6: Zoomed view of a single TFT with a W/L ratio device mobility and the applied gate to source volt- of 75/25 age. The mobility of the transistor is an extraordinarily important parameter for describing the optimal per- formance of the resulting device on-chip. A very high 4 Result and discussion magnitude of field-dependent mobility is the reason for the presence of a polycrystalline ZnO channel layer TFT belongs to the family of new generation portable between SiO2 and metallic contact. With increasing Field Effect Transistors. Like all our conventional Field VGS, the ratio of free carrier to fixed charge at the grain Effect Transistors, it requires a thorough electrical char- boundaries increases in proportion to the charge den- acterization to be proven efficient in next-generation sity of induced free carrier, resulting in a reduction of mobile smartphone display technologies. The choice the potential barrier at the grain boundaries. A maxi- of active material always plays the most significant role mum saturation mobility of 48 cm2/Vs was recorded at in deciding the ultimate performance of the fabricated VGS = 24.1 V and VDS = 10 V. Some of the studies [28, 29, transistor in our case, which is ZnO. 31] were done in the past on ZnO nanostructures to prove their worth for potential high-speed device ap- In this context, a bottom gate ZnO TFT is fabricated on plications but this research clearly shows the novelty a single crystal silicon die under a centralized contam- of ZnO TFT in terms of speed and power consumption. ination-free Clean Room Facility, and after its develop- Furthermore, the magnitude of field-dependent mobil- ment, it is mounted on a Printed Circuit Board for prop- ity was compared with much recent literature shown in er electrical characterization. The final output wires Table 1 to conclude the superiority of this device. are connected to the relevant PCB electrical contacts designated as Source, Drain, and Gates, respectively, Figure 10 shows the Capacitance-Voltage character- to connect with the external Electrical probe station istics for a wide range of frequencies, from 1 kHz to 1 for characterization. All necessary transistor terminals, MHz. According to the plot at 1 kHz, the accumulation such as Source, Drain, Gate, and others, are wire bond- zone is shown by the left-hand region of VGS = −5V, the ed with the PCB electrical contacts. depletion zone is indicated by the region between −5 V and −1.2 V, and the strong inversion region by the A wafer level electrical characterization system also region immediately to the right of VGS = −1.2 V. The known as a DC Probe Station (PM5, Agilent Device Ana- observed value of gate oxide capacitance at the fre- lyzer B1500A with pulsed source of 5 MHz) was used to quency of 1 kHz was found to be 28.5 pF from the CV perform the IV and CV measurements for the specific characteristics plot. It is discovered that the estimated TFT. The characterization system’s fundamental char- value of VTH from the CV measurement curve is −1.2 V. acteristics include superior IV measurement perfor- Figure 9 shows a clear example of the shift in threshold mance: measuring resolution of 0.1 fA/0.5 μV, Measure- voltage towards the negative x-axis that interferes with ment features for the HV-SPGUs include direct control, the depletion-type operation of the TFT. At the point arbitrary linear waveform generating GUI, single and where the applied Gate voltage is larger than −1.2 V, multi-channel sweep, time sampling, list sweep, quasi- a strong inversion effect causes the n-channel to be static CV (using the SMUs), a 10 ns pulsed I-V solution is formed from the p-type silicon substrate. available for characterizing samples, and an integrated capacitance module supports CV measurements be- When a very high frequency (1 MHz) is reached, a dif- tween 1 kHz and 5 MHz. ferential change in capacitor voltage has no impact on the inversion layer charge. The differential change in 109 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 Figure 7: Drain current vs Gate to Source voltage plot Figure 10: CV characteristics plot of ZnO TFT of ZnO TFT charge carrier occurs at the meal as well as the space charge region of the p-type semiconductor substrate. Therefore, the capacitance achieves a minimum value. The frequency dependence of the Capacitance-Gate Voltage plot can be visualized in Figure 10. Figure 11: Transient response of ZnO TFT To measure the transient response of a ZnO TFT fab- ricated on a single-crystal silicon (100) substrate, a Source Measure Unit (SMU), such as the Keithley 2460, is typically used. The SMU applies a pulsed gate voltage (VG) to switch the device between its ON and OFF states, while a constant drain voltage (VD = 10 V) is applied, and the normalized drain current (ID) is monitored as Figure 8: Drain current vs Drain to Source voltage plot a function of time. The transient response curve in Fig- ure 11, showing ID versus time, provides critical metrics: the turn-on time (ton), defined as the time for ID to reach 90% of its steady-state value when VG transitions from OFF to ON, and the turn-off time (toff), the time for ID to drop to 10% of its steady-state value when VG transi- tions from ON to OFF. The fabricated ZnO TFTs, known for high carrier mobility, typically exhibit ton = 1.5 µs and toff = 5 µs. This setup and analysis highlight the de- vice’s suitability for high-speed electronic applications. The off current in the ZnO-TFT was measured at VDS = 10 V, and VGS = −1.2 V these values correspond to the depletion mode, ensuring the device operates at its minimum drain current (IDS,off), which aligns with the Figure 9: Field-dependent mobility plot threshold voltage (VTH) experimentally determined from the capacitance-voltage (C-V) characteristics. The choice of these bias values allows for an accurate on/ 110 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 off current ratio calculation, as VTH at −1.2 V, represents ZnO is typically found to have an n-type structure. This the onset of the depletion zone, consistent with the n-type is caused by structural point defects (vacancies transfer characteristics. The threshold voltage (VTH) was and interstitials) and extended defects (threading/pla- determined by analyzing the C-V curves, which delin- nar dislocations). The n-type conductivity of the ZnO eated the transition between the depletion and inver- lattice is due to oxygen vacancies. The pre-existence of sion regimes. This analysis confirmed the negative VTH n-type nature creates an n channel in the ZnO thin film observed in the transfer characteristics. structure, resulting in electrical conduction at VGS less than 0 volt and compels the TFT to be operated in the Sub-threshold conduction is a critical aspect of the depletion mode. ZnO-TFT, particularly for applications in energy-effi- cient display technologies where minimizing power Table 1: Different types of ZnO TFTs with their on/off consumption is essential. In the fabricated device, current ratio and saturation mobility values the sub-threshold leakage current, measured as the minimum drain current (IDS, min) at VGS = −1.8 V, is ap- Different types of ZnO TFTs Associated on/off proximately 0.0001663×10−11 A with a calculated sub- current ratio and threshold slope of 0.075 V/Decade using two sets of Saturation mobility values (VGS = −1.2 V, ID = 0.5 x 10−11 A) and (VGS = −1.8, ID = values 0.0001663 x 10−11A) putting into to relation mentioned Transparent ZnO thin-film on/off current ratio in equation (1) shown below, transistor fabricated by rf = 106 magnetron sputtering [32] saturation mobility = 2 cm2/V-s 1  ln Ds s  I Stable ZnO thin film transistors on/off current ratio   (1) by fast open-air atomic layer = 108  V  Gs  deposition [33] saturation mobility = 10 cm2/V-s This value indicates that sub-threshold conduction Improving the Gate Stability of on/off current ratio is minimal, highlighting the effective gate control ZnO Thin-Film Transistors with = 1.45 x 103 Aluminium Oxide Dielectric saturation mobility over the channel in the depletion mode. A low sub- Layers [34] = 0.24 cm2/V-s threshold leakage current reduces standby power con- Investigation on doping on/off current ratio sumption, making the device well-suited for portable dependency of solution- = 4.17 x 106 and low-power applications such as next-generation processed Ga-doped ZnO thin saturation mobility displays. The implications of sub-threshold conduc- film Transistor [35] = 1.63 cm2/V-s tion are closely tied to the sub-threshold slope, which Fully flexible solution- on/off current ratio determines the voltage required for an order-of-mag- deposited ZnO thin-film = 106 nitude increase in current. The reported low leakage transistors Saturation Mobility current suggests efficient control in the sub-threshold = 0.35 cm2/V-s regime. Including this discussion and potentially calcu- Characteristics of ALD-ZnO Thin on/off current ratio Film Transistor Using H2O and = 2 x 107 lating the sub-threshold slope based on experimental data would strengthen the analysis of the ZnO-TFT’s H2O2 as Oxygen Sources [37] saturation mobility suitability for display applications. = 10.7 cm2/V-s Effects of yttrium doping on on/off current ratio the electrical performances and = 107 Repeated measurements were conducted for key pa- stability of ZnO thin-film tran- saturation mobility rameters, including mobility and on/off current ratios to sistors [38] = 9.8 cm2/V-s ensure data reliability. The mobility of the ZnO TFT was Controllable Doping and Pas- on/off current ratio measured with a maximum uncertainty of ±1.2 cm²/Vs, sivation of ZnO Thin Films by = 105 derived from variations in multiple measurements. Simi- Surface Chemistry Modification saturation mobility larly, the on/off current ratio was determined with an er- to Design Low-cost and High- = 0.117 cm2/V-s ror margin of ±5%, calculated based on fluctuations in performance Thin Film Transis- the recorded drain current under consistent conditions. tors [39] These measurements were performed using an Agilent Impact of electrode materials on/off current ratio on the performance of amor- = 107 to 108 Device Analyzer B1500A with a pulsed source of 5 MHz, which has a resolution of 0.1 fA/0.5 µV for current and phous IGZO thin-film transis- saturation mobility tors [40] = 24 to 50 cm2/V-s voltage measurements, ensuring high precision. The re- ported data represent the mean values obtained from Table 1 gives a survey of all potential ZnO-based TFTs at least five measurements, with the standard deviations along with their on/off current ratios and saturation used to estimate the error margins. mobility values. Both of these parameters are extreme- ly crucial to determine the performance of a TFT. In 111 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 this context, the fabricated ZnO TFT on a p-type single a final VTH, final of −2.1 V. These observations confirm that crystal Silicon substrate not only exhibits an extremely the shift is attributed to charge trapping at the ZnO/ high value of on/off current but also exhibits a remark- dielectric interface and defect generation within the able magnitude of field-dependent saturation mobility channel or dielectric layer, highlighting the device’s that was never reported before which implies a largely stability under prolonged negative bias stress. This en- improved operating speed of the Transistor at the on- sures the reliability of the fabricated ZnO TFT for smart- state condition. phone display applications. The fabricated ZnO TFT has been compared against The term “improved” in the title is justified by the sig- amorphous silicon (a-Si) TFTs and IGZO TFTs, the most nificant advancements demonstrated in this study. commonly used technologies in display applications The fabricated ZnO Thin Film Transistor (TFT) exhib- that ZnO TFTs aim to replace. Amorphous silicon TFTs, its an exceptionally high on/off current ratio of 2×108 known for their low field-effect mobility (0.1–1 cm²/Vs) and a maximum field-dependent saturation mobility [1], dominate low-cost display applications but are of 48 cm2/Vs, outperforming many previously reported limited by slower response times. IGZO TFTs, with their ZnO-based TFTs (refer to Table 1 of the manuscript). significantly higher mobility (10–20 cm²/Vs) and excel- These parameters highlight superior switching behav- lent uniformity and stability, are more suited for high- ior and enhanced operational speed. Additionally, the end displays [14], [37]. In contrast, the fabricated ZnO use of RF magnetron sputtering at room temperature TFT demonstrates a remarkable field-effect mobility of ensures a cost-effective and scalable fabrication pro- 48 cm²/Vs, significantly surpassing both a-Si and IGZO cess compared to more expensive techniques like PLD, technologies. Furthermore, it exhibits a high on/off making it suitable for mass production. The bottom- current ratio of 2×108, outperforming many reported gate structure developed on a p-type single-crystal IGZO devices [37]. ZnO TFTs can also be fabricated us- silicon substrate ensures high device quality and com- ing cost-effective methods such as RF magnetron sput- patibility. These improvements position the ZnO TFT tering at room temperature [32], combining the per- as a promising candidate for next-generation display formance advantages of IGZO TFTs with the scalability technologies, addressing the demand for high-perfor- and affordability of a-Si TFTs. mance, low-power, and flexible devices, particularly in advanced laptop and smartphone displays. A comparative analysis with IGZO TFTs studied by Tap- pertzhofen et al., 2022, further underscores the com- The ZnO TFT fabrication process described in this study petitive performance of the ZnO TFT. While IGZO TFTs demonstrates significant potential for large-area display in Tappertzhofen’s study achieved saturation mobilities applications due to its scalability and cost-effectiveness. ranging from 24 to 50 cm²/Vs and on/off ratios up to The use of RF magnetron sputtering ensures uniform 108, depending on the electrode materials (Pt, W, or Ti) ZnO deposition across extensive surfaces, which is criti- [40], the ZnO TFT from our study matches these bench- cal for achieving consistency and reliability on large sub- marks with a saturation mobility of 48 cm²/Vs and an strates, such as Gen 10 or Gen 11 mother glass commonly on/off ratio of 2×108. Importantly, our research empha- used in the display industry. Maskless UV photolithog- sizes low-cost fabrication using RF magnetron sput- raphy, employed in this work, eliminates the need for tering and Al electrodes, whereas Tappertzhofen et al. expensive masks, enabling flexible and direct pattern- focused on optimizing IGZO TFTs with advanced elec- ing over large areas. This approach can be scaled using trode materials to enhance performance. Both studies industry-standard step-and-repeat or digital lithography highlight their devices’ potential for high-resolution techniques, further enhancing its applicability for mass and flexible display applications. The ZnO TFT stands production. The modular fabrication steps—such as SiO2 out for its balance of excellent performance and cost- etching, ZnO deposition, and Al metallization—can be effective manufacturing, making it a strong candidate easily adapted to automated processes and advanced for next-generation display technologies. systems like roll-to-roll sputtering for high-throughput manufacturing. Additionally, RF sputtering, a cost-effec- An experiment was conducted on the depletion-type tive alternative to methods like PLD, makes the process ZnO TFT with an initial threshold voltage VTH of −1.2 V economically viable for industrial-scale production. Fu- to study the effects of Negative Bias Stress (NBS). A gate ture work will focus on demonstrating the fabrication of voltage VGS of −6 V was applied for stress durations of large-area TFT arrays on substrates like flexible polymers, 10,000 s (2.8 hours) and 24 hours. The results showed a optimizing throughput and uniformity, and validating shift in threshold voltage ΔVTH of approximately −0.4 V performance, yield, and scalability for flat-panel display for the shorter stress duration, resulting in a final thresh- applications. old voltage VTH, final of −1.6 V. For the extended stress du- ration of 24 hours, the ΔVTH increased to −0.9 V, yielding 112 A. Bose et. al.; Informacije Midem, Vol. 55, No. 2(2025), 103 – 114 5 Conclusion 6. Liao F, Chen C and Subramanian V., “Organic TFTs as gas sensors for electronic nose applications”, This study demonstrated the successful development Sensors and Actuators B: Chemical, Vol. 107 No. 2, of a highly efficient ZnO-based Thin Film Transistor 2005, pp. 849-855. (TFT) fabricated using RF magnetron sputtering on a 7. Estrela P and Migliorato P., “Chemical and bio- single-crystal silicon substrate. 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Abstract: A dual-band, single-layer reflect array offering high gain has been developed for dual-polarized drone tracking applications. The reflect array unit comprises two center-notched spiral structures aligned orthogonally and is separated by an independent notch- perfect rectangle element. Based on the reflect array unit design, a single layer 7 x 7 array, totally 49 elements for Horizontally Linearly Polarized (HLP) Ku-band transmission (12.4 – 14.8 GHz) and 49 elements for Vertically Linearly Polarized (VLP) X-band reception (10.7 – 12 GHz is designed with the phase changes of over 75o. This phase changes is obtained by adjusting the length of the notched spiral patch within the unit cell. Two distinct horn sources has been implemented to energize the orthogonal ports, supplying separate linear polarization for each frequency band. The efficiency is about 18.2 to 22% across different frequency bands, underscoring the array’s suitability for Drone Tracking applications. From the performance measures, it is found that the proposed dual-band reflect array is more suitable for drone ground station tracking applications. Additionally, this proposed structure minimizes design complexity and meets specifications of a low profile antenna with a simple structure and reduced weight. Keywords: Dual-band, Reflect array, orthogonally linear polarization, single reflecting layer, Low Profile Dvopasovni odsevni niz za oddajnik/sprejemnik zemeljske postaje za sledenje dronov Izvleček: Razvit je bil dvopasovni enoslojni odbojni niz z visokim ojačenjem za dvo-polarizirane aplikacije sledenja dronov. Enota odbojnega polja je sestavljena iz dveh spiralnih struktur s središčnim zarezovanjem, ki sta pravokotno poravnani, ločuje ju neodvisni pravokotni element s popolnim zarezovanjem. Na podlagi zasnove enote odbojnega polja je zasnovano enoslojno polje 7 x 7, ki ima 49 elementov za oddajanje v pasu Ku (12,4-14,8 GHz) in 49 elementov za sprejemanje v pasu X (10,7-12 GHz) z vertikalno linearno polarizacijo (VLP) s faznimi spremembami nad 75o. Te spremembe faze se dosežejo s prilagajanjem dolžine spiralne zaplate z zarezami v enoti celice. Za napajanje ortogonalnih vrat sta bila uporabljena dva različna rogova, ki zagotavljata ločeno linearno polarizacijo za vsak frekvenčni pas. Učinkovitost je približno 18,2 do 22 % v različnih frekvenčnih pasovih, kar poudarja primernost polja za aplikacije sledenja dronov. Iz meritev učinkovitosti je razvidno, da je predlagano dvopasovno odbojno polje primernejše za aplikacije sledenja zemeljskih postaj dronov. Poleg tega ta predlagana struktura zmanjšuje zapletenost zasnove in izpolnjuje specifikacije nizkoprofilne antene z enostavno strukturo in manjšo maso. Ključne besede: Dvopasovno, odbojni niz, ortogonalno linearna polarizacija, en odbojni sloj, nizek profil * Corresponding Author’s e-mail: viwinsingh3@gmail.com How to cite: V. S. Yobuamalan et al., “Dual Band Reflectarray for Transmitter/Receiver Ground Station Drone Tracking Applications", Inf. Midem-J. Micro- electron. Electron. Compon. Mater., Vol. 55, No. 2(2025), pp. 115–125 115 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 1 Introduction Dual-band reflect arrays often use two layers, making them more complex and expensive to produce. They The transmit and receive (Tx/Rx) communication in also become heavier, which is not ideal for many uses. Drone Tracking Applications has garnered significant Single-layer elements are better because they are interest due to its ability to double the spectrum ef- cheaper, lighter and easier to make [19-23]. So, this ficiency. To achieve this, high transmit-receive (Tx/Rx) work focused on single layer elements Dual Band Re- isolation at the antenna layer is required, which helps flect Array for Tx/Rx Ground Station Drone Tracking Ap- reduce the complexity and cost in wireless communi- plications. cation systems. Hence, several Tx/Rx antennas like co- polarized shared aperture scheme with high isolation have been developed. However, extending these co- 2 Antenna design polarized designs to large-scale arrays can be complex. Thus, a formulated basic single-layer microstrip ele- Reflect array antennas known for their high gain and ment is shown in Figure 1a. simple feeding mechanisms have been formulated. It typically have narrow bandwidths, but modifying the (a) f/D ratio and aperture size can increase it by about 10% [1-2]. To make the aperture smaller and reduce cross polarization, the elements of the RA are fine-tuned us- ing a multilayered RAs. Although these are more con- structive but leads to misalignment errors [3]. Multilayer reflect arrays can enhance bandwidth by over 15%, though they are challenging to design, expensive to fabricate, and heavier than single-layer structures. To allow system frequencies to share the same aper- ture in a single layer, they need to be widely separated [4]. Thus, Multi-resonant single-layer elements achieve phase variation at two distinct bands by varying patch length. Three interconnected dipoles in a single layer achieve various polarizations, but wide spacing may lead to impractically large inner element spacing and (b) narrow element patterns [5]. A design of a wide band single layer reflect array antenna using a new broad- band cell is proposed [6, 7]. Single-layer dual-band circularly polarized reflect arrays combine devices op- erating on different frequency bands, though with rela- tively high side-lobe levels and cross-polarization due to high-frequency components [8]. Designs like a single reflecting layer with curved double cross elements ca- ter to dual-band linearly polarized operation. Dielectric Figure 1: Geometry of unit cell in mm (a) top view b) layers with phase delay lines and circular patches with side view slots are used for X-band and K-band operation. Addi- tionally, designs using square rings with slots and par- The radiating patches of the unit element module are allel dipoles in a single layer demonstrate phase shift in the shape of rectangular spirals. The rectangular spi- and operation in two distinct frequency bands. Circular ral patches are evenly spaced relative to the origin and patches added to ring structures with a single dielec- perpendicular to the axis of the unit cell. The horizontal tric layer offer dual-band capabilities. A dual-frequency centre notched spiral loop element is accountable for reflect array with three layers of patches of differing siz- the horizontal linear polarized reflect array, while the es is described, although it incurs significant process- vertical centre notched spiral loop element is account- ing costs due to structural complexity [9-14]. However, able for the vertical linear polarized reflect array. multilayer reflect array antennas restrict transmission phase, diminishing overall performance. Profile reduc- The notched rectangle element is positioned in the tion can be achieved by reducing the number of layers, middle between the dual elements for polarization di- resulting in low-profile structures with high radiation versity between the operating bands and to decrease efficiency and simple designs [15-18]. cross polarization. Horizontal and vertical elements 116 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 are positioned orthogonally and independently. This (a) single-layer component eliminates a number of design flaws that were present in the previous designs [24-26]. In this design, there are no spatial restrictions on the elements, and they are all independent of one another. By introducing a notch in the centre of a spiral struc- ture, perfect orthogonal linear polarization at two fre- quencies can be supported. The reflect array structure is very simple and easy to fabricate, and it provides a high degree of polarization diversity. By varying the horizontal spiral loop length L1 achieved nearly 75○ phase shift similarly the vertical spiral loop length L2 achieved nearly 78○ phase shift. The dual element changing their length provides the smooth phase re- (b) sponse independently. 2.1 Design and study of unit cell The unit cells are etched on a standard Taconic RF 35 substrate, which has a dielectric constant of 3.55 and a thickness of 0.76 mm. The ground plane for transmit- ting and receiving frequencies is a conventional cop- per plane. The floquet port is used to model the unit cell structures, and a periodic boundary condition is established. A comprehensive wave analysis is then performed using the incident plane that is normal to the unit cell axis. The unit cell for transmitter frequen- (c) cies is built for linear horizontal polarization. Similarly, the receiver is designed for linear vertical polarization. The unit cell performance is critical in determining the radiation performance of the planned array. To reduce phase errors, a phase range of 360 degrees or greater is required. Obtaining a smooth linear phase versus length response is also critical. The width L1 is changed to achieve a wide phase range for the transmit band’s centre frequency. The width L2 is changed to obtain a large phase range for the receiver band’s centre fre- quency [27]. 2.1.1 Phase ranges for transmit band and receive band (d) The required phase shift at each element in flat reflect array unit cell is obtained from [1], R  K0 di  xicosb  yi sinb  sin b  (1) where, K0 = propagation constant in vacuum, di = dis- tance from phase center of the horn feed to the indi- vidual cell, (xi, yi) = the co-ordinates of element i. (φb, θb) = beam azimuth and elevation angle from the source. Varying the length changes the impedance and there- fore the refection phase-shift is changed. To verify this, Figure 2: Reflection phase and magnitude of unit cell the reflected phase versus length response for the (a) Reflection Phase Ku-band. (b) Reflection Phase X- center frequency is examined for polarization modes band. (c) Reflection magnitude Ku-band. (d) Reflection and is shown in figure 2a and 2b. magnitude X-band. 117 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 Here, Ansoft HFSS simulation software, which provides remains low because the copper has good conductiv- master-slave boundaries and Floquet Ports to model ity and the substrate has almost no loss tangent. Since repeating structures has been utilised. By changing the the loss is very small, it doesn’t need to be considered length, a phase shift and a change in the magnitude of in the design of the refractory antenna. the reflection field can be achieved, as shown in Figure 2. To improve scanning gain, this design keeps the posi- A parametric sweep from 2 mm to 7 mm for L1 revealed tions of the feeding horns fixed. The Tx and Rx beams in a comprehensive reflected phase range exceeding 360 the boresight direction are mainly set by the elements degrees for transmitter center frequencies, as shown in lined up with the feeding horns. Figure 4 shows the Figure 2(a) within CST MWS environment, configured calculated radiation patterns based on the array factor for horizontal polarization (mode 2). However, in mode and element pattern. 1 (vertical polarization), the reflected phase range was limited to approximately 30 degrees (-140 to -170). For reception frequencies, it’s crucial that the reflecting element operates solely in linear vertical polarization, as confirmed by design findings. Remarkably, across all center frequencies in mode 1, an expansive phase range exceeding 360 degrees was observed, meeting vertical polarization requirements. Conversely, in mode 2, intentionally inferior performance was noted. Illus- trated in Figure 2(B), the phase response for L2 values from 1 to 4 mm emphasizes the unit cell’s exclusive op- erability in vertical polarization mode for receiver func- Figure 4: Radiation Patterns tionality, where it dominates in mode 1 and exhibits submissiveness in mode 2 within the complementary The array can produce broadside radiations in both configuration. main planes. The E-plane has normal radiation, but the side lobes in the H-plane are quite strong. This indicates The simulation results in Figures 2a and 2b show that that the phase distribution of the other half of the ar- the new unit cell has a wide linear phase range, about ray (along the positive x-axis) can impact the H-plane’s 500° and 300°, for the frequencies studied in the Ku and radiation performance (side lobes). To reduce these X bands. The graphs reveal that the phase response is side lobes, a phase distribution optimization scheme is similar at nearby frequencies. This feature can enhance introduced. Thus, the optimised design parameters of the bandwidth in both frequency bands. So it can con- the proposed antenna is depicted in Table 1. sidered that all the elements are normally illuminated. Table 1: Parameter value of the design As shown in Figures 2a and 2b, when L increases, the reflection phase curve becomes more linear and the Parameter Value (mm) phase range also increases. Additionally, the reflection N 0.2 magnitude changes as the length varies. Lc 1.5 Figure 3 shows the current distribution. Even though T 0.76 strong currents are generated on the resonator, the loss Tg 1 W1 7.5 W2 7 D1 7 D2 4.5 D3 1.25 Wu 19.3 Lu 19.3 G 1 Where, N - Centered notch size (in both horizontal and vertical) Lc -independent center notched rectangle element length, Figure 3: Current distribution T - Substrate thickness, 118 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 Tg -Air gap thickness, 3 Results and discussion W1 and W2 - vertical element width, D1 and D2 - horizontal element width, The unit cell elements were used to create a 7 × 7 array, Wu and Lu - unit cell length and width. resulting in a single layer that measures 135.66 mm by L1 and L2 - varying horizontal and vertical spiral length 135.66 mm. This array was made on a standard Taconic for phase responses. RF-35 lossy substrate, which has a dielectric constant of (a) 3.55 and a thickness of 0.76 mm, with a loss tangent of 0.0018. The elements of the array were etched onto the substrate. There is a 1 mm thin air gap layer between the substrate and the ground plane to allow for wide bandwidth. The required phase for each individual ele- ment, based on its position, is listed in Table 2 is calcu- lated using Equation (1). The array is simulated with the CST MWS time domain solver, with the normalized impedance set to 50 ohms before simulation. Radiation properties including main lobe level, main lobe beam width, and side lobe levels were examined. Figure 5 shows the fabricated single layer reflect-array antenna. Figure 6 shows the measurement setup. A 7×7 element reflect array was placed at a distance from the feed (b) horn, following the ratio f/D = 1. The feed horn was connected to a standard WR34 coaxial to waveguide adapter. The reflect array was tilted at 20° with a spacer and all these components were accumulated in a di- electric frame. The source center feed comprises a pyramidal horn an- tenna with an F/D ratio set to 0.8. A full wave analysis was conducted for all six frequencies. The array was modeled using a waveguide port. (c) Figure 6: Measurement setup for the proposed reflect array antenna. Figure 7 compares the measured and simulated gain radiation patterns. The measured and simulated pat- terns match well, although the measured gain is slight- Figure 5: Fabricated single layer reflect-array antenna (a) ly lower than the simulated gain. These differences Top View (b) Bottom view (c) Phase distribution diagram might be due to process errors and dielectric losses. 119 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 The results show that the fabrication process is range from 10 GHz to 12.5 GHz. effective. The transmission and reception effi- ciency of the reflect array antenna are 18% and These findings suggest that the developed prototype 22%, respectively. demonstrator exhibits good electrical performance and shows potential for applications in drone systems. Figure 8 shows a comparison of the relative magni- For performance comparisons, Table 3 lists recently re- tudes of the simulated and measured patterns at dif- ported designs of single-layer dual-band antennas. ferent frequencies. Table 3 shows a comparison of the fabricated reflect Figure 9 shows the measured S11 of the reflect array array with existing reflect array antennas. The results antenna. The S11 is below -14 dB in the frequency show that horn centre feed blockage reduces effi- (a) (b) (c) 120 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 (d) (e) (f ) Figure 7: Simulated and tested reflect-array co-polarization radiation pattern comparison and 3D radiation pattern of transmitter bands (a) 12.2 GHz (b) 13.5 GHz (c) 14.8 GHz, receiver bands (d) 10.7 GHz (e) 11.4 GHz (f ) 12 GHz ciency. When the number of elements and aperture 4 Conclusion size of the tested reflect array antenna are compared, the higher gain is achieved. Furthermore, the ability to This work developed a highly efficient 7 × 7 single- tune the phase of two bands independently simplifies layer reflect array antenna with dual linear polarized dual band independent pattern isolation shaping at modes designed for two distinct frequency bands. The the transmitter and receiver. incorporation of independent rectangular spirals for each band, along with strategically positioned notched square shapes within the unit cells, ensures effective 121 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 isolation between the dual elements. This proposed unitcell, owing to its simplicity and compactness. This unit cell design presents a promising solution for vari- simulations have yielded impressive gains, with values ous applications, including long-range communication ranging from 18.2 to 22 dBi across different frequency for drone ground stations, tracker antennas, radar sys- bands, underscoring the array’s suitability for high-gain tems, and CubeSat satellite communication prototype applications. Table 2: Amount of phase shift (Degrees) required at each element position in 7 × 7 array and (L1/L2) normalized values (mm) -146.6o 157.32o 122.6o 110.83o 122.6o 157.32o -146.6o (L1=5.95 mm / L2=4.47 mm) (6 / 4.55) (6.06 / 4.57) (6.07 / 4.6) (6.06 / 4.57) (6 / 4.55) (5.95 / 4.47) 157.32o 98.97o 62.72o 50.41o 62.72o 98.97o 157.32o (6 / 4.55) (6.15 / 4.58) (3.62/ 2.54) (3.65 / 2.55) (3.62/ 2.54) (6.15 / 4.58) (6 / 4.55) 122.6o 62.72o 25.45o 12.79o 25.45o 62.72o 122.6o (6.06 / 4.57) (3.62/ 2.54) (3.67 / 2.58) (3.68 / 2.6) (3.67 / 2.58) (3.62/ 2.54) (6.06 / 4.57) 110.83o 50.41o 12.79o 0o 12.79o 50.41o 110.83o (6.07 / 4.6) (3.65 / 2.55) (3.68 / 2.6) (3.7 / 2.62) (3.68 / 2.6) (3.65 / 2.55) (6.07 / 4.6) 122.6o 62.72o 25.45o 12.79o 25.45o 62.72o 122.6o (6.06 / 4.57) (3.62/ 2.54) (3.67 / 2.58) (3.68 / 2.6) (3.67 / 2.58) (3.62/ 2.54) (6.06 / 4.57) 157.32o 98.97o 62.72o 50.41o 62.72o 98.97o 157.32o (6 / 4.55) (6.15 / 4.58) (3.62/ 2.54) (3.65 / 2.55) (3.62/ 2.54) (6.15 / 4.58) (6 / 4.55) -146.6o 157.32o 122.6o 110.83o 122.6o 157.32o -146.6o (5.95 / 4.47) (6 / 4.55) (6.06 / 4.57) (6.07 / 4.6) (6.06 / 4.57) (6 / 4.55) (5.95 / 4.47) Table 3: Comparison of the tested reflect array with existing reflect array antenna Ref. Freq. No. of Sub- Elements Phase Gain (dBi) AE (%) Polari- Feed Element (GHz) strate Layer Range (degree) zation Type Type 5 10/22 Single + 360 / 360 23/ 30 41/ 42 Dual LP Center Independent ele- Airgap feed ment with space limit 7 20/ 30 Single More than 360 36/ 38 66.5/ 50 CP Offset Not an independ- feed ent element 9 X/ K Single + 400 / 500 26/ 29 47/25 Dual CP Offset Not an independ- Airgap Feed ent with circular shape 10 X/ Ku Single 530/ 780 23/ 25 46/33 CP Center Independent ele- Feed ments with space limits. Outer bor- der element gives space resistance. 11 X / Ku Single 550 / 600 28 / 31 50 / 51 Dual LP Center Independent Feed elements. Dual elements varying length in both Hor- izontal and Vertical 12 X / K Single + 400 / 400 27 / 31 63 / 42 Orthog- Center Not an independ- Airgap onal LP feed ent with circular shape 13 Ka / W Dual 500/ 500 44 / 49 NA LP Offset Independent ele- feed ments situated in different layers 16 13.5 / 22 Three + 400 / 400 22 / 26 33 / 27 Dual LP Center Independent ele- Two Airgap feed ments situated in different layers Proposed 10.7, Single + Air 750 / 780 19.72, 22, 47.8 / 21.3 Dual Or- Center Independent ele- work 11.4, Gap 19.99 /18.87, thogo- Feed ments with band 12 / 12.2, 18.14, 18.73 nal LP diversity. Not affect 13.5, 14.8 each other. 122 V. S. Yobuamalan et. al.; Informacije Midem, Vol. 55, No. 2(2025), 115 – 125 Figure 8: (a) Simulated H pattern at Receiver Band, (b) Simulated E pattern at Tx, (c) Measured H pattern at Rx, (d) Measured E pattern at Tx. 6 Acknowledgment The authors would like to thank DST-FIST for providing support facilities in the department of Electronics and Communication Engineering at SRM Valliammai Engi- neering College in Chennai, Tamil Nadu, India. 7 References 1. Imaz-Lueje, B., Prado, D.R., Arrebola, M. and Pino, M.R., 2020. Reflectarray antennas: A smart solu- tion for new generation satellite mega-constel- Figure 9: Measured S11 of the reflect array antenna lations in space communications. Scientific Re- ports, 10(1), p.21554. https://www.nature.com/ articles/s41598-020-78501-0 5 Conflicts of interest 2. Narayanasamy, K., Mohammed, G.N.A., Savari- muthu, K., Sivasamy, R. and Kanagasabai, M., 2020. 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Arrived: 27. 08. 2024 Accepted: 05. 03. 2025 125 126 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.206 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 2(2025), 127 – 136 An efficient Spotted Hyena Optimizer based Multi- user Detection for Polar Encoder Biju George George Alexander1, Ablin Rajathurai2, Albert Raj Anthonymuthu3 1Department of Electronics and Communication Engineering, Stella Mary's College of Engineering, Aruthenganvilai, Tamil Nadu, India 2Department of Electronics and Communication Engineering, Arunachala College of Engineering for Women, Manavilai, Tamil Nadu, India 3Department of Electronics and Communication Engineering, DMI Engineering College, Aralvaimozhi, Tamil Nadu, India Abstract: Polar codes are among the most efficient types of error correction coding. Currently, these codes are employed in 5G communication networks and are the leading contender for 6G. Symmetry is significant in coding and decoding techniques for polar codes. However, some algorithms have high latency, and low throughput but suffer from high computational complexity. To overcome these issue a novel efficient Spotted Hyena Optimizer based Multi-User Detection for Polar Encoder (SHO-MUD) has been proposed for enhancing the throughput and reduce the latency. To increase spectrum, throughput, and energy efficiency, the SHO-MUD technique that has been suggested combines a polar encoder (PE) multiplexed with OFDMA with parity check polar coding (PCPC). PCPC-PE uses a system-configurable transmission rate to increase diversity gain and coding process dependability. To achieve optimum resource use over several data blocks, users are scheduled using the Spotted Hyena Optimizer (SHO) approach in conjunction with the MPA. The SHO scheduling efficiently allocates and schedules resources, resulting in a throughput gain of 0.6 bits per second. The suggested system provides user fairness by assuring an equal throughput of 1.55 bits/sec for all users. Keywords: Polar Encoder; Multi-User Detection; Message Passing Algorithm: Spotted Hyena Optimizer; parity check polar coding Učinkovito zaznavanje več uporabnikov za polarni kodirnik na osnovi Spotted Hyena optimizatorja Izvleček: Polarne kode so ena najučinkovitejših vrst kodiranja za popravljanje napak. Trenutno se te kode uporabljajo v komunikacijskih omrežjih 5G in so glavni kandidat za 6G. Pri tehnikah kodiranja in dekodiranja polarnih kod je pomembna simetrija. Nekateri algoritmi imajo visoko latenco in nizko prepustnost, vendar trpijo zaradi visoke računske zapletenosti. Za odpravo teh težav je bil predlagan nov učinkovit optimizator Spotted Hyena za zaznavanje več uporabnikov (SHO-MUD) za povečanje prepustnosti in zmanjšanje zakasnitve. Za povečanje spektra, prepustnosti in energetske učinkovitosti predlagana tehnika SHO-MUD združuje polarni kodirnik (PE), ki je multipleksno povezan z OFDMA s polarnim kodiranjem za preverjanje paritete (PCPC). PCPC-PE uporablja sistemsko nastavljivo prenosno hitrost za povečanje raznolikosti in zanesljivosti procesa kodiranja. Za doseganje optimalne uporabe virov v več podatkovnih blokih se uporabniki načrtujejo z uporabo pristopa Spotted Hyena Optimizer (SHO) v povezavi z MPA. Načrtovanje SHO učinkovito razporeja in načrtuje vire, kar omogoča povečanje prepustnosti za 0,6 bita na sekundo. Predlagani sistem zagotavlja pravičnost uporabnikov z zagotavljanjem enake prepustnosti 1,55 bitov/s za vse uporabnike. Ključne besede: Polarni kodirnik; zaznava več uporabnikov; algoritem za posredovanje sporočil: Spotted Hyena; polarno kodiranje s preverjanjem paritete * Corresponding Author’s e-mail: biju04@gmail.com How to cite: B. G. G. Alexander et al., “An efficient Spotted Hyena Optimizer based Multi-user Detection for Polar Encoder", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 2(2025), pp. 127–136 127 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 1 Introduction - To ensure proper resource utilization of multi- ple data blocks, the users are scheduled by im- Polar codes (PC) have garnered significant interest for plementing the Spotted Hyena Optimizer (SHO) their capacity to accomplish successive cancellation technique along with the MPA. (SC) decoding and symmetric capacity on binary-input discrete memoryless channels. [1, 2]. After properly The remaining portion of the work has been followed combining the input bits of several copies of the chan- by, section 1 illustrates the introduction, section 2 rep- nel in a parallel concatenation scheme, the bit-channels resents the literature review, Section 3 illustrates the present different reliabilities [3]. Asymptotically, as the proposed model, Section 4 describes the findings from number of copies goes to infinity, a fraction of the bit- the experiment, and Section 5 depicts the conclusion channels becomes noiseless, while the remaining bit of the work. channels are rendered useless [4,5]. Encoding amounts to sending the data bits through the good bit-channels and the so-called frozen bits (usually zeros) through 2 Literature review the bad bit-channels [6,7]. In 2021 Krasser, F.G., et al., [16] provided a unique and Polar codes are intended to separate bit channels into effective test bench and implementation for a small the most and least reliable categories [8]. The least PC using an Intel DE10-Standard Development Kit for trustworthy channels are considered frozen, meaning a System on Chip Field Programmable Gate Array (SoC they record zero values while creating code words. The FPGA). An 11% boost in throughput over a reference most reliable channels are utilized to move information implementation for short PC is achieved by adopt- bits [9]. The way the polar codes are constructed de- ing fully-unrolled encoder and decoder architectures, termines how reliable the bit sequence is. There exist which also result in high throughputs while consuming methods for generating convolutional polar codes [11], very little energy. even if the majority of studies employ the traditional block structure given in [10]. Furthermore, polar codes In 2023 Zhai, Y., et al., [17] Developed a polar code gen- are joined with other codes to create a concatenated eration approach for the underwater acoustic channel code, which boosts productivity. A cyclic redundancy that significantly decreases complexity while meeting check (CRC) is therefore computed before to polar en- the necessity for practical UWC. The suggested con- coding in 5G NR, which significantly enhances trans- struction method and scheme also effectively ensures mission noise immunity. [12,13]. data transmission reliability, as demonstrated by lake- trial results under two different channel conditions. In 5G communication model, PC play a crucial role in several aspects, primarily in ensuring reliable and effi- In 2024 Pillet, C., et al., [18] describe a low-latency de- cient data transmission over wireless channels. PC are coding strategy for shorter PC based on automorphism utilized as the channel coding scheme in the control groups. The automorphism group of shorter polar channels of the 5G New Radio (NR) standard [14]. These codes, generated by two known shortening patterns, is control channels are responsible for transmitting criti- shown to be finite but not empty, allowing for reduced cal signaling information such as synchronization sig- polar code decoding with the Automorphism Ensem- nals, system information, and scheduling assignments ble (AE). Extensive simulation results for shorter polar [15]. By employing polar codes, 5G systems can achieve codes using AE are shown and compared to the SC-List high reliability and efficiency in transmitting these con- (SCL) approach. Shorter polar codes under AE have a trol signals, even in challenging wireless environments. block-error rate that matches or surpasses SCL while lowering decoding latency. The reliability order of bit-channels is not universal since it is determined by channel circumstances and code In 2023 Shreshtha, A. and Sarangi, S.R., [19] recom- length. Several approaches for designing frozen sets on mends an innovative way for appropriately using PC the fly with little complexity have been offered. The ma- encoders in a 5G base station. Additionally, we offer a jor contribution of the work has been followed by collection of novel resource allocation algorithms and - The proposed approach combines parity check assess their efficacy against similar methods in the liter- polar coding (PCPC) with a polar encoder (PE) ature in order to intelligently allocate user data packets and OFDMA multiplexing to improve spectral, across available compute nodes. Using our suggested throughput, and energy efficiency. optimization approaches, we save 17% on a 5G base - PCPC-PE to enhance the coding process reliability station. Simultaneously, we may enhance performance and diversity gain by employing a flexible trans- by 24% over a typical base station. mission rate on the system. 128 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 In 2019 Sharma, A. and Salim, M., [20] focused on chan- 3 Proposed methodology nel coding schemes, specifically for URLLC use cases in 5G New Radio (5G-NR), and analyzing the performance In this paper a novel efficient Spotted Hyena Optimizer of polar codes for the same. Polar codes are examined based Multi-User Detection for Polar Encoder (SHO- using a variety of performance settings for short block MUD) has been proposed for enhancing the through- lengths and low code rates, as required for the URLLC put and reduce the latency scenario. The extremely reliable polar code’s excep- tional error correction performance, along with its low Polar codes computational complexity and decoding delay, makes it a viable candidate in the URLLC channel coding com- Erdal Arıkan (Arikan, 2009) developed polar codes, petition. the first deterministic code architecture that achieves Shannon capacity with minimal encoding and decod- In 2021 Liao, Y., et al., [21] proposed a novel polar-code ing complexity. This section introduces PC and gives generation approach that avoids the need to sift and inspiration for our technique. select bit channels depending on dependability. It is proved that using this strategy to optimize polar-code synthesis for the SCL decoder is equivalent to maximiz- ing the anticipated benefit of traversing a maze. The simulation findings reveal that typical polar-code ar- chitectures built for successive cancellation decoders are no longer ideal for SCL decoding in terms of frame error rate. In 2020 Xu, W., et al., [22] suggested deep learning (DL) techniques to optimising polar belief propagation (BP) decoding and concatenated LDPC-polar codes. Nu- merical simulations reveal that there is no performance difference between 2-D OMS and accurate BP at varied code lengths. In 2022 Tseng, S.M., [23] employing LSTM for Polar code decoding with Markov Gaussian memory impulse Figure 1: Proposed Methodology noise channels. The proposed LSTM-based approach has a one-third bit error probability when compared 3.1 Polar encoding to typical SC/BP/SCL decoding algorithms for Markov Gaussian channels. It is also 5–12 times faster in execu- One linear block coding scheme, PC, encodes by modi- tion time and decoding delay. fying linear codes into systematic codes and decodes in a range of scenarios with little to no complexity. The In 2019 Wen, C., et al., [24] presented a technique that use of a PCPC determines the system’s dependabil- combines convolutional neural networks (CNN) and ity utilized a Polarization Weight (PW) evaluation and classic Belief Propagation (BP) decoding. We model enhances BER performance. The following equations the proposed method’s performance using 4QAM and describe the coding system for linear transformations BPSK modulation. The traditional real-valued CNN ap- over the field F. proach is extended to complex-valued ones using a QAM modulation method that is detailed. The findings U a1  bk1 indicate that lowering anticipated noise increases bit 0 o G1 (1) error rate (BER) performance. Where U a1 0 represents the code word, bk1 o represents In 2023 Hebbar, S.A., et al., [25] provide a novel CurRIc- the message word, and G1 represents the generator ulum-based Sequential neural decoder for Polar cod- matrix using eqn 1 ing (CRISP). The recommended curriculum is critical in increasing CRISP accuracy, as seen by comparisons to bk1  bk1 o Y , k o b 1 o Yu (2) other curricula. To the best of our knowledge, CRISP is the first data-driven decoder for PAC codes, and it The first part of bk1 o Y includes user information pro- works almost optimally on the PAC (32,16) code. vided by to enable a free interchange between each transmission cycle. 129 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 bk1Y  bk1 j 3.1.1 2D Spreader o o : jY (3) The 2D spreader receives the output from the SCMA The number of digits that are considered frozen at the encoder after that. Two-dimensional OFDM distribu- start of the decoding process is provided in the second tion allows for frequency reuse and frequency varia- section and is shown by  tion in a cellular environment. By allocating a portion of subcarriers to every receiver, OFCDM may provide multiple-access. Additionally, there is an increase in bk1Y  bk1 j o u o : jYu (4) throughput along with temporal and frequency di- versity. The provided symbol may be distributed using Combine the equation 3,4, and 5 will written by codes {+1, −1, +1, −1} in the time domain and {+1, −1} in the frequency domain. Effective transmission across U a1  bk1YG k 1 0 o 1Y  b  o YuG1Y u (5) a multipath fading channel is made possible by the 2D spreader. where, G1Y and G1Yb illustrates the sub-matrices of G1 with row indices Y and Y 3.1.2 IFFT and Cyclic prefix u. The non-systematic encoder is the name given to this kind of mapping. By appropri- Symbols that are sent are directed to the IFFT block, ately selecting the set Y’s size, the coding rate may be which performs 2D spreading and converts the fre- adjusted. quency domain vector signal into a time domain sig- nals. Guard intervals help prevent fading from many U a1  bk1  bk1 paths. The 2D spread data streams are fed into the IFFT 0 o YG1YX o YuG1Y c, (6) block in the following manner to provide the orthogo- U a1  bk1 k 1 nality of subcarriers: 0 o YG1YX  b  Y G YuX , (7) u o u 1 u  V 1 M  2m (8) k t   l Rect t mT e j2c/T c,v (10) c v0 The generator matrices PC with block size m is given as Where lc,v represents the cth transmitted symbol in the vth sub- G  H m (9) carrier. Prior to transmission to the base station, the signal is up-converted. 1 0 H    where, 1 1  illustrates the Kernel, and ⊗ de- 3.1.3 Multi-User Detection (MUD) via Message passing notes the Kronecker power. Algorithm MUDs are used on the receiving end to separate user data from non-orthogonal overlapping data. The num- ber of data layer collisions on each resource piece is decreased by the sparseness of the polar codewords. Multiple Access Interference (MAI) is the main fac- tor affecting MUD performance. The best perform- ing but most difficult approach for handling MAI is the optimal maximal a posteriori algorithm (MAP). A straightforward technique is needed to improve MAP performance. The serial MPA is an efficient method for scheduling in ascending order on the receiving side. The serial MPA algorithm’s convergence rate varies with scheduling, though. Consequently, an IWO-based MPA detection system is presented to improve its per- formance, which creates a path between the resource node and user node for an appropriate scheduling or- Figure 2: Polar codes encoder der. Figure 2. depicts a model for PC encoding operation 3.2 Polar decoding with (N, K, CC) and encoding decoding complexity. O(NlogN) A technique for deciphering communications in polar codes is called polar decoding. PC are a kind of error- correcting codes that express data using polar coordi- 130 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 nates. Polar decoding involves converting the received tion for the SHO. The spotted, striped, brown, and aard- signal’s polar coordinates to Cartesian coordinates be- wolf are the four recognized hyena species; they differ fore applying a typical decoding method to decode it. in size, behavior, and nutrition. Out of the three hyena Applications for polar decoding are numerous and in- species, the spotted hyena is the most proficient preda- clude data storage and wireless communication. tor. Spotted hyena females live in clans or groups. 3.2.1 Rician fading channel The Rician fading version is another statistical variant that implies that the sign consists of a resilient LOS el- ement and a random component. The LOS element is a linear channel with regular amplitude and segment that connects the transmitter and receiver. 2 P u  2 (11) 2 P u2  2 2 described as the scale parameter andRatio of power contributions from line-of-sight paths to other multipaths. Figure 3: Position vectors in two dimensions of spot- The second scaling factor for the distribution is Ω, ted hyena which represents the total power from both pathways. To create SHO, the hunting tactics and social dynamics Ω  u2  2 2 (12) of the spotted hyena are computationally constructed. The four stages of SHO include encircling, hunting, at- Ω  u2  2 2 described as the total power obtained tacking prey, and searching. Spotted hyena’s position across all routes. The received signal amplitude (rather vectors in 2d are given in figure 3. than the received signal strength) is then distributed using the following parameters in rice distribution 3.3.1 Encircling (RD). The function of probability density is In SHO, hyenas try to place themselves as close to the prey as possible, leading the group to that location. The optimal position is now approximated to be the loca- u2 P   (13) tion of the prey. Once they locate their meal, hyenas 1 P circle around it. First, the best member of the popula- tion is recognized, and others modify their views ac-  2   cordingly. The encircling mechanism is modeled by 21  P (14) equation (17).   a2 u2     Dihy  A Popy  y  Po  y (17)     f a | u, a   ex au  2 p    2 2 I    0  2 ( 5     1 )         Po  y 1  Popy  y  F Dihy (18) This leads to the following probability density function: Equation (2) defines parameter Dt as the distance be- tween a hyena and the prey’s position. Po  y 1 de-   2P 1a  P 1a2   P P 1  f a   expP   I0 2 a  16         ( ) notes the hyena’s newfangled location in the current  repetition. The current iteration is denoted by y in I n Equations (18) and (19), The algorithm iteration is y, this case, I0 is the first-kind modified Bessel function of and hyenas use this equation to gauge the distance to order zero at 0th order. their prey, surrounded by specific mechanisms. Equa- tions (20) and (21) calculate vector coefficients A and 3.3 Spotted hyena optimizer (SHO) F , using position vectors and element-wise multiplica- tion. The behavior of the spotted hyena, particularly its so-   cial relationships with other animals, served as inspira- A  2 qb1 (19) 131 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136      F  2d qb2  d (20) The ideal position is saved and updated by Po  y 1 in Equation (26), and The best agent’s position deter-     mines how the other search agents are positioned. d  5 IT 5  (21)  max   IT  3.3.4 Searching for prey T   his method depends on modifications to the vector Equation (5) shows that qb F that enable hunting (random search). The arbitrary 1 and qb2 are random vec- tors in the interval (0, 1), and that h drops linearly from 5 numbers that force the search engine to depart from to 0 during the iteration time. The maximum number of a reference hyena and are greater than or less than −1 iterations is indicated by the max are represented by F . When compared to the non-ran- IT option. An increased number of iterations is necessary to increase efficiency. dom search phase, the random search phase computes a search agent’s location based on the search agent’s 3.3.2 Hunting selection at random rather than using the current best Hyenas are mostly gregarious animals that hunt in search agent. The SHO may conduct a global search packs and are adept at locating prey. In order to statisti- thanks to this mechanism and |F| > 1. Both of these fac- cally explain hyena behavior, it is thought that the opti- tors highlight random search. mal search factor is an ideal component that knows the position of the prey. In order to identify the top search agent, other search agents’ band together and update 4 Materials and Methods the best results they have found which are given in equation (22), (23) and (24). In this section evaluates and compares the perfor- mance of the proposed SHO-MUD. The experimental     Di arrangement executed on PC with Windows 11, 13 hy  A Pohy  Pok (22) generation Intel (R) Core (TM) is 1335U 1.30 GH2.     Pok  Pohy  F Dihy (23)     Chy  Pok  Pok1  PokM (24) The first hyena’s ideal location is determined by the constraint Pohy, whereas the other hyenas’ location is indicated by Pok . Equation (10) is used to calculate the number of hyenas, which is displayed in Parameter M.      M  countns Pohy  Pohy1  Pohy2 ,..,Pohy  N  (25) The ns parameter in Equation (25) specifies the total Figure 4: Number of user vs Throughput number of solutions as well as all feasible solutions., where  N is a random vector in the interval (0.5,1). The Figure 4 depicts the analysis of throughput for each parameter C represents a set of the ideal solution’s hy user. In this scenario, the suggested throughput results number M. are compared to benchmark methodologies such as SoC FPGA [16], CRISP [25], and 5G-NR [20]. The SHO 3.3.3 Attacking Prey scheduling efficiently allocates and schedules resourc- The worth of the path hy is decreased with the purpose es, resulting in a throughput gain of 0.6 bits per second. of creating a mathematical model for the target attack. The suggested system provides user fairness by assur- The vector h can have its value reduced from 5 to 0 dur- ing an equal throughput of 1.55 bits/sec for all users. ing an iteration by reducing the change in the vector The overall Energy Efficiency of the proposed SHO- F. The pack of untainted hyenas is forced to outbreak MUD method is 1.6%. The throughput of the proposed the target if the value of F is |F| < 1, Which is given in model 1.34%, 1.36%, and 0.9% better than SoC FPGA, equation (26). CRISP and 5G-NR respectively.   C Po  y Figure 5 shows the variance in outage probability over 1  hy (26) M the Rician fading distribution. The projected outage probability is calculated depending on the number 132 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 of interfering signals. The proposed method is 19% Figure 7(a,b) shows the horizontal axis as the number whereas, existing SoC FPGA has 18.6%, CRISP has of times epoch. One epoch, out of all the examples, had 48.7% and 5G-NR has 51.23% respectively. one forward pass and one retrograde pass. The varia- tion in accuracy and loss with increasing epochs is seen in Figure 7(a,b). Figure 5: Rician Fading Distribution Outage Probability Figure 8: Normalized latency and computational com- plexity Figure 8 displays the computational complexity and la- tency values of the suggested design with N = 32, 768, which are correspondingly normalized by the recom- mended values. When the decoding converges and the amount of parallelism grows, each point displays a nor- malized value. In comparison to the suggested decod- ing, the proposed decoding flexibility reduces delay at the expense of computational complexity. Figure 6: Energy Efficiency Fig. 6, all techniques show an increase in energy effi- ciency as SNR increases. The suggested technique out- performs the existing SoC FPGA [16], CRISP [25], and 5G-NR [20] approaches in terms of EE. The average En- ergy Efficiency of the proposed SHO-MUD method is 31.1%. The BER of the proposed model 0.52%, 0.58%, and 0.89% better than SoC FPGA, CRISP and 5G-NR re- spectively. Figure 9: Convergence of iterations vs identification accuracy Figure 9 illustrates the convergence of the pro-posed and the basic technique. It is evident from the graph- ic that the suggested strategy outperforms previous approaches in terms of identification accuracy. With a 90.71% accuracy the proposed method performs better the existing techniques such as SoC FPGA has 5.02%, CRISP has 4.96% and 5G-NR has 3.44% respec- Figure 7: Performance based on training and testing sets tively. 133 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 for SNR = -8 dB is displayed in Figure 12. Every SNR re- ceived its own file, which was made. As a result, build- ing models for various SNR levels is made simpler. Fur- thermore, a larger random collection of SNR values has been generated, which may be utilized to train a global model that can forecast for any SNR value. Figure 10: Number of iterations vs BER Figure 10 displays a comparison of the detection scheme’s convergence behavior. When compared to the current serial and parallel MPA approaches, the suggested scheme exhibits a greater rate of conver- gence after at least two rounds. The average BER of Figure 13: Comparison analysis of existing deep learn- the proposed method is 7%. The BER of the proposed ing models model 5.02%, 4.96%, and 3.44% lower than SoC FPGA, CRISP and 5G-NR respectively. The accuracy obtained by ResNet, Alex Net, DenseNet, and suggested is 90.34%, 94.39%, 89.92%, and 99.5%, respectively, as Figure 13 illustrates. The suggested spe- cificities of 91.19%, 89.98%, 90.18%, and 99.7% were attained by ResNet, Alex Net, and DenseNet. ResNet, Alex Net, and DenseNet yielded the following recom- mended precision values: 89.58%, 93.87%, 91.49%, and 94.29%. ResNet, Alex Net, and DenseNet yielded the fol- lowing projected recall percentages: 93.51%, 89.59%, 92.87%, and 95.18%. ResNet, Alex Net, and DenseNet provide the F1 score, which is 90.31%, 89.98%, 87.89%, and 95.34%, respectively. The accuracy rate of the sug- gested is greater than that of the models in use at the moment. Figure 11: Target distribution for SNR = 4dB 5 Conclusions In this section a novel efficient Spotted Hyena Optimiz- er based Multi-User Detection for Polar Encoder (SHO- MUD) has been proposed for enhancing the through- put and reduce the latency. Using a SHO-based MUD method, the suggested technique lowers complexity and increases convergence rate in terms of iterations. It also lowers the Bit Error Rate (BER) and achieves im- proved throughput and energy efficiency, respectively. The SHO scheduling effectively schedules and distrib- utes the resources, increasing throughput by 0.6 bits/ sec. By guaranteeing an equal throughput of 1.55 bits/ sec for every user, the suggested technique accom- Figure 12: Target distribution for SNR= -8 dB plishes user fairness. The EE of the proposed method is17%, 18%, 23.2%, and 23% better than existing tech- Fig. 11 displays the values’ histogram at two distinct niques. Future research aims to assess how well the SNR levels, namely SNR=4 dB The target distribution 134 B. G. G. Alexander et. al.; Informacije Midem, Vol. 55, No. 2(2025), 127 – 136 suggested generalized rapid decoding applies to real- nication systems,” Multimedia Tools Appl. vol. 82, world multi-kernel codes. no. 24, pp. 36739-36768, 2023. http://dx.doi.org/10.1007/s11042-023-14507-w 8. M. Fletcher, E. Paulz, D. Ridge, and A.J. Michaels, 6 Acknowledgments “Low-Latency Wireless Network Extension for In- dustrial Internet of Things,” Sens. vol. 24, no. 7, pp. The author would like to express his heartfelt gratitude 2113, 2024. to the supervisor for his guidance and unwavering sup- http://dx.doi.org/10.3390/s24072113 port during this research for his guidance and support. 9. A. Alashqar, J. Alkasassbeh, R. Mesleh, and A. Al- Qaisi, “SDR implementation and real-time per- formance evaluation of 5G channel coding tech- niques,” AEU Int. J. Electron. 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PMLR. http://dx.doi.org/10.1109/isit50566.2022.9834589 Copyright © 2025 by the Authors. This is an open access article dis- tributed under the Creative Com- mons Attribution (CC BY) License (https://creativecom- mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 15. 07. 2024 Accepted: 07. 01. 2025 136 Call for papers Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 2(2025), 137 – 137 MIDEM 2025 60th INTERNATIONAL CONFERENCE ON MICROELECTRONICS, DEVICES AND MATERIALS WITH THE WORKSHOP ON ENERGY MANAGEMENT AND RENEWABLE ENERGY SOURCES October 1st – October 3rd, 2025 Ljubljana, Slovenia Announcement and Call for Papers GENERAL INFORMATION Chairs: The 60th International Conference on Microelectronics, Devices and Ma- terials with the Workshop on Energy Management and Renewable En- Prof. Dr. Barbara Malič ergy Sources continues the successful tradition of annual international Dr. Andraž Bradeško conferences organized by the MIDEM Society, the Society for Microelec- tronics, Electronic Components and Materials. The conference will be IMPORTANT DATES held in Ljubljana, Slovenia, from OCTOBER 1st – 3rd, 2025. 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