UDK 621.3:(53+54+621 +66)(05)(497.1 )=00 ISSN 0352-9045 Strokovno društvo za mikroelektroniko elektronske sestavne dele in materiale 3-2005 L _A Strokovna revija za mikroelektroniko, elektronske sestavne dele in materiale Journal of Microelectronics, Electronic Components and Materials UDK 621.3:(53+54+621 +66)(05)(497.1 )=00 ISSN 0352-9045 INFORMACIJE MIDEM 3 o 2005 INFORMACIJE MIDEM LETNIK 35, ŠT. 3(115), LJUBLJANA, SEPTEMBER 2005 INFORMACIJE MIDEM VOLUME 35, NO. 3(115), LJUBLJANA, SEPTEMBER 2005 Revija izhaja trimesečno (marec, junij, september, december), izdaja strokovno društvo za mikroeiektroniko, elektronske sestavne dele in materiale - MIDEM. Published quarterly (march, june, september, december) by Society for Microelectronics, Electronic Components and Materials ■ MIDEM. Glavni in odgovorni urednik Editor in Chief Dr. Iztok Šorli, univ. dipl.ing.fiz., MIKROIKS d.o.o., Ljubljana Tehnični urednik Executive Editor Dr. Iztok Šorli, univ. dipl.ing.fiz., MIKROIKS d.o.o., Ljubljana Uredniški odbor Editorial Board Dr. Barbara Malič, univ. dipl.ing. kern., Institut Jožef Stefan, Ljubljana Prof. dr. Slavko Amon, univ. dipl.ing. el., Fakulteta za elektrotehniko, Ljubljana Prof, dr. Marko Topič, univ. dipl.ing. el., Fakulteta za elektrotehniko, Ljubljana Prof. dr. Rudi Babic, univ. dipl.ing. el., Fakulteta za elektrotehniko, računalništvo in informatiko Maribor Dr. Marko Hrovat, univ. dipl.ing. kern., Institut Jožef Stefan, Ljubljana Dr. Wolfgang Pribyl, Austria Mikro Systeme Intl. AG, Unterpremstaetten Časopisni svet Prof. dr. JanezTrontelj, univ. dipl.ing. el., Fakulteta za elektrotehniko, Ljubljana, International Advisory Board PREDSEDNIK-PRESIDENT Prof. dr. Cor Claeys, IMEC, Leuven Dr. Jean-Marie Haussonne, EIC-LUSAC, Octeville Darko Belavič, univ. dipl.ing. el., Institut Jožef Stefan, Ljubljana Prof. dr. Zvonko Fazarinc, univ. dipl.ing., CIS, Stanford University, Stanford Prof. dr. Giorgio Pignatel, University of Padova Prof. dr. Stane Pejovnik, univ. dipl.ing., Fakulteta za kemijo in kemijsko tehnologijo, Ljubljana Dr. Giovanni Soncini, University of Trento, Trento Prof. dr. Anton Zalar, univ. dipl.ing.met., Institut Jožef Stefan, Ljubljana Dr. PeterWeissglas, Swedish Institute of Microelectronics, Stockholm Prof. dr. Leszek J. Golonka, Technical University Wroclaw Naslov uredništva Uredništvo Informacije MIDEM Headquarters MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenija tel.: + 386(0)1 51 33 768 fax: + 386 (0)1 51 33 771 e-mail: Iztok.Sorli@guest.ames.si http://www.midem-drustvo.si/ Letna naročnina znaša 12.000,00 SIT, cena posamezne številke je 3000,00 SIT. Člani in sponzorji MIDEM prejemajo Informacije MIDEM brezplačno. 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The Journal is indexed by (SI® for Sci Search®, Research Alert® and Material Science Citation Index™ Po mnenju Ministrstva za informiranje št.23/300-92 šteje glasilo Informacije MIDEM med proizvode informativnega značaja. Grafična priprava in tisk BIRO M, Ljubljana Printed by Naklada 1000 Izvodov Circulation 1000 issues Poštnina plačana pri pošti 1102 Ljubljana Slovenia Taxe Percue UDK621.3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)3, Ljubljana ZNANSTVENO STROKOVNI PRISPEVKI PROFESSIONAL SCIENTIFIC PAPERS I.Boerasu, B. En rico Watts, F.Leccabue: Morfološke in optične raziskave ultra tankih filmov PZT (20/80) 109 I. Boerasu, B. Enrico Watts, F. Leccabue: Morphological and Optical Investigation Of Lead Zirconate Titanate (20/80) Ultra-Thin Films M.Hrovat, D.Belavič, J.Kita, J.Holc, J.Cilenšek, L.Golonka, A.Dziedzic: Debeloplastni upori z nizkimi in visokimi odvisnostmi upornosti od temperature na LTCC substratih. 114 M.Hrovat, D.Belavic, J.Kita, J.Holc, J.Cilensek, L.Golonka, A.Dziedzic: Thick-Film Resistors With Low And High TCRs on LTCC Substrates G.Stojanovič, A.Maric, L.Živanov: Pregled različnih izvedb integriranih monolitnih transformatorjev 122 G.Stojanovic, A.Maric, L.Zivanov: Review of Various Realizations of Integrated Monolithic Transformers D.Osebik, R.Babič, K.Kovačič: Aritmetična-logična enota z zaporedno logiko za izračun utežne vsote s programirnimi vezjii 133 D.Osebik, R.Babic, K.Kovacic: Arithmetic Logic Unit for Weighted Sum Calculation with Programmable Logic Cell Array R.Benkovič, K.Kovačič, A.PIeteršek: Integralna nelinearnost določena z zaporedjem izbire tokovih virovv DA pretvornikih 140 R.Benkovic, K.Kovacic, A.PIetersek: Integral Nonlinearity Determined by Selection Order of Current Array Units in DA Converters B.Glažar, M.Jankovec, M.Topič: Razvoj GPIB krmilnika združljivega z USB 2.0 144 B.GIazar, M.Jankovec, M.Topic: Development of USB 2.0 compliant GPIB controller F.Pavlovčič, J.Nastran: Težnja kontaktnih materialov k tvorjenju električnih potegnjenih oblokov 148 F.Pavlovcic, J.Nastran: Affinity Of Contact Materials to Form the Electric Drawn Arcs APLIKACIJSKI ČLANEK 158 APPLICATION ARTICLE K.Steblovnik: Nove tehnologije in ergonomija v beli tehnik K.Steblovnik: New Technologies and Ergonomics In White Goods Predstavljamo podjetje z naslovnice 165 We Present Company From Front Page EMPS 2006 obvestilo o zbiranju prispevkov 167 EMPS 2006 Call for Papers NOVICE 168 NEWS MIDEM prijavnica 173 MIDEM Registration Form Slika na naslovnici: HYB d.o.o. ima dolgoletne izkušnje na področju proizvodnje debeloplastnih hibridnih vezij po naročilu in senzorjev pritiska za uporabo v medicini Front page: HYB Hybrid Circuits and Sensors Company has many years experience in the production of custom thick film hybrid circuits and pressure sensors for medical applications VSEBINA CONTENT Obnovitev članstva v strokovnem društvu MIDEM in iz tega izhajajoče ugodnosti in obveznosti Spoštovani, V svojem več desetletij dolgem obstoju in delovanju smo si prizadevali narediti društvo privlačno in koristno vsem članom.Z delovanjem društva ste se srečali tudi vi in se odločili, da se v društvo včlanite. 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Kot član strokovnega društva prejemate revijo »Informacije MIDEM«, povabljeni ste na strokovne konference, kjer lahko predstavite svoje raziskovalne in razvojne dosežke ali srečate stare znance in nove, povabljene predavatelje s področja, ki vas zanima. O svojih dosežkih in problemih lahko poročate v strokovni reviji, ki ima ugleden IMPACT faktor.S svojimi predlogi lahko usmerjate delovanje društva. Vaša obveza je plačilo članarine 25 EUR na leto. Članarino lahko plačate na transakcijski račun društva pri A-banki : 051008010631192. Pri nakazilu ne pozabite navesti svojega imena! Upamo, da vas delovanje društva še vedno zanima in da boste članstvo obnovili. Žal pa bomo morali dosedanje člane, ki članstva ne boste obnovili do konca leta 2005, brisati iz seznama članstva. Prijavnice pošljite na naslov: MIDEM pri MIKROIKS Stegne 11 1521 Ljubljana Ljubljana, september 2005 Izvršilni odbor društva UDK621.3:(53+54 + 621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)2, Ljubljana MORPHOLOGICAL AND OPTICAL INVESTIGATION OF LEAD ZIRCONATE TITANATE (20/80) ULTRA-THIN FILMS lulian Boerasu1, Bernard Enrico Watts2 and Fabrizzio Leccabue2 1 National Institute of Materials Physics, Bucharest, Romania 2lstituto IMEM/CNR, Parma, Italy Key words: Atomic Force Microscopy, Faceting, Optical Properties, Growth Mechanisms Abstract: Ultra-thin (<20 nm) lead zirconate-titanate films with Zr/Ti ratio of 20/ 80 have been deposited on single crystal MgO substrates by sol-gel techniques. Atomic force microscopy reveals a smooth surface consisting of pyramids or domes. The surface morphology is discussed in terms of a double-step growth process: epitaxial growth in the early stages followed by growth on screw dislocations. Measurements of the optical extinction spectra for the PZT (20/80) ultra-thin films are reported and modelled to extract the data on the energy gap. Morfološke in optične raziskave ultratankih plasti PZT (20/80) Kjučne besede: mikroskopija na atomsko silo, AFM mikroskopija, zirkonijevega titanata, optične lastnosti, mehanizmi rasti Izvleček: Nanesli smo ultratanke plasti ( <20 nm Jzlrkonijevega titanata z razmerjem Zr/Ti 20/80 na podlage iz kristalnega MgO s tehniko sol-gel. Preiskava z AFM mikroskopijo pokaže gladko površino sestavljeno Iz piramidastih ali kupolastlh struktur. Površinsko morfologijo razložimo z dvostopenjskim procesom rasti : začetna epltaksijalna rast, ki ji sledi rast na vijačnih dislokacljah. Prikažemo tudi meritve optičnega ekstlnkcijskega spektra ultratankih plasti PZT (20/80), ki jih uporabimo pri modeliranju In Izračunu vrednosti za energijsko režo. 1. Introduction Lead zlrconate tltanate, Pb(ZrTI)03 (PZT), ceramics have excellent ferroelectric and optical properties that make them useful for various electronic and optoelectronic applications /1 /. Due to the refractive index dispersion n (X), the low optical loss, high transmittance, together with the strong electro-optic Kerr effect, PZT thin films could also be used for optical and electro-optical applications, e.g. optical shutters and modulators /2/. Ultra-thin films (<20 nm) are particularly interesting in this respect since nonlinear effects become important if light can be confined within the film. Moreover, surface roughness becomes an Important parameter to control if one seeks to fabricate thin films with optimal optical properties. Recently, new devices have been proposed composed of arrays of ferroelectric nano-capacitors made by self-patterned ultra-thin films/3, 4/. Fundamental studies on ferroelectric properties show that the grain size and film thickness are important for the limit of ferroelectricity /5, 6, 7/. A number of papers /8-12/ have appeared recently covering different optical properties of ferroelectric PZT bulk ceramics and thin films. There Is a lack of information on optical properties of PZT ultra-thin films. Generally, transmission (T) and reflection (R) spectra are used to determine the optical properties i.e. the absorption coefficient (n), the extinction coefficient (k) and the energy band gap (Eg) of thin films. Modelling of these spectra Is very sensitive to errors, especially because different experimental set-ups are used. Usually, two methods are used for calculating the optical properties: the Swanepoel's method /11/ and transfer matrix formalism /12/. However, different characteristic values of the optical properties are obtained by applying these methods to the same sample /11,12/. This difference is coming mainly from the "resolution" method. The basics of the Swanepoel 's method consist in solving the equations for T and R of the light with wavelength A,. The system of equations for T and R has more than one solution, since T and R values vary to a great extent with X. The problem of guaranteeing that the system has a singular solution is solved using the maxima and minima of the transmission spectrum. Considering the Swanepoel's approach /11 / the experimental transmission spectrum is enclosed by the envelope function of the transmittance maxima (Tm) and by the envelope function of the transmittance minima (Tm) which are function of the wavelength X (Figure 1). The strong drawback of this method It is that it induces errors when one draws the envelopes. Recently, an alternative method has been proposed in order to determine the optical properties of ferroelectric thin films /12/. The key of the method consists of applying the transfer matrix formalism on modelling the complex dielectric function. The strong drawback of this procedure comes from the difficulty of the mathematical calculus that Is rather complex and very sensitive to errors. 114 I. Boerasu, B. Enrico Watts, F. Leccabue: Morphological and Optical Informacije MIDEM 35(2005)3, str. 109-113 Investigation of Lead Zirconate Titanate (20/80) Ultra-thin Films Č-H Figure 1. The Tm and Tm envelope of the experimental transmission spectra, according to Swanepoel's approach /11/. In this work, optical extinction measurements are proposed as a quality check of the films of PbZr0.20Ti0.80O3 as thin as 15 nm. Band gap energies (Eg) and the extinction coefficient (k) for these films are reported under the assumption of a direct band-to-band transition. 2. Experimental Stoichiometric PbZro,2oTio,8o03 films were prepared from the sols derived from methoxyethanol solutions. Lead acetate was dehydrated under vacuum (49 mbar) at room temperature for 15 hours. A 1M stock solution of Pb was obtained by mixing the anhydrous Pb(CH3COO)2 with 2-methoxyethanol followed by two vacuum distillations (60 mbar at 60 °C each) and dilutions with the solvent. Ti iso-propoxide and Zr n-propoxide were mixed with 2-methox-yethanol, followed by two vacuum distillations (66 mbar at 80 °C each). The resultant solution was mixed with the Pb stock solution and 2-methoxyethanol, Two vacuum distillations (66 mbar at 90°C) were again performed to complete the reaction and remove any remaining reaction byproducts. The Pb/Zr/Ti solution was partially hydrolysed with an equal volume of a 1 M water mixture in 2-methoxyethanol to obtain a 0.25 M sol. The films were deposited on MgO (001 ) single crystal substrates by spin-coating. Prior to deposition, the substrate was thermally treated at 1100 °C for 1 hr to obtain well-defined vicinal surfaces and a reproducible surface finish /13/. The sol was syringed through a 0.2 pm filter onto the substrate and spun at 6000 rpm/ 60 s. A two-step hot plate treatment was then used at 95 °C and 300 °C for 5 min each. Finally, the amorphous film was placed in an inverse-crucible configuration, together with some lead oxide powder to provide a lead oxide-rich atmosphere, and heated in a chamber furnace to 750 °C. The surface microstructure of the films was characterized with Atomic Force Microscopy (AFM; Nanoscope Ilia). The equipment allowed the determination of the average surface roughness for selected areas and line scans to determine peak to trough height differences. The optical extinction spectra were recorded at room temperature using a Carry 17D PC double beam UV-VIS-NIR scanning spectrophotometer. 3. Results and discussion 3.1. Atomic Force Microscopy The AFM images of the ultra-thin PbZro.2Tio.sO3 film, in Figure 2, reveal faceted structures that are either pyramids or domes/14/. The density ofthe pyramids is low, but these are very well defined, with a wide square base and four facets. The surface profiles indicate that the typical height ofthe pyramids is about 120 nm. The domes, which cover the majority of the substrate, are closely packed and have a square base top surface, and four faces. The film surface is smooth; the average root mean square (rms) roughness is 5 nm, calculated from the AFM data. The height of the domes and equivalents the thickness of the film were estimated at 15 nm. This was measured using a step, made during the sample processing. Three different structures, domes, super-domes and pyramids, were observed on tetragonal PZT (52/48) films deposited on Nb doped SrTi03 substrates /15, 16/. The morphology depended on the dilution of the precursor solutions and the crystallisation temperatures. In our work, only pyramids and domes were observed. As depicted in Figure 2, some of the domes resemble "super-domes" /16/, but this could be an artefact; the angle of the tip used for the AFM analysis is about 8°, which could blur the real profile /17/. A similar morphology to that seen in the present work has been reported for germanium grown on silicon by Metalorganic Chemical Vapour Deposition (MOCVD) /18, 19/. nm M 161. 0, 3.0 \ Figure 2. Atomic force microscope image of the surface of the PbZro.2Tio.8O3 film, deposited on single crystal MgO. 110 I. Boerasu, B. Enrico Watts, F. Leccabue: Morphological and Optical Investigation of Lead Zirconate Titanate (20/80) Ultra-thin Films Informacije MIDEM 35(2005)3, str. 109-113 It was mentioned that AFM revealed closely-packed domes having no holes or empty space in between them. The kinetic model, presented by Srolovitz /20, 21, 22/, explains the formation and evolution of holes in a continuous film as the direct result of volume diffusion and surface evaporation/ condensation. Lead diffuses readily from the bulk of the film to its surface in Pb(Zr,Ti)03. These phenomena lead to compositional inhomogeneities, due to segregation and evaporation. Additionally, this diffusion promotes the formation of capillary holes through the film thickness. Hence, the suppression of lead oxide surface evaporation by using lead oxide rich atmosphere also reduces the initiation of capillary holes and their further evolution. The very low roughness of the film could be explained by the following model of nucleation and growth. The base of the domes is wider than their height, suggesting that lateral growth preferentially takes place. In the early stages of crystallisation, the first 2 to 6 monolayers, perovskite nuclei having stoichiometric composition, form on the MgO surface /23/. These nuclei spread laterally and coalesce, due to the very good lattice match between the MgO (aMgo = 0,421 nm) and PZT (apzi = 0,414 nm), forming an epitaxial film. As the temperature increases, the film acts as a site for uniform growth in three dimensions, either perpendicular or horizontal to the substrate surface /23, 24/; in turn, large dome structures will grow. Strain induced dislocations are present not only at the film-substrate interface, but also develop in the growing epitaxial film. The dislocation periodicity decreases as the film thickness increases, due to the greater stress relaxation. Athighertem-peratures, the greater surface mobility increases the rate of growth on imperfections leading to a low density of large faceted pyramids resulting in smooth PZT film /25/. 3.2. Optical characterisation Optical extinction (E) spectra were recorded to characterise the optical properties and to determine the band transition energy of the ultra-thin film. Given the low density of pyramids, one can assume that the optical extinction is measured on a film, about 15 nm thick, composed of domes. An MgO substrate, heat treated at 1100 °C for 1 hour, was used as the reference body. The spectra are presented in Figure 3. A local maximum is present between 3 5-3.6 eV (Fig. 2). According to the Beer-Lambert law, the absorption coefficient (a) is related by the optical extinction (E) and film thickness (d) by the following relationship: e o c. O Figure 3. 3.0 4.0 h v (eV) Optical extinction spectrum of the PbZro.2Tio.8O3 film on MgO. versus wavelength. To our knowledge, this is the first report for k of ultra-thin PZT films. The latter is shown in Figure 4. a = E/ d (1) Figure 4. The extinction coefficient k of PZT (20/80) ultra-thin film on MgO as a function of the wavelength. The extinction coefficient of the film is nearly constant (k = 0,08) for X > 1 |im and rapidly increases for shorter wavelengths. This increase is related to an interband absorption in PZT (20/80). Moreover, for a direct band gap material, the absorption coefficient can be expressed as a function of the incident photon energy (hn): The extinction coefficient (k) is directly connected with the absorption coefficient by the relation /10/: a = 4 n k / X (2), where X Is the wavelength. Thus, the equation (1) and (2) could be used to obtain the dispersion relationships for k a =(A hv)(hv-Eg)1/2 where A is a constant and Eg is the band gap /10/. (3) Thus, the plot d(ln(ahv))/d(hv)vs. hv in Figure 5, will have a divergence at hv = Eg/26/, which corresponds to a transition energy of 3.52 eV. This is in reasonable agreement 111 I. Boerasu, B. Enrico Watts, F. Leccabue: Morphological and Optical Informacije MIDEM 35(2005)3, str. 109-113 Investigation of Lead Zirconate Tltanate (20/80) Ultra-thin Films 3.2 3.6 hv (eV) Figure 5. Plot of d(in(ah v))/ d(hv) vs. h v. The observed divergence at hv = 3,52 eV is attributed to a band transition. with the value reported in the literature for the band gap energy (Eg) of PZT (20/80) thin films /10, 26, 27/. Figure 6 is the plot of (ahv)2 vs. hv where a linear behaviour can be seen at high photon energies. Such behaviour has been observed for PZT materials and attributed to a direct band transition /10, 28/. o T* o > > JS £5 Figure 6. Plot of (ah v)2 vs. h v for the PbZro.2Tio.sO3 film. 4. Conclusions PZT (20/80) ultra-thin films have been deposited on MgO (001) substrate by sol-gel techniques. Dilute solutions and high rotation rates were utilized to obtain films approximately 15 nm thick. The surface morphology of the film was analyzed by AFM techniques, which evidenced a complex structure, consisting of pyramids and domes. The density of pyramids is low; however, the domes are closely packed and completely cover the substrate. This leads to a relatively smooth film. Optical extinction spectra permit the calculation of band transition energy equal to 3.52 eV. Linear behaviour at high incident photon energy indicates a direct band-to-band transition in PZT ultra-thin films. 5. Acknowledgements I. Boerasu wishes to thank the Consiglio Nazionale delle Ricerche and NATO for providing the opportunity to work at IMEM/CNR, Parma (Italy) through the NATO Outreach grant n. 215. 35. S. 6. References /1/ J. F. Scott, Ferroelectric Memories, Springer, Berlin (Germany), 2000. /2/ J. M. Herbert, Ferroelectric Transducers and Sensors vol. 3, Gordon and Breach Science Publishers, London (U.K.), 1985. /3/ M. Alexe, A. Gruverman, C. Harnagea, N. D. Zakharov, A. Pig-nolet, D. Hesse, J. F. Scott, Appl. Phys. Lett. 75 (1999) 1158. /4/ M. Alexe, J. F. Scott, C. Curran, N. D. Zakharov, D. Hesse, A. Pignolet, Appl. Phys. Lett. 73 (1998) 1592. /5/ J. Junquera, P. Ghosez, Nature, 422 (2003) 506. /6/ N. A. Spaldin, Science, 304 (2004) 1606. /7/ M.-W. Chu, I. Szafraniak, R. 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Shinozaki, N. Mizutani Thin Solid Films, 2 (1999) 166. /24/ K. S. Hwang , T. Manabe, T. Nagahama, I. Yamaguchi, T. Kum-agai, S. Mizuta, Thin Solid Films, 1-2 (1999) 106. /25/ G. J. Davies, Solidification and Casting, Applied Science Publishers, London (U.K.), 1973. /26/ S. K. Bera, S. Chaudhuri, A. K. Bandyopadhyay, B. R Chakraborty, A. K. Pal, J. Phys. D Appl. Phys. 34 (2001) 273. /27/ M. P Moret, M. A. C. Devillers, K. Worhoff, P. K. Larsen, J. Appl. Phys, 92 (2002)468. /28/ W. L. Warren, J. Robertson, D. Dimos, B. A. Tuttle, G. E. Pike, D. A. Payne, Phys. Rev. B, 53 (1996) 3080. 113 Dr. lulian Boerasu, National Institute of Materials Physics, Bucharest-Magurele. P.O.Box MG-7, Romania boerasu@infim.ro Dr. Bernard Enrico Watts, Istituto IMEM/CNR, Area delle Scienze 37/A 1-443010 Fontanini, Parma, Italy watts@imem.cnr.it Dr. Fabrizzio Leccabue, Istituto IMEM/CNR, Area delle Scienze 37/A 1-443010 Fontanini, Parma, Italy leccabue@imem.cnr.it Prispelo (Arrived): 22.06.2005 Sprejeto (Accepted): 30.09.2005 UDK621.3:(53+54 + 621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)2, Ljubljana THICK-FILM RESISTORS WITH LOW AND HIGH TCRS ON LTCC SUBSTRATES Marko Hrovat1, Darko Belavič2, Jaroslaw Kita3, Janez Hole1, Jena Cilenšek1, Leszek Golonka3, Andrzej Dziedzic3 1 Jožef Stefan Institute, Ljubljana, Slovenia 2HIPOT-R&D, d.o.o., Šentjernej, Slovenia 3Wroclaw University of Technology, Wroclaw, Poland Key words: thick-film, resistors, NTC, LTCC, interactions, electrical parameters Abstract: Low-Temperature Co-fired Ceramic (LTCC) materials, which are sintered at the low temperatures typically used for thick-film processing, i.e., around 850°C, are widely used for ceramic multi-chip modules (MCM-C). Thick-film resistors with lowTCRs (Du Pont, 2041, nominal sheet resistivity 10 kohm/sq.) and thick-film NTC thermistors with high negative TCRs (EMCA-Remex, 4993, nominal resistivity 1 kohm/sq.) which were developed for alumina substrates, were evaluated on glassy LTCC substrates. The electrical and microstrutural characteristics of films fired on alumina or co-fired on "green" LTCC substrates were compared. The electrical characteristics (TCRs, sheet resistivities and noise indices) of 2041 resistors fired on both substrates are similar indicating that the resistors are compatible with the LTCC material. In the case of the NTC 4993 thermistors the resistivities, beta factors and noise indices of the thermistors fired on LTCC substrates significantly increased, indicating the interactions between the thermistor layers and the LTCC substrates. The changes in the electrical parameters were attributed to the diffusion of a silica-rich phase from the LTCC into the thermistor films. Debeloplastni upori z nizkimi in visokimi odvisnostmi upornosti od temperature na LTCC substratih Kjučne besede: debeli filmi, upori, NTC, LTCC, interakcije, električne karakteristike Izvleček: Keramika z nizko temperature žganja (LTCC - Low temperature co-fired ceramics) se sintra pri temperaturah, tipičnih za debeloplastno tehnologijo, to je okrog 850°C. Uporablja se za izdelavo keramičnih večplastnih struktur (MCM-C). Debeloplastni upori z nizkimi TCR (Du Pont, 2041) in debeloplastni NTC termistorji (EMCA Remex, 4993), ki so bili razviti za žganje na inertnih ai2o3 substratih, so bili testirani na steklastih LTCC podlagah. Primerjane so električne in mikrostrukturne karakteristike plasti, žganih na ai2o3 in LTCC podlagah. Električne karakteristike (plastne upornosti, TCR in šum) 2041 uporov, žganih na obeh vrstah podlag, so primerljivi, kar pomeni, da so testirani upori kompatibilni z reaktivnimi LTCC podlagami. Za NTC 4993 termistorje so rezultati pokazali, da upornosti, beta faktorji (strmina odvisnosti upornosti od temperature) in šum narastejo po žganju na LTCC podlagah. Spremembe električnih karakteristik pripisujemo predvsem difuziji Si02 bogate steklaste faze med žganjem iz LTCC v NTC upore. Introduction Ceramic multi-chip modules (MCM-Cs) are multilayer substrates with buried conductor lines, which means they have a high density of interconnections. An additional advantage of the smaller size and higher density is the ability to integrate screen-printed resistors, or occasionally, capacitors and inductors. These screen-printed components can be placed either beneath the discrete components on the surface of the multilayer dielectric or buried within the multilayer structure. Low-temperature co-fired ceramic (LTCC) materials, which are sintered at the low temperatures typically used for thick-film processing, i.e., around 850°C, are widely used for the production of MCM-Cs, especially for telecommunications and automotive applications. LTCCs are either based on crystallisable glass or a mixture of glass and ceramics; for example, alumina, silica or cordierite (Mg2AI4Si50i8) /1-6/. The composition of the inorganic phase in most LTCC tapes is similar to, or the same as, materials in thick-film multilayer dielectric pastes. To sinter to a dense and non-porous structure at these, rather low, temperatures, it has to contain some low-melting-point glass phase. This glass would (or could) presumably interact with, for example, thick-film resistors leading to changes in the electrical characteristics. Some of the results for the resistor/LTCC combinations and the influences on the electrical characteristics can be found in /7-10/. The main required characteristics for thick-film resistor materials are a long-term stability and relatively narrow tolerances of the sheet resistivities after firing. A very important characteristic is a low temperature coefficient of resistivity (TCR), which for most modern resistors is around or under 100x10"6/K. However, for temperature-sensing or temperature compensating applications the resistors with a large temperature dependence of resistivity - thermistors-are required. The thermistors with negative TCRs have very large and strongly non-linear temperature vs. resistivity dependence. The dependence of the specific resistance pvs. temperature is described by: 114 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Thick-film Resistors with Low and High TCRS on LTCC Substrates Informacije MIDEM 35(2005)3, str. 114-121 p = po x exp(B/T) (1) where po is the resistivity (ohm.cm) at "infinite" temperature, T(K) is the temperature and B (K) is the thermistor constant (also called the beta factor or the coefficient of temperature sensitivity). Resistivity at "infinite" temperature is determined by the total number of "B" lattice sites in a spinel structure that can take part in the "hopping" conductivity process (there is no contribution to the overall conductivity if ions with different valences are on the A sites because the distance between the two A sites in a spinel lattice is too great for an electron "hopping" mechanism). The B is defined as the ratio between the activation energy for electrical conduction and the Boltzman constant. Basically it is a "steepness" of the resistivity vs. temperature curve. For the calculation of B from measured resistances at different temperatures the equation (1) is normally rewritten as B = In (R1/R2) / (I/T1-I/T2) (2) where T(K) is again the temperature and R1 and R2 (ohm) are the resistances atTi and T2, respectively. These materials with large, negative TCRs (NTC) are based on solid solutions of transition-metal oxides. Mostly, due to their long-term stability, the compounds are solid solutions of Mn304, C03O4 and NiO oxides with the spinel structure /11-13/. The general formula of the spinel structure is AB2O4. It is based on oxygen atoms arranged in an fee (face-centred-cubic) structure containing tetrahedral (A) and octahedral (B) lattice sites. The electrical charge transport is via the hopping of electrons between the B3+ and B4+ ions present at the octahedral sites in the lattice. This is shown schematically in Fig. 1 forthe NIO-doped Mn304. The spinel Mn3C>4 (Mn2+ 2Mn3+C>4) is non-conducting. When some of the manganese 3+ ions are substituted by the nickel 2+ ions the same number of manganese ions change their valence from 3+ to 4+ in order to preserve the overall electrical neutrality. Electron hopping between the Mn3+ and the Mn4+ can take place. The values of the resistivities and the beta factors of the NTC materials depend on the ratio of the oxides. The resistivities range from a few hundred ohm.cm to a few tens of kohm.cm, and the beta factors from 2500 K to 4000 K. These electrical characteristics are shown in the ternary phase diagram of Mn-Co-Ni-oxides forthe resistivities (Fig. 2.a) and the beta factors (Fig. 2.b) /13/. The compositions with minimum resistivities, and maximum and mini- Conductivity - electron "hopping" "A" sites "B" sites Mn2+ Mn3+Mn3+ 04 - non-conducting xNi2+ xMn4+(2-x)Mn3+ 04 - conducting Mn4+ + e- —-.......-> Mn3+ fig. 1. Conductivity mechanism in NiO-doped Mn3Ö4 spinel - schematic .... v Z Fig. 2. a: Ternary phase diagram of Mn-Co-Ni-oxides. The minimum resistivity is indicated by the arrow/13/ B max y,; 1 Fig. 2.b: Ternary phase diagram of Mn-Co-Ni-oxides. The maximum and minimum beta factors are indicated by the arrows/13/ mum beta factors are indicated by arrows. The solid solutions with the lowest resistivities (rich on manganese oxide) also have the lowest temperature coefficients of expansion, i.e. 8.2 x 10"6/K. A partial substitution of the iron ions (3+) on the B sites or the copper ions (1 +) on the A sites increases or decreases the resitivities, respectively /14-17/. The fired thickness of the thick-film layers is usually between ten and twenty micrometers. As mentioned before, the resistivities of the different spinel compositions are between a few hundred ohm.cm and a few tens of kohm.cm, and can be increased up to 1 Mohm.cm with the partial substitution of manganese ions with iron ions. These are useful values for pellet-type components. How- 115 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Informacije MIDEM 35(2005)3, str. 114-121 Thick-film Resistors with Low and High TCRS on LTCC Substrates ever, due to the dimensions of the thick-film resistors the values of the sheet resistivities (ohm/sq.) are between two and three orders of magnitude higher than the resistivities (ohm.cm) of the materials themselves. The glass phase, which is added for better sintering of the thick-film layers at relatively low firing temperatures (850°C), further increases the resistivity. Therefore, materials for thick-film NTC resistors usually Include some phase with a low specific resistance, generally RuC>2. RuC>2 has a relatively low specific resistivity, 40 x 10"6ohm.cm, and a positive, linear, metallic-like dependence of resistivity vs. temperature, with a TCR of 7000x10"6/K for single crystals and a few 1000x10"S/K for sintered microcrystalline samples /18,19/. The addition of ruthenium oxide decreases the specific resistance, reduces the noise and improves the stability of the resistors. However, due to the RuC>2 high, positive and linear metallic-like TCR /14,20/ it also decreases the beta factors. As most of the thick-film resistors were developed for firing on alumina substrates their compatibility with (rather glassy) LTCC substrates needs to be evaluated. The aim of this work is to compare the electrical and microstrutural characteristics of the low TCR "normal" thick-film resistor 2041 (10 kohm/sq., Du Pont) and the 4993 NTC thermistor (1 kohm/sq., EMCA Remex) fired on 96% alumina and co-fired on Du Pont LTCC 951 substrates. The 2041 resistor was chosen because of its high stability and low noise. The conductive phase is based on a mixture of Ru02 and Pb2Ru206.5 /21,22/. The nominal beta factor of NTC 4993 thermistors is 1200 K. As mentioned above, both thick-film materials were developed for alumina substrates. The X-ray spectra of the Du Pont LTCC 951 tapes, unfired and fired at 850°C, are shown in Fig. 3 /23/. The unfired material is a mixture of alumina and glass. After firing, peaks of anorthite ((Na.CaXAI.SiUOs) phase appear. The peaks of alumina and anorthite are denoted by "A" and asterisk, respectively. Experimental The 2041 resistors and NTC 4993 thermistors were screen printed and fired for 10 min at 850°C on 96% alumina and on green LTCC (951, Du Pont) substrates. The LTCC substrates were made by laminating three layers of LTCC tape at 70°C and at a pressure of 200 bar. The thick-film resistors were terminated by Pd/Ag electrodes that were pre-fired at 850°C on alumina substrates, and cofired together with the printed thermistors and LTCC substrates. The dimensions of the resistors for the microstructural analysis and the X-ray diffraction (XRD) analysis, which were printed and fired without conductor terminations, were 12.5x12.5 mm2. For the microstructural investigation the samples were mounted in epoxy in a cross-sectional orientation and then cut and polished using standard metallographic techniques. A JEOL JSM 5800 scanning electron microscope (SEM) equipped with an energy-dispersive X-ray analyser (EDS) was used for the overall microstructural and compositional analysis. Note that boron oxide, which is also present in the glass phase, cannot be detected in the EDS spectra because of the low relative boron weight fraction in the glass and the strong absorption of the boron Ka line during EDS analysis in the glass matrix. Dried thermistors (150°C) and thermistors fired at 850°C were analysed by X-ray diffraction (XRD) analysis with a Philips PW 1710 X-ray dif-fractometer using Cu Ka radiation. X-ray spectra were measured from 2 9=20° to 2 6=70° in steps of 0.02°. Cold (from -25°C to 25°C) and hot (from 25°C to 125°C) TCRs were calculated from resistivity measurements at - 25°C, 25°C, and 125°C. The current noise was measured in dB on 100-mW loaded resistors using the Quan Tech method (Quan Tech Model 315-C). Results and discussion LTCC Du Pont 951 120 1850 deg. C > 100 : A * 1 1 C 80 C 1 * * 60 ^AVAJVV 40 1 Green tape 20 0 ;------------------ Fig. 3: X-ray spectra of green and fired (850°C) Du Pont LTCC 951 tapes/16/. The peaks of alumina and anorthite are denoted "A" and asterisk, respectively 2041 resistors X-ray spectra of dried 2041 resistors and resistors fired at 850°C on alumina and LTCC substrates are shown in Fig. 4. The spectra of RuC>2 (denoted Ru02) and Pb2Ru206.5 (denoted RU) are added. As mentioned above the conductive phase of the 2041 resistor material is based on a mixture of ruthenium oxide and ruthenate. The spectra of 2041 resistors, fired on alumina and LTCC substrates, are nearly the same, which indicates the compatibility of the 2041 with LTCC. The microstructure ofthe surface of the 2041 resistor, fired at 850°C is shown in Fig. 5. Cross-sections of the 2041 fired at 850°C on alumina and LTCC substrates are shown in Figs. 6.a and 6.b, respectively. The substrate is on the right. The 2041 resistor is a multiphase mixture consisting of conductive phase (white grains), dark-grey grains (rich in Si and Zr, presumably SrZrCU), and a light-grey glass phase. 116 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Thick-film Resistors with Low and High TCRS on LTCC Substrates Informacije MIDEM 35(2005)3, str. 114-121 2041 I 850 C Fig. 4: X-ray spectra of dried 2041 resistors and resistors fired at 850°C on alumina and LTCC substrates. The added spectra of Ru02 and Pb2F!u206.5 are denoted Ru02 and RU, respectively. Ï«sï®i lä » / s ; Fig. 6,b: Cross-section of the 2041 resistor, fired at 850°C on LTCC. The LTCC substrate is on the right. The EDS micro-analyses over the whole cross-sections of the 2041 films (area 15x15 um2) on the alumina and LTCC substrates are presented in Table 1. The compositions are given for elements and for oxides in at. % and mol. %, respectively. The concentration of oxygen is calculated by difference and not measured directly. The concentrations of the elements are similar for the resistors fired on alumina and on LTCC substrates. This indicates that there was no significant (or observable) interaction between the glassy LTCC material and the 2041 resistor. Table 1: The EDS analyses of the concentration of elements (in atomic %) and oxides (in mol. %) in the 2041 films fired at 850°C on the alumina and LTCC substrates Fig. 5: The microstructure of the surface of the 2041 resistor, fired at 850°C Fig. 6.a: Cross-section of the 2041 resistor, fired at 850°C on alumina. The alumina substrate is on the right. Element AI203 LTCC Oxide A1203 LTCC (at. %) substrate substrate (mol. %) substrate substrate Mg / <1 MgO / <3 Al 4 3 A10,.5 11 8 Si 17 17 Si02 45 44 Ca 2 4 CaO 5 10 Zn 1 1 ZnO 3 3 Zr <1 <1 Zr02 <3 <3 Ru 6 6 Ru02 16 15 Ba 1 1 BaO 3 3 Pb 6 5 PbO 16 13 0 67 66 The electrical characteristics, i.e., sheet resistivities, cold (-25°C to 25°C) and hot (25°C to 125°C)TCRs and noise indices of the 2041 resistors fired on alumina and LTCC substrates are shown in Table. 2. Note that the noise indices are expressed in "dB" and "uV/V". These two units are "connected" with a simple equation, i.e,. noise (dB) = 20 x log noise (uV/V) The dependence of the relative sheet resistivities vs. temperature of the 2041 resistors fired at 850°C on alumina or LTCC substrates is shown in Fig. 7. 115 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Informacije MIDEM 35(2005)3, str. 114-121 Thick-film Resistors with Low and High TCRS on LTCC Substrates Table 2: Sheet resistivities, cold (-25°C to 25°C) and hot (25°C to 125°C) TCRs, and noise indices of the 2041 resistors on alumina and on LTCC substrates. Substrate R sheet (ohm/sq.) Cold TCR (x 10~6/K) Hot TCR (xl0"6/K) Noise (dB) Noise (uV/V) a2o3 850 2540 2580 -11 0,28 LTCC 180 3070 3075 -32 0,02 aiumina -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 T(deg. C) Fig. 7: Relative resistivity vs. temperature of the 2041 resistors fired at 850°C on alumina or LTCC substrates The electrical characteristics, summarised in the Table 2, tentatively confirm that there is no significant interaction between the 2041 resistor material and the glassy LTCC substrates. The resistivity vs. temperature curve of resistors fired on LTCC substrates is a little more "steep", but theTCR values are still well inside the required +/- 100x10"6/ K values. All the presented results, i.e., XRD and EDS analyses as well as electrical characteristics strongly indicate the (very useful) compatibility between the 2041 resistors and the LTCC substrates when resistors are cofired on the LTCC. Fig. 8: The X-ray diffraction spectra of the NTC 4993 thermistors fired at 850°C on alumina and on LTCC substrates. The spectrum of ruthenate, denoted "Ru02", is also included. Peaks of spinel phase are denoted "SP". NTC 4993 thermistors The X-ray diffraction spectra of the NTC 4993 thermistors dried at 150°C and fired at 850°C on alumina and cofired on LTCC substrates are shown in Fig. 8. The spectrum of ruthenium oxide, denoted "Ru02", is also included in the graph. It is interesting to note that peaks of spinel phase (denoted "SP") appear after firing, but are not present in the dried thick-film. This means that the active phase is formed during the firing and is not included as a prereact-ed compound. In the fired layers the X-ray analyses show mainly spinel and RuC>2, which is added to the thick-film NTC materials, as mentioned in the Introduction, to decrease the specific resistance and to improve the stability and the current noise. The presence of a few (unmarked) X-ray peaks, most notably the one at 2 6 = 38°, could be tentatively attributed to un-reacted oxides. The temperature of the formation of the spinel solid solution in the investigated thick-film NTC thermistors, as seen from the X-ray spectra, is relatively low. In the production of discrete components the required firing temperatures are from 1000°C to over 1200°C /11,14,24,25/. The lower temperature of the spinel synthesis in thick-film materials as compared to bulk ceramics is presumably due to the presence of the liquid glass phase which appears in thick-film resistors at temperatures around 700°C /26,27/. The microstructure of the surface of the NTC 4993 thermistors fired at 850°C is shown in Fig. 9. The microstructure is glassy and porous with pore dimensions up to 10 * P S 0 3É8É ê i* * ^ Fig. 9: The microstructure of the surface of the NTC 4993 thermistor, fired at 850°C 116 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Thick-film Resistors with Low and High TCRS on LTCC Substrates Informacije MIDEM 35(2005)3, str. 114-121 um. The lighter phase is a glass phase. Cross-sections of the NTC 4993 thermistors fired at 850°C on alumina and LTCC substrates are shown In Figs. 10.a and 10.b. respectively. In both cases the films are porous. The interaction layer on the interface between the NTC films and the substrates is observed for both substrates. The thin, light-coloured phase on the alumina side is lead-oxide rich and Indicates the diffusion of PbO into the alumina ceramics. The darker interface within the LTCC substrate near the Interface is rich in alumina which presumably diffused from the LTCC into the NTC film. Fig. 10.a: Cross-section of the 4993 NTC thermistor, fired at 850°C on alumina. The alumina substrate is on the right en for elements and for oxides in at. % and mol. %, respectively. The concentration of oxygen is calculated by difference and not measured directly. The elemental ratio between Mn-, Co- and Ni-oxides is roughly 5/2/1, which puts this composition in the region of solid solutions with the lowest specific resistances between 0.5 and 1 kohm.cm /13/. Note that a higher concentration of Si02 In the NTC films fired on LTCC substrates than the films on alumina substrates, indicates a significant diffusion of silica from the LTCC into the thick-film NTC thermistors during firing. Table 3: The EDS analyses of the concentration of elements (in atomic %) and oxides (in mol. %) in the NTC 4993 thermistors fired at 850°C on the alumina and LTCC substrates Element AI2O3 LTCC Oxide A1203 LTCC (at. %) substrate substrate (mol. %) substrate substrate Al 7 7 AIO1.5 17 15 Si 5 9 Si02 12 19 K <1 <1 KOo.5 <2 <2 Ca <1 <1 CaO <2 <2 Mn 10 11 MnOx 24 23 Co 4 4 CoOx 10 9 Ni 2 2 NiO 5 4 Cu 6 6 CuO 14 13 Ru 2 2 Ru02 5 4 Pb 4 4 PbO 10 9 0 57 55 The electrical characteristics, i.e., sheet resistivities, cold (-25°C to 25°C) and hot (25°C to 125°C) TCRs, beta factors and noise indices of the NTC 4994 thermistors fired on alumina and LTCC substrates are shown in Table. 4. Note that the noise indices are expressed in "dB" and "uV/ V". The noise indices are expressed In "dB" and "uV/V". NTC 4993 Fig. 10.b: Cross-section of the 4993 NTC thermistor, fired at 850°C on LTCC. The LTCC substrate is on the right The overall analyses of the NTC layers (area 15x15 um2) showed the presence of mainly Al, SI, Mn, Co, Ni, Cu, Ru and Pb. As mentioned in the Introduction, copper oxide and ruthenium oxide are added to lower the specific resistance of Mn-Co-Ni solid solutions. The results of the analysis are present In Table 3. The compositions are giv- ltcc -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 T(deg. C) Fig. 11: Logarithm of sheet resistivities vs. temperature of NTC 4994 thermistors fired at 850°C on alumina or LTCC substrates. 115 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Informacije MIDEM 35(2005)3, str. 114-121 Thick-film Resistors with Low and High TCRS on LTCC Substrates Table 4: Sheet resistivities, cold (-25°C to 25°C) and hot (25°C to 125°C) TCRs, beta factors and noise indices of the 2041 resistors on alumina and on LTCC substrates. Substrate R sheet Cold TCR Hot TCR B Noise Noise (ohm/sq.) (xlO"s/K) (X10"6/K) (K) (dB) (uV/V) A1203 550 -22700 -6510 1240 -12.2 0.25 LTCC 2250 -41500 -7550 1660 7.4 2.34 These two units are "connected" with a simple equation -see the comments relating to Table 2. The dependence of the relative sheet resistivities vs. temperature of the 2041 resistors fired at 850°C on alumina or LTCC substrates is shown in Fig. 11. The sheet resistivities of the NTC 4993 thick-film thermistors (nominal sheet resistivity 1 kohm/sq,) are, at room temperature, around 500 ohm/sq. on alumina, while on the LTCC substrates they are four times higher. Similarly, the cold and hot TCRs and the beta factors of the thermistors fired on LTCC are higher than the values fired on alumina. These results could be attributed to the diffusion of the glassy phase, mainly Si02, from the LTCC substrates into the NTC films during firing. The additional glass presumably "breaks up" some of the conductive paths through the resistor film, thereby increasing the sheet resistivities as well as the noise indices. However, if the higher current noise of the NTC 4993 thermistors fired on LTCC substrates is acceptable the investigated thick-film NTC materials could be used on LTCC substrates. Conclusions Low-Temperature Co-fired Ceramic (LTCC) materials, which are sintered at the low temperatures typically used for thick-film processing, i.e. around 850°C, are convenient and widespread technique for MCM-C (Ceramic multi-chip modules). LTCC materials are based either on crystalliza-ble glass or a mixture of glass and ceramics. As most of the thick-film resistors were developed for firing on alumina substrates their compatibility with (rather glassy) LTCC substrates needed to be evaluated. The "normal", i e., low TCR thick-film resistor 2041 (10 kohm/sq., Du Pont) and the 4993 NTC thermistor (1 kohm/sq., EMCA Remex) were fired on 96% alumina and co-fired on green Du Pont LTCC 951 tapes. The electrical and microstructural characteristics were compared. The X-ray spectra of the 2041 resistors fired on alumina and LTCC substrates are nearly the same, which indicates the compatibility of the 2041 with LTCC. Also, the electrical characteristics of 2041 resistors fired on both substrates are similar indicating that the resistors are compatible with the LTCC material. The EDS analyses did not show any significant interaction between the 2041 resistors and the LTCC substrates. For the NTC 4993 thermistors the XRD analysis showed that the spinel active phase is formed during the firing and is not included as a pre-reacted compound. There were no significant differences in the X-ray spectra between thermistor films fired on alumina or on LTCC substrates. The electrical characteristics, i.e., the sheet resistivities, beta factors and noise indices of the thermistors fired on LTCC substrates as compared to films fired on alumina significantly increased, indicating the interaction between the thermistor layers and the LTCC substrates. The changes in the electrical parameters were attributed to the diffusion of a silica-rich phase from the LTCC substrates into the thermistor films. Acknowledgements The authors wish to thank Mr. Mitja Jerlah (HIPOT-HYB) for printing and firing the samples as well as for measuring the electrical characteristics. The financial support of the Slovenian Research Agency is gratefully acknowledged. References /1./ A. A. Shapiro, D. F. Eiweil, P. Imamura, M. L. MeCartney, Structure-property relationships in low-temperature cofired ceramic, Proc. 1994 Int. Symp. on Microelectronics ISHM-94, Boston, 1994, 306-311 /2. / J.-H. Jean, C.-R. Chang, Camber development during oofiring Ag-based low-dielectric-constant ceramic package, J. Mater. Res., 12, (10), (1997), 2743-27 50 /3. / R. E. Doty, J. J. Vajo, A study of field-assisted silver migration in low temperature cofirable ceramic, Proc. 1995 Int. Symp. on Microelectronics ISHM-95, Los Angeles, 1995, 468-474 /4. / R. E. Doty, J.J. Vajo, A study of field-assisted silver migration in low temperature cofirable ceramic, Proc. 1995 Int. Symp. on Microelectronics ISHM-95, Los Angeles, 1995, 468-474 /5. /C.-J. Ting, C.-S. Hsi, H.-J. Lu, Interactions between ruthenium-based resistors and cordierite-glass substrates in low temperature co-fired ceramics, J. Am. Ceram. Soc., 83, (12), (2000), 23945-2953 /6. / W. K. Jones, Y. Liu, B. Larsen, P. Wang, M. Zampino, Chemical, structural and mechanical properties of the LTCC tapes, Proc. 2000 Int. Symp. on Microelectronics IMAPS-2000, Boston, 2002, 669-674 /7. / M. A. Rodrigues, P. Yang, P. Kotula, D. Dimos, Microstructure and phase development of buried resistors in low temperature co-fired ceramics, J. Electrooeramics, 5, (3), (2000), 217-223 /8. / A. Dziedzic, L. J. Golonka, J. Kita, H. Thust, K-H. Drue, R. Bauer, L, Rebenklau, K-J. Wolter, Electrical and stability properties and ultrasonic microscope characterization of low temperature 116 M. Hrovat, D. Belavič, J. Kita, J. Hole, J. Cilenšek, L. Golonka, A. Dziedzic: Thick-film Resistors with Low and High TCRS on LTCC Substrates Informacije MIDEM 35(2005)3, str. 114-121 co-fired ceramics resistors, Microelectronics Reliability, 41, (2001), 669-676 /9. / P. Yang, M. A. Rodrigues, P. Kotula, B. K. Miera, D. Dimos, Processing, microstructure, and electric properties of buried resistors in low-temperature co-fired ceramics, J. Appl. Phys., 89, (7), (2001), 4175-4182 /10. / C-S. His, D-F. Chen, F-M. Shieh, S-L. Fu, Processing of LTCC with embedded RuOi-based resistors, Mater. Chem. Phys., 78, (2002), 67-72 /11. / J. L. Martin deVidales, P. Garcia-Chain, R. M. Rojas, E-Vila, O. Garcia-Martinez, Preparation and characterisation of spinel-type Mn-Ni-Co-0 negative temperature coefficient ceramic thermistors, J. Mater. Sci., 33, (6), (1998), 1491-1496 /12. /J. Huang, Y. Hao, H. Lin, D. Zhang, J. Song, D. Zhou, Preparation and characteristics of the thermistor materials in the thick-film integrated temperature-humidity sensor, Mater. Sci. Eng., B99. (1-3), (2003), 523-526 /13. / M. Prudenziati (Ed.), Thick Film Sensors, Elsevier, Amsterdam, 1994, 127-150 /14. / M. L. Martinez Sarrion, M. Morales, Preparation and characterization of NTC thermistors based on Fe2*yMni-x-yNix04, J. Mater. Sci., 30, (10), (1995), 2610-2613 /15. / K. Park, D.J. Bang, Electrical properties of Ni-Mn-Co-(Fe) oxide thick-film NTC thermistors prepared by screen printing, J. Mater. Sci.: Materials in Electronics, 14, (2003), 81-87 /16. / D. Metz, P. Caffin, R. Legros, A. Rousset, The preparation, characterization and electrical properties of copper manganite spinels, CuxMn3-x04, 02 in (Mn,.2Nio.78Coo.87-xCuo.i5Six)04 negative temperature coefficient thermistors, Scripta Materialia, 50, (2004), 551-554 /26. / M. Hrovat, F. Jan, An investigation of thick film resistor materials properties during firing process, Hybrid circuits, 14, (1987), 25-29 /27. / M. Hrovat. A. Benčan, D. Belavič, J. Hole, G. Dražič, The influence of firing temperatures on the electrical and microstructural characteristics of thick film resistors for strain gauge applications, Sensors and Actuators. A103. (2003), 341.352 Marko Hrovat, Janez Hole, Jena Cilenšek Jožef Stefan Institute, Jamova 39, SI-1000 Ljubljana, Slovenia Phone: +386 1 477 3900, e-mail: marko.hrovat@ijs.si Darko Belavič, HIPOT-R&D, d.o.o., Trubarjeva 7, SI-8310 Šentjernej, Slovenia Jaroslaw Kita, Leszek Golonka, Andrzej Dziedzic Wroclaw University of Technology, Wybrzeze Wyspianskiego 27, 50-370 Wroclaw, Poland Prispelo (Arrived); 03.06.2005 Sprejeto (Accepted): 30.09.2005 121 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)4, Ljubljana REVIEW OF VARIOUS REALIZATIONS OF INTEGRATED MONOLITHIC TRANSFORMERS Goran Stojanovič, Andrea Maric, Ljiljana Živanov Faculty of Technical Sciences, Novi Sad, Serbia and Montenegro Key words: integrated transformer, coupling coefficient, planar structure, stacked structure. Abstract: The integrated transformer is an essential component In many RF Integrated circuits. Planar and stacked transformers on a silicon substrate are widely used in low-noise amplifiers, active mixers, voltage control oscillators, filters, etc. This paper gives an overview of different configurations of Integrated transformers, their layouts and fundamental electrical characteristics. This review, also, compares the advantages and disadvantages of various integrated monolithic transformer realizations regarding the occupied area on chip, the coupling coefficient, the inductances values and the parasitic effects. Some possibility for improvement of transformer performances, such as using patterned ground shield or design structures with variable width of turns in the primary and secondary winding are proposed, too. Pregled različnih izvedb integriranih monolitnih transformatorjev Kjučne besede: integrirani transformatorji, koeficient sklopltve, planarna struktura, nakopičena struktura Izvleček: Integrirani transformatorje bistven element v mnogih RF integriranih vezjih. Planarni In nakopičeni transformatorji na silicijevi rezini se uporabljajo pri izvedbi malošumnih ojačevalnikov, aktivnih mešalnih vezjih, napetostno krmiljenih oscilatorjih, filtrih in podobno. V prispevku podajamo pregled različnih možnih konfirguracij Integriranih transformatorjev, njihov razpored na površini In osnovne električne značilnosti. Primerjamo tudi prednosti in slabosti različnih izvedb tovrstnih transformatorjev glede površine, ki je zasedajo na čipu, koeficienta sklopltve, vrednosti induktance in parazitnih efektov. Predlagamo tudi nekatere Izboljšave transformatorskih lastnosti, z uporabo ozemljenega oklopa ali načrtovanjem strukture s spremenljivo širino linij v primarnem in sekundarnem navltju. I. Introduction Constant growth of wireless applications brought to an intensive need for mobile communications and mobile communication devices. According to some research data /1/, the annual worldwide sales of cellular phones have exceeded the figure of $2.5B and in Europe only the profit from equipment and service for mobile communications has overcome $30B. Due to growing need for wireless communication devices radio frequency and wireless market is continuing'its development. As well known, there are three main generations of mobile systems, as shown In Fig. 1 /2, 3/. Japan USA Europe Europe USA Japan Fig. 1. Mobile communication generations /2/. Nowadays, the second generation of mobile systems is widely established, using GSM (Global System for Mobile Communications) as a most successful digital wireless service. But different standards that are in use worldwide are quite inadequate for successful Interconnecting. So, it was suggested that the third generation of mobile systems should give a worldwide high-performance standard UMTS. UMTS is to provide data rates up to 144Kblts/s, 384 Kbits/ s and 2 Mbits/s in macrocellular, microcellularand indoor environments respectively. This would unlock services such as real-time video, mobile entertainment, etc /4/. But, there are many difficulties present that apply to Implementation of this technology. Mobile communication is mainly concentrated on long distance range applications. For short-range distance between the emitter and the receiver, such as In wireless U\N (WL7\N), different standards have been Introduced. In industry, for WU\N are used standards sanctioned by WECA (the Wireless Ethernet Compatibility Alliance) based on standard created by the 802.11 committee of the IEEE. According to this standard spectrum around 2.4GHz (for Wi-Fi or IEEE802.11 a) and 5GHz (for HlperU\N or IEEE802.11 a) are used with transmission speeds of 11 Mbps. Another standard for short-range communications ( 10-100m) Is Bluetooth. It uses 2.4GHz ISM band and has transmission speed of 780kbs/s. These standards intend to take primate in mobile communications for low band applications. 122 G. Stojanovič, A. Maric, L. Živanov: Review of Various Realizations of Integrated Monolithic Transformers Informacije MIDEM 35(2005)3, str. 122-132 Silicon based RF (radio frequency) integrated circuits are becoming more and more competitive in wide band frequency range. An essential component of these IC (Integrated circuits) is integrated (or on-chip) transformer. They are widely used In mobile communications, microwave integrated circuits, low noise amplifiers (LNA) /5, 6/, active mixers /7,8/, baluns (give balanced output for unbalanced input) /9, 10/. They are required in impedance matching, signal coupling, and phase splitting applications. Transformers are proved effective for miniaturized sensors, actuators, filters and power converters that should be integrated on chip modules and installed In various electronic systems /11-17/. In Fig. 2 are shown some of the most common applications of the monolithic transformer in LNA and active mixer /8/. I b) Fig. 2. Integrated transformer in a) LNA application b) active mixer. In LNA circuit transformer provides an inductive feedback path aiming to improve the linearity and the stability of the circuit. Fig. 2b shows a useful example, where transformer having current gain is placed in the current path of an active mixer. Although significant efforts have been made in order to Improve the characteristics of on-chip transformers, it is still a great problem to bring in piece the opposite demands for low cost, low supply voltage, low power dissipation and low distortion, but high frequency of operation in RF implementation of these transformers /15/. Commonly used transformers are fabricated on lossy silicon substrate hence they are from the start limited to a lower quality factor, coupling coefficient and high parasitic effects between the component and the substrate. However, low cost of SI IC fabrication over GaAs or quartz IC fabrication still dictates the usage of silicon substrates. Arbitrary transformer layouts also impact the transformer characteristics. These layouts include parallel windings, interleaved windings, overlay windings and concentric spiral windings and they result in planar or stacked configurations. Planar transformers generally have lower self-Inductance, parasitic capacitances and coupling factor, but higher resonant frequency compare to stacked which engage less chip area and has higher Inductance values and lower quality factor. Width of the windings, spacing between coils and material used for their fabrication also has influence on overlay characteristics of the transformer. In order to give the general insight in transformer configurations various constructions will be presented in this paper. We will closely clarify the influence of substrate conductivity, mutual coupling, symmetry and process parameters on transformer behaviour. We also propose some techniques for improvement of integrated transformer performances. II. Fundamental Characteristics of Integrated Transformers As well known, monolithic transformer is one of the indispensable elements of many RF ICs. Fig. 3 represents a typical configuration of monolithic planar transformer, its electrical equivalent symbol and layout in the chip /12/. Transformer Is characterized by the inductance {Lp, Ls) and the voltage (Vp, Vs) of the primary and the secondary winding and its operation is based upon the mutual inductance of the windings. According to the Lenz law variations of the magnetic flux produced by the current flow in the primary winding ip induce a current/s in the secondary winding that flows out the terminal Š. They also provide a positive voltage Vs between the secondary terminals. It Is important to emphasize that DC signals are blocked by the transformer therefore linking windings at different voltages is possible. There are two ways of connecting the primary and the secondary terminals - in non-inverting or inverting manner. The phase of Vs depends on the choice of the reference terminal. In non-inverting connection an AC signal source and the ground are on primary terminals P and P, giving a minimal phase shift of the signal at the S output while S is grounded. An inverting connection differs in as much that terminal S is now grounded and at the S output 123 G. Stojanovic, A. Marie, L. Zivanov: Informacije MIDEM 35(2005)3, str. 122-132 Review of Various Realizations of Integrated Monolithic Transformers Clout mmmmmm§mmmiim p I mMm^mMMm dout IP P Vp P _ 1: n _ / to Lp J '^Ls ) ( \ > L c- .-J b) Due to its common use, it is crucial that insertion losses of the transformer are brought to a minimum. These losses are invoked with finite metal resistance, finite inductances of coils, substrate dissipation and magnetic coupling factor. The metal ohmic losses can be reduced by using high conductive materials for windings or by increasing its thickness. Substrate losses are minimized by utilizing substrate materials with high resistivity or placing isolation layers (made usually by silicon-dioxide) between the substrate and the transformer coils. There are three main electrical parameters that describe every monolithic transformer - the transformer turns ratio n, /(-factor and Q-factor. The transformer turns ratio is related with the current and voltage transformation between the windings as shown (in accordance with symbol 1: n in Fig. 3b) n = K v.. (D Lp and Ls represent the inductance of primary and secondary winding of the transformer. Generally, value of the ratio n is around 1 for symmetrical structures, but in the case of step-up or step-down transformer topology it can be greater or less than 1, respectively. The strength of the magnetic coupling between the primary and the secondary is represented by the /(-factor, which is closely related with the mutual inductance as well as with the self-inductance of the windings c) Fig. 3. Monolithic planar transformer a) physical layout b) schematic symbol c) the view on the chip. produced signal is in antiphase to the signal applied to the primary. Phase shifting is just one of the by-products that take place when using this two constructions /18, 19/. k = M J Lp ■ Ls (2) In the expression (2) M stands for mutual inductance of the primary and the secondary coil. The value of /(-factor primarily depends upon the width and spacing of the metal traces and the substrate thickness. By increasing the number of turns in transformer and decreasing the space between the windings higher values fork-factor can be achieved. For the ideal transformer /(-factor is 1, but for the most fabricated constructions k is in range 0.75 to 0.9 /18/. Quality factor, Q-factor, is more technology than geometry dependent factor and it can be calculated by the following equation Q = - Im(7n) Re(Fn)' (3) Yn represents input admittance of the transformer. Q-factor is dimensionless and it is proportional to the ratio of the resultant magnetic energy stored in the transformer to the energy dissipated per unit time cycle /20/. Reaching high values for Q-factor represents a problem. Great efforts have been made in order to improve this parameter, but the results are not still satisfying. 124 G. Stojanovič, A. Maric, L. Živanov: Review of Various Realizations of Integrated Monolithic Transformers Informacije MIDEM 35(2005)3, str. 122-132 III. Various Realizations of Integrated Transformers Prior to integrated transformers on-chip inductors on silicon substrate have been fully analyzed. Many researches have been performed in order to explain, define and illustrate design, modeling and optimization of integrated inductors. But in spite of the many similarities between inductors and transformers significant difference caused by magnetically induced losses are present between their equivalent models. Therefore, only some of the experiences that are used for improvement of inductors can be implemented fortransformers, so there are still many unknown rules that are present in the field of monolithic transformer theory. As inductors, on-chip transformers are usually fabricated by deposition of conductive metal layers on silicon substrate. These metal coils are mainly square and can be placed in planar or stacked configuration. The planar configuration engages larger area on chip in order to achieve higher inductances and Q-factor and to minimize the substrate losses. On the other hand, vertically stacked constructions require less chip area for same values of inductance and have high mutual inductance, but a lower Q-factor. Which of these layout structures are to use Is strongly dependent on the application in which transformer is needed. A. Tapped (nested) Transformer Tapped transformer is illustrated in Fig. 4. This is planar transformer and its secondary winding is placed around the primary. Thus, the common periphery between two windings is limited to just a single turn. Due to such configuration, mutual coupling between adjacent conductors mainly contributes to the self-inductance of each winding and not to mutual inductance between the windings. This implies a lower /(-factor (not higher than 0.6). Both windings can be implemented on the top metal layer and therefore the parasitic capacitance between substrate and windings Is minimized. Another disadvantage of this layout is non-symmetrical structure. Tapped transformer can be useful in high-performance broadband amplifiers and other three terminal applications. dont do ut I nte rt, eta I dielectric Metaitrace; V1/ \ y ji Silicon dioxicte Silicon substrate Backside metallization Fig, 4, Tapped transformer. d out •Á f- ! ¡1 f IP ■■I Ui s,< IIIsl- P S din M ~ : m lisas! III —■■Ii KSOl _ dout B. BifilarTransformer Bifilar transformer is illustrated in Fig. 5. This is also planar transformer and it is constructed from two parallel conductors that are interleaved. Therefore, mutual coupling between windings have higher influence on mutual inductance. As a result /(-factor has higher values than in tapped configuration. Self-inductance values of the primary and secondary windings are not equal, because of the non-equal length of the metal. In this structure windings are also placed on the top metal layer. This implies an asymmetrical structure, which can be corrected in the manner shown in the interleaved structure. Inter-metal dielectric w Metal trace: \ n m i ^_3 S i'i'i'i'i'ii IThTMI y';;,'! K'iTi'a Silicon dioxide Silicon substrate Backside metallization Fig. 5. Bifilar transformer. 125 G. Stojanovic, A. Marie, L. Zivanov: Informacije MIDEM 35(2005)3, str. 122-132 Review of Various Realizations of Integrated Monolithic Transformers C. Interleaved Transformer This is the most commonly used layout and with it full symmetry of the transformer is achieved. As shown in the Fig. 6 primary and secondary winding are identical and therefore they have almost identical self-inductance value. This configuration gives /(-factor approximately around 0.7 /21 /. Again, placing the primary and the secondary winding on the top layer can minimize the parasitic capacitance between windings and the substrate. Another advantage of this design is that the transformer terminals are an opposite sides of the physical layout, which facilitates connections to other circuitry. It is frequently used in four terminal applications. :i -, >A sl^r.-___tzJ ■) wMmsaiMmm mÊSSm 'i • X clout V H ! 'i .« ; i din s r V lili i ■Sil i i ml PHHHHHHI Inter-rnetal dielectric wMm_ cioii w ■/letal.traceE I B r-1 im r-; n ^_"r-1 S r-¡ r-i ect Silicon dioxide £-1 Neon substrate Backside metallization Fig. 6. Interleaved transformer. To gain higher step-up ratio, transformer shown in Fig. 7 is commonly used. As depicted 1:5 turns ratio is designed with one secondary winding and five individual turns for the primary (connected in parallel). This configuration leads to drastic failure of the primary inductance value and slightly decreases the k-factor by increasing step-up ratio /18/. Therefore, the input impedance must be low in order to efficiently couple a signal into the primary of the transformer. The step-up transformer is an ideal feedback element for RF amplifiers. D. Stacked Transformer Stacked transformer, or vertical-coupling structure /22/, represents a multiple conductor layer structure, as shown in Fig. 8a and Fig. 8b. This configuration has the advan- Inter-metal dielectric Mefa| ^ w \ s / "Wo. r~i ¡ai r~i taa r~i ra„ „_nI fin tn.n..o n. i Backside metallization Fig. 7. The step up, 1 ;5 interleaved transformer. tage of area efficiency and higher mutual coupling between the windings due to placing the primary coil on top of the secondary. Typical thickness of the dielectric between the layers is 1jj.m. Stacked transformers mainly have high k-factor, up to 0.9, and high mutual inductance, but low self-resonance frequency and therefore relatively small bandwidth /23/. For its fabrication three metal layers are needed, compared to tapped, bifilar and interleaved structure, which require two metal levels. This is not a symmetrical structure. The primary and the secondary winding are placed in adjacent metal layers causing different distances from the substrate. Also, their thickness often differ implying asymmetry in the electrical response of the transformer and unequal resistance of the windings. The lower winding shields the upper one from the influence of the conductive substrate causing difference in the parasitic capacitance to the substrate. In order to improve its characteristics the windings are placed in slightly offset position (horizontally or diagonally shifted), resulting in higher Q-factorand resonant frequency, Fig. 8c. Also, better characteristics of this transformer can be gained by placing the primary winding on lower metal layer. In this manner the substrate losses are slightly increased, but the parasitic capacitance between the windings becomes significantly decreased, thus the self-resonant frequency Increases /8/. Non-symmetrical configuration of the stacked transformer can be a limiting factor of its usefulness, but current trends in silicon technology are focused on improving its characteristics and performances. 126 G. Stojanovič, A. Maric, L. Živanov: Review of Various Realizations of Integrated Monolithic Transformers Informacije MIDEM 35(2005)3, str. 122-132 dout U h" dout dout dout I riter-rnetal dielectric ^ etal traces w V\ s j*--' ' silicon , dioxide Backside metallization b) I rite r-rnetal dielectric M Sgj i. H.......................... V >■ „OOP.........n, o o. Metal traces .X Silicon substrate silicon dioxide Fig. 8. Backside metallization C) Stacked transformer a) layout b) non-offset position c) offset position of the windings. Another structure of the stacked transformer can also be used. Fig. 9 /8/ depicts transformer with 1-to-2 step-up ratio. This configuration uses three different metal layers for placing the windings. As shown in Fig. 9 secondary windings are interconnected by via and slightly offset compared to the primary winding placed in between. The number of spirals used for each winding impacts the voltage (or current) gain at a desired frequency. The concept of stacked transformer can be applied, also, to more metal layers to achieve higher voltage gain. E. Stacked Interleaved Transformer Fig. 10 represents another realization of monolithic transformer/24, 25/. This is a symmetrical structure and it occupies small area on chip. It consists of two interleaved transformers that are stacked on top of one another. In this structure both the primary and the secondary winding are / / if" 7 / Secondary Primary lnter-metaMielectric^Meta|traces res Oy^_resl ^ / , ■ ilicon VS m / np.dup),.......o.ra.cg, illllllllBilll dioxide Backside metallization Fig. 9.1: 2 stacked transformer structure. dout contact tu bottom laver primar/ "TT"^-»® top primary '--top :econdary contact to bottom layer :econdary t— dout bottom primary' I S — M g I contact to { ; I - —- ^ top layer primary f' _b otto rri secondary A contact to top layer H i secondary dB f, ^ top layer I I I I ri te r-rnetal dielectric W, Metal traces ¡lililHliiliHI Silicon dioxide Backside metallization Fig. 10. Stacked interleaved transformer. 127 G. Stojanovic, A. Marie, L. Zivanov: Informacije MIDEM 35(2005)3, str. 122-132 Review of Various Realizations of Integrated Monolithic Transformers present in both metal layers achieving in this manner a full symmetry of the layout. This also implicates reduction of the parasitic capacitance between primary and secondary windings. Matching ends of windings in top and bottom layer are interconnected by vias (A and B in Fig. 10). Stacked interleaved transformer has higher value of the self-inductance of the windings, but lower mutual inductance than the stacked configuration. However, the values of total inductance forthese two configurations are approximately the same. This transformer is used in narrowband applications that require symmetry. square segments, yet their parts are connected by vias through one of the lower metal layers at points on vertical symmetry axis. In this configuration, as in center-tapped, primary and the secondary terminals are on opposite outside edges of the transformer and as result connection of the transformer to other electrical components is easy. , 250 urn , F. Central-taped Transformer Transformer shown in Fig. 11 represents also a mixture of interleaved (Fig. 6) and stacked (Fig. 8) configuration. Depicted transformer has a square structure, consisting of two groups of interleaved coils that are divided along a horizontal symmetry line, forming turns ratio of 4:5. One of the advantages of such construction is alleviation in connecting transformer to other circuitry, due to placing both terminals to the outside edge of the transformer. This construction shows good mutual couplings, which is favored by interwounding of the inductors. Center-taped transformer is utilized in power dividers/combiners and baluns. dout m & □ out iter-metal dielectric . . . ,, u e Metal traces \\ * W \\ hd rn g g o v \ n, mm „fa.riCTn, Silicon substrate .üiiicon „-ilicixi de Backside metallization Fig. 11. Central-taped transformer. Similar transformer configuration is depicted in Fig. 12 /26/. The primary and the secondary winding are laid on the same upper metal layer. Windings don't form whole secondary ¡#11 is p n maty & ■ m i« Fig. 12. Integrated transformer with Lp=5.5nH, Ls"7nH, k=0.83 and Qp= Qs =70 at 1.7GHz/26/. The primary and the secondary winding can have other shapes not only square, like octagonal or circular. A special planar winding scheme for circular monolithic transformers which results in a very high coupling coeficient k is depicted in Fig. 13 /27, 28/. For realization other values than 1:1 of the turn ratio, different numbers of primary and secondary turns must be used. This implements that some adjacent conductors belong to the same winding which results in a lower /(-factor. A solution for this problem is to use an interlaced winding-scheme /28/. The monolithic transformer shown in Fig. 13 consists of six primary turns P1-P6 and two secondary turns. The centertaps PCT and SCT are available. Fig. 13 shows a three-dimensional top view of the transformer. The outer diameter is about 200 ¡j.m and the inner diameter is about 50 p,m. Fig. 13. 3-D-view of the planar high coupling performance transformer /28/. 128 G. Stojanovič, A. Maric, L. Živanov: Review of Various Realizations of Integrated Monolithic Transformers Informacije MIDEM 35(2005)3, str. 122-132 a) b) c) d) HI H 1 ■■ji < Fig. 14. The various patterned ground shields constructions a) solid ground b) coarse ground c) patterned ground d) bar ground /29/. IV. Some Techniques for Improvement of Transformer Characteristics One of additional techniques for improvement of transformer characteristics is implementing patterned ground shields - PGS /29/. PGS is placed between the silicon substrate and the transformer windings, onto the silicon or slightly above it. It is commonly made of aluminum or polysilicon. The main reason for introducing PGS is to limit flow of magnetically induced eddy currents in the silicon substrate. Some designs of PGS are depicted in Fig. 14. Solid PGS (Fig. 14a) gives good results in preventing losses invoked by the electrical field. But losses caused by the magnetic field and induced eddy currents in PGS are substantial. Therefore the shield must be patterned. In Fig. 14c, 14d are depicted two ways of patterning the shield. In Fig. 14c PGS has metal strips with a 40|_im width and 10|im spacing, while in Fig. 14d width of the strips is the same but the spacing between them is 60|im. As shown in /29/ transformer using PGS with larger spacing has lower values of inductance and Q-factor, but has higher resonant frequency and larger bandwidth than the other configuration. Introduction of these PGS leads to lower values of inductance and Q-factor and voltage gain on lower frequencies, but give better k- and Q-factor on frequencies higher than 4GHz compared to transformers without PGS. On frequencies higher than 14GHz shields lose their purpose leaving the transformer with the same characteristics as without PGS. In order to decrease substrate losses it is advisable to use surrounding metal tracks for ground pads in the vicinity of on-chip components, Fig. 15. This ground ring enables dissipation of the magnetic flux in the conductive silicon substrate. According to the previous experience with inductors position of the ground ring implicates variations of the self-resonance frequency of the transformer and usage of substrate area is increased. As the ground pads are moved farther from the transformer resonance frequency increases, till It doesn't reach a saturation value. Bulk and surface micromachining are techniques compatible with standard IC industry of inductors and transformers. By means of these techniques, electrical coupling losses can be reduced. They employ substrate removal underneath planar components (inductor, transformer...). In this way substrate losses and electrical coupling are eliminated from the component, resulting in substantial increase of self-resonant frequency and quality factor /30/-/33/. However, when the silicon substrate is removed, magnetically induced losses (eddy currents) become much more relevant. They are directly dependent on the time varying magnetic flux through the coils. They represent frequency dependant losses and they increase while the coil width increases, so they must be taken into account /31 /. The recently new solutions have been developed based on layout optimization and finding the optimum value between the magnetically induced and ohmic losses in metal 129 G. Stojanovic, A. Marie, L. Zivanov: Informacije MIDEM 35(2005)3, str. 122-132 Review of Various Realizations of Integrated Monolithic Transformers b) Fig. 15. interleaved transformer with a) the ground ring, and b) the ground ring and the PGS. colls. The first step of this optimization Is analyzing the series resistance of the transformer's coils. It is widely known that ohmic losses of this resistance decrease while the width of the metal strips increases, but the magnetically induced losses enhance. So, there must be an optimum strip width, which minimize series resistance and maximize Q-factor. Layout optimization techniques can be used not to find the optimum width of the coil, but to embrace the width and/or the pitch (the thickness) of every turn as the variable part of the design. For Inner turns narrow strips are used to optimize magnetic field losses, which are at the highest value in the center of the primary or secondary Front size z Handle substrate Settled epuxy \ \ _ K \Quartz Handle substrate 4 Front size a) b) Fig. 17. Substrate transfer technique /29/. 130 G. Stojanovič, A. Maric, L. Živanov: Review of Various Realizations of Integrated Monolithic Transformers Informacije MIDEM 35(2005)3, str. 122-132 coil of integrated transformers. The wide strips optimize the outer turns, where ohmic losses are predominant. In this manner much better results can be obtained (higher Q-factor and resonant frequency) /30/. Planar transformers with variable conductor width of the primary and the secondary winding can be realized in two configurations as it can be seen from Fig. 16. The form shown in Fig. 16a is more used, where the spacing between adjacent turns is constant (s=const.). The configuration depicted in Fig. 16b has property that the total distance between neighboring segments is constant (w+s=const.) Another advanced technique can be used to improve characteristics of the monolithic transformer at high frequencies /29/. By employing a substrate transfer technique lossy silicon substrate is replaced with lossless quartz substrate. First step in this process is to mount the transformer die onto a peace of insulating quartz by dissolvable epoxy glue (Fig. 17a). Then silicon substrate is removed by mechanical polishing with diamond sand paper until 30|j.m of silicon is left. This remain of silicon is removed by reactive plasma etching at room temperature. Following step is to use epoxy to attach another piece of quartz onto the etched surface of the die (Fig. 17b). By dissolving the epoxy glue in acetone substrate transfer technique is finished (Fig. 17c). Transformer on the quartz substrate has improved Q-factor and voltage gain at higher resonant frequency. However, the influence of the substrate on the k-factor and inductance is negligible. The usage of this technique is not yet so popular due to more complicated fabrication. V. Conclusion Integrated monolithic transformer performances greatly depend on geometrical and process parameters. Opposite demands are often expected and therefore a good balance should be found among self-inductance value, mutual coupling, parasitic capacitances, resonant frequency and naturally the cost of fabricated component. In this paper we have presented various transformer configurations and gave their fundamental characteristics. As we have said, planar structures occupy plenty space on chip, but they have high resonant frequency and therefore can be used in band-wide applications. Tapped transformer has also a low/c-factor and fairly low self-inductance. Interleaved and bifilar configurations have pretty high values for coupling coefficient, but low self-inductance. On the other hand, stacked structures engage less chip area and are used in narrow-band circuits as a terminal device due to their low self-resonant frequency. Hence, this work compares the advantages and disadvantages of various monolithic integrated transformer realizations and, also, gives some possibility for improvement of integrated transformer performances. Acknowledgement This work was supported in part by the Ministry of Sciences and Environment Protection of Republic of Serbia under the Project TR-006116B. References /1/ B. A. Georgescu, "Spiral inductor, Q-enhancement techniques," Ph. D. thesis, Department of Electrical and Computer Engineering, the University of Calgary, Apr. 2003. /2/ J. C. Costa, "Analysis of integrated transformers and its application to RFIC design," Ph. D. thesis, Department d'Eleotronica, Universität de Barcelona, Oct. 2002. /3/ E. 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Corresponding author: PhD Goran Stojanovic, IEEE Member Faculty of Technical Sciences Trg Dositeja Obradovica 6, 21000 Novi Sad Serbia and Montenegro e-mail: sgoran@uns.ns.ac.yu Goran Stojanovic, Andrea Marie and Ljiljana Zivanov are with the Department of Electronics Faculty of Technical Sciences University of Novi Sad, Trg Dositeja Obradovica 6, 21000 Novi Sad Serbia and Montenegro Tel +381 -21 - 459449 Fax +381 -21 - 4750572 Prispelo (Arrived): 29.08.2005 Sprejeto (Accepted): 30.09.2005 132 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)4, Ljubljana ARITMETIČNA-LOGIČNA ENOTA Z ZAPOREDNO LOGIKO ZA IZRAČUN UTEŽNE VSOTE S PROGRAMIRNIMI VEZJI Davorin Osebik1, Rudolf Babič1, Kosta Kovačič2 1Univerzav Mariboru, Fakulteta za elektrotehniko, računalništvo in informatiko, Maribor, Slovenija 2IDS d.o.o., Ljubljana, Slovenija Kjučne besede: digitalna obdelava signalov, nerekurzivna digitalna sita, aritmetično-logična enota, koncentrirana aritmetika, zaporedna aritmetika, implementacija, programirna vezja Izvleček: V članku je opisana izvedba aritmetično-logične enote z zaporedno logiko za sprotno določitev utežne vsote implementirane v programirna vezja (FPGA). Aritmetično logično enoto lahko uporabimo pri načrtovanju in izvedbi digitalnih FIR sit. Celotna struktura sita ima modularno zasnovo, ki podpira enostavno razširitev digitalnega FIR sita glede na poljubno število koeficientov. Zgradba modulov temelji na uporabi zaporedne logike za izvajanje aritmetičnih operacij. Pri načrtovanju smo se omejili na 16-bitnl zapis vhodno-izhodnega signala digitalnega FIR sita. Načrtovanje digitalnega FIR sita z opisano aritmetično logično enoto za izračun utežne vsote koeficientov zagotavlja majhno aparaturno kompleksnost in linearno naraščanje aparaturne kompleksnosti sita glede na število koeficientov. FIR sito je zasnovano tako, da se lahko uporabi kot samostojno vezje. Opisana aritmetično logična enota v sistemu digitalnega FIR sita omogoča sproten vnos koeficientov v času med dvema vzorcema vhodnega signala, zato jo lahko uporabimo tudi kot FIR enoto v sistemu adaptivnega sita. Za načrtovanje aritmetično-logične enote in njene uporabe pri izvedbi digitalnih FIR sit smo uporabili programski paket Xilinx ISE 6.1 WebPack, ki podpira vnos, sintezo vezja in implementacijo v programirna vezja. Izbrali smo programirno vezje XC3S-400, družine Spartan, firme Xilinx. Vanj smo Implementirali digitalna FIR sita z 8, 16, 32 in 64 koeficienti. Simulacijo digitalnega FIR sita smo opravili s programskim paketom ModelSim. Pri tem smo na osnovi rezultatov simulacije ugotovili, da lahko pri 16-bitnem zapisu vhodnega signala, dosežemo frekvenco vzorčenja 4.4M Hz. Arithmetic Logic Unit for Weighted Sum Calculation with Programmable Logic Cell Array Key words: digital signal processing, FIR filter, arithmetic logic unit, concentrated arithmetic, serial arithmetic, VHDL, implementation, FPGA. Abstract: In this article the design of the arithmetic logic unit with serial arithmetic procedure for weighted sum calculation and programmable logic cell array implementation is presented. This arithmetic logic unit is especially intended for adaptive FIR digital filter realization because all the coefficients of the digital filter can be changed simultaneously between two input samples. FIR digital filter with proposed arithmetic logic unit with serial arithmetic Is shown in Fig. 3. It can be designed in the modular structure (Fig. 5) that allows the whole system to be expanded to any number of coefficients with minimal effort. The previous realizations of digital filters in programmable circuits were focused on reduction of the complexity of the hardware realization /5/. The idea that stands behind the serial arithmetic structure is the reduction of hardware implementation complexity. It is shown that the hardware complexity increases linearly with the number of coefficients used (Table 1 and Fig. 8). The FIR digital filter in the modular structure consists of N cells. One cell of the modular structure Is elementary arithmetic block (Fig. 4) and consists of serial multiplier (Fig. 6), serial adder (Fig. 7) and FIFO register. The filter has been designed in the Xilinx ISE 6,1 environment. The basic units, serial multiplier, serial adder and FIFO register of digital filter structure Is designed with VHDL. The Xilinx schematic editor was used for connections between basic units. The test application is made with FIR digital filter of 16 coefficients and a 16-bit quantization of input and output signal. The Xilinx FPGA circuit XC3S-400 is used for implementation of FIR digital filter structures with 8, 16, 32 and 64 taps. The 64 taps FIR digital filter occupy only 72 % of input output blocks (IOB) and 78 % of slices of the whole XC3S-400 circuit used for this application. At 71 MHz clock frequency a sample frequency of input-output signal of 4.4 MHz has been obtained. The processing of one output signal sample needs 16 clock pulses. 1. Uvod Programirna vezja so zanimiva za implementacijo digitalnih FIR sit, kjer izračun izhodnega otipka poteka brez. uporabe zunanjega pomnilnika, za zapis delnih vsot koeficientov /1/. Struktura digitalnega FIR sita, ki uporablja arit-metično-logično enoto z zaporedno logiko za izračun utežne vsote, omogoča vpis vektorja koeficientov v času med dvema otipkoma vhodnega signala. FIR sita s takšno arit-metično-logično enoto so zanimiva v sistemih adaptivnih digitalnih FIR sit, kjer se koeficienti dinamično spreminjajo. Pri načrtovanju struktur digitalnih FIR sit, ki omogočajo vnos koeficientov v času med dvema otipkoma, ločimo strukture s porazdeljeno aritmetiko /1, 2/ in strukture s koncentrirano aritmetiko /3/. Obe strukturi je možno implementirati v eno programirno vezje, če uporabimo načr-tovalske postopke, ki zmanjšajo aparaturno kompleksnost izvedbe. Aparaturna kompleksnost je odvisna od načina implementacije diskretnega sistema. Pri povsem strojni implementaciji je aparaturna kompleksnost diskretnega sistema v glavnem odvisna od števila množilnikov za izračun izhodnega signala /4/. Zaradi tega je uporabljeno število množilnikov za implementacijo nekega sistema najpomembnejši parameter aparaturne kompleksnosti. Drugi kriterij 133 Informacije MIDEM 35(2005)3, str. 133-139 D. Osebik, R. Babič, K. Kovačič: Aritmetična-logična enota z zaporedno logiko za izračun utežne vsote s programirnimi vezji pri implementaciji diskretnih sistemov je zahteva po pomnilniku. Velikost potrebnega pomnilnika je odvisna od potrebnega števila lokacij za shranjevanje notranjih spremenljivk diskretnega sistema. Kot tretji kriterij računske kompleksnosti omenimo zbiranje in razmeščanje podatkov znotraj strukture. Zadnji, četrti kriterij pa je vpliv končne dolžine besede na čas izračuna izhodne vrednosti. Vse štiri opisane kriterije smo upoštevali pri izbiri strukture digitalnega FIR sita in pri njegovi implementacijo v programirno vezje. Pokazali bomo, da je možno z upoštevanjem vseh naštetih kriterijev v eno programirno vezje družine Spartan-3 ob uporabi 16-bitne aritmetike in 16-bitne kvantizacije vhodnih signalov, implementirati digitalno FIR sito s 100 koeficienti. Osnovno strukturo nerekurzivnega digitalnega FIR sita opišemo s konvolucijsko enačbo, ki jo opišemo tudi kot utežno vsoto, /V-1 d: V konvolucijski enačbi je vektor koeficientov h digitalnega FIR sita določen s komponentami, h=[ho, h-\,...hn--\], in vektor koeficientov vhoda s komponentami, u=[uo, l/i,...un-i]-Izvedbe digitalnih FIR sit so bile vedno povezane z iskanjem postopkov za zmanjšanje kompleksnosti algoritma, saj pomeni direktna izvedba enačbe (1) N množenj in N seštevanj za izračun otipkov izhodnega signal. Očitno je, da kompleksnost izračuna izhodnega otipka narašča z uporabljeno kvantizacijo vektorja koeficientov digitalnega FIR sita h in vektorja koeficientov vhoda u. Aparaturna kompleksnost digitalnega FIR sita narašča z večanjem števila koeficientov. Za implementacijo enačbe (1), bi bilo ugodno poiskati takšno strukturo digitalnega FIR sita, kjer bo aparaturna kompleksnost s kvantizacijo vhodno-izhodne besede in s številom koeficientov čim počasneje naraščala.. Znani pristop zmanjšanja potrebnih aritmetičnih operacij je uporaba aritmetično-loglčne enote na osnovi porazdeljene aritmetike, kjer se delne vsote koeficientov izračunajo vnaprej in se zapišejo v posebni pomnilnik /5/. Tako se potrebne operacije za izračun izhodnega signala y(k) omejijo na seštevanje in deljenje z dve. Žal pa takšne strukture ni možno uporabiti v sistemih adaptivnih digitalnih FIR sit, saj se v teh sistemih koeficienti dinamično spreminjajo. Rešitev je uporaba enote za sproten izračun koefi- cientov, ki je aparaturno najkompleksnejši del pri izvedbi digitalnega FIR sita v strukturi porazdeljene aritmetike /8/. Klasični način implementacije aritmetične-logične enote za izračun utežne vsote temelji na strukturi koncentrirane aritmetike. V strukturi koncentrirane aritmetike ločimo dve obliki nerekurzivnlh digitalnih sit. Prva je struktura s porazdeljenimi seštevalniki, ki jo prikazuje slika 1. Druga struktura digitalnega FIR sita je izvedba z enim globalnim seštevalnikom. Blokovno shemo prikazuje slika 2. m K Z * Z h i,-> y(k) ¥ Slika 2: Nerekurzivno digitalno sito v strukturi koncentrirane aritmetike s skupnim globalnim seštevalnikom Fig. 2: The FIR digital filter structure in concentrated arithmetic with a global adder Strukturo digitalnega FIR sita v koncentrirani aritmetiki s porazdeljenim seštevalnikom je enostavneje implementirati v programirno vezje. V programirnem vezju je enostavneje realizirati večje število zaporednih seštevalnikov, kot pa globalen seštevalnik. Poleg tega je struktura s porazdeljenimi seštevalniki tudi primernejša za modularno zgradbo nerekurzivnega digitalnega sita, kjer je možno enostavno povečati število uporabljenih koeficientov. Podana struktura nerekurzivnega digitalnega sita s slike 1 zadosti drugemu kriteriju o zahtevi po pomnilniku in tretjemu kriteriju o zbiranju in razmeščanju podatkov znotraj strukture. Pri uporabi strukture z globalnim seštevalnikom je potrebno za povečanje stopnje nerekurzivnega digitalnega sita spremeniti celotno strukturo globalnega seštevalnika. Postopek implementacije nerekurzivnega digitalnega sita v programirno vezje omogoča pomembno zmanjšanje aparaturne kompleksnosti izvedbe aritmetičnih operacij. Pri tem se število potrebnih aritmetičnih operacij ne spremeni. Za zmanjšanje aparaturne kompleksnosti aritmetičnih operacij uporabljenih v nerekurzivnem digitalnem situ smo uporabili zaporedno logiko /7/. Vse spremenljivke so zapisane na bitnem nivoju. Takšen zapis omogoča zmanjšanje aparaturne kompleksnosti implementacije enot za izvaja- u(k) Slika 1: Nerekurzivno digitalno sito v strukturi koncentrirane aritmetike s porazdeljenimi seštevalniki Fig. 1: The FIR digital filter structure in concentrated arithmetic with a distributed adder 134 D. Osebik, R. Babič, K. Kovačič: Aritmetična-logična enota z zaporedno logiko za izračun utežne vsote s programirnimi vezji Informacije MIDEM 35(2005)3, str. 133-139 nje aritmetično-logičnih operacij. Princip je podoben cev-Ijenju, ki ga poznamo pri mikroprocesorjih. Ideja je v tem, da se zahtevna operacija razbije na več enostavnih, katere pa lahko tečejo hitreje. Z enostavno implementacijo več enakih struktur za izvajanje aritmetičnih operacij dosežemo njihovo sočasno izvajanje. Zaradi sočasnega izvajanja arit-metično-logičnih operacij je izračun otipka izhodnega signala odvisen samo od dolžine zapisa Bu vhodne besede u(k). 2. Izvedba aritmetično-logičnih operacij z zaporedno logiko Za ponazoritev izvedbe aritmetično-logičnih operacij z zaporedno logiko vzemimo izračun produkta po enačbi (1) med vektorjem koeficientov h nerekurzivnega digitalnega sita z N koeficienti in vektorjem vhodnega signala u. V enačbi sta vektorja h in u dimenzije N. Za izračun otipka izhodnega signala y(k) potrebujemo N množenj. Če so vrednosti komponent vektorja množitelja un omejene na intervalu [-1 1 ], jih lahko zapišemo v binarni obliki z dvojiškim komplementom. bit. Z uporabo binarnega zapisa spremenljivke un v enačbo (1) zapišemo z, 7 : N-l E*. n—0 Bu-l n,0 M (3) Z zamenjavo vrstnega reda seštevanj dobimo izraz, ki omogoča izračun skalarnega produkta dveh vektorjev h in u na drugačni osnovi. Iz enačbe (3) zapišemo izraz za delne produkte pn med komponentami vektorja koeficientov vhoda un in komponentami vektorja koeficientov sita hn, Bu Pn = ^hnbn,i (4) in izraz za izračun delnih vsot produktov vpn vsot iz delnih produktov pn, 1 VPn = Pn +2P" + l n = 0,l,...,N - 1. Izračun utežne vsote med vektorjema h in u je, (5) = -b n,0 Bu n = 0,1,..., A^ — 1 (2) y = hu N-l n = 0 (6) V enačbi (2) je z Su določena dolžina binarne besede za zapis vrednosti un, z b„,\ so označene binarne spremenljivke, ki zavzemajo le vrednosti 0 ali 1. Predznak določa prvi najbolj utežen bit bn,o, £>n,Bu-i pa je najmanjši utežni Izraz (6) predstavlja tudi izračun izhodne vrednosti nerekurzivnega digitalnega sita z N koeficienti na zasnovi MAC (Multply and Accumulate) strukture. Na osnovi podanih enačb (4), (5) in (6) smo načrtali nerekurzivno sito v strukturi koncentrirane aritmetike s porazdeljenimi seštevalniki. ft;-: 6;, -H* h:,A 3h polje zaporednih množilnikov N-ti množilnik (A/-1)-ti množilnik (W-2)-ti množilnik polje /V-tih zaporednih množilnikov 3. množilnik 2. množilnik 1. množilnik u(k) Bv, •A®-..Pa-M- Mk)..... Mk)-- vm- polje zaporednih seštevalnikov ..vMA)... ..vfiu-M...... ..... jepM- ...v/fc {k). A/. polje pomnilnih celic mviM). vp»:Ak-1) mmx... y(kh: ► Slika 3: Povezava treh osnovnih enot nerekurzivnega digitalnega sita v strukturi koncentrirane aritmetike s porazdeljenimi seštevalniki Fig. 3: Tree structure of FIR digital filter in concentrated arithmetic with distributed adder 135 Informacije MIDEM 35(2005)3, str. 133-139 D. Oseblk, R. Babič, K. Kovačič: Aritmetlčna-logična enota z zaporedno logiko za Izračun utežne vsote s programirnimi vezji Strukturo nerekurzivnega digitalnega sita smo organizirali tako, da smo pri njeni implementacijo uporabili zaporedno logiko za Izvajanje aritmetično-logičnih operacij. Shemat-sko povezavo treh glavnih enot nerekurzivnega digitalnega sita v strukturi koncentrirane aritmetike s porazdeljenimi seštevalnlki, prikazuje slika 3. Digitalno FIR sito v strukturi koncentrirane aritmetike s porazdeljenimi seštevalnikl sestavljajo tri glavne enote: polje zaporednih množilnikov, polje zaporednih seštevalnikov in polje pomnilnih celic. Tako organizirana struktura digitalnega FIR sita je osnova za implementacijo v programirno vezje. 3. Uporaba zaporedne logike za izvajanje aritmetično-logičnih operacij pri implementaciji digitalnega FIR sita Namesto povezave osnovnih enot, ki določajo strukturo digitalnega FIR sita s slike 3, lahko strukturo digitalnega FIR sita prikažemo In opišemo tudi kot povezavo posameznih celic, ki vsebujejo zaporedni množilnik, zaporedni seštevalnik in pomični register. Blokovno shemo celice prikazuje slika 4. U{k) zap zaporedni množilnik P<><) Vp,,.:(k) zaporedni seštevalnik vp,(/<) pomični registri vp-.(k- Slika 4. Blokovna shema celice nerekurzivnega digitalnega sita Fig. 4: The celi block scheme of FIR digital filter Zaradi uporabe zaporedne logike za izvajanje aritmetično-logičnih operacij pri implementaciji nerekurzivnega digitalnega sita, je struktura celice simbolno prikazana z eno vrstico povezave polja zaporednih množilnikov, zaporednih seštevalnikov in polja pomičnih registrov s slike 3. To smo storili zaradi preglednosti in enostavne razširitve nerekurzivnega digitalnega sita na poljubno število koeficientov. Blokovno shemo strukture digitalnega sita zgrajeno z povezavo N celic prikazuje slika 5. Struktura digitalnega FIR sita je sedaj sestavljena iz N enakih gradnikov, ki smo jih poimenovali celice in jih označili z zaporednim številom koeficienta digitalnega FIR sita. Pri tem je z vrednostjo 0 označena celica prvega koeficienta, z vrednostjo A/-1 pa je označena celica zadnjega koeficienta. Podana zaporedna vezava enakih celic digitalnega FIR sita poenostavi Implementacijo FIR sita v programirna vezja, prav tako tudi poenostavi razširitev digitalnega FIR sita na poljubno število koeficientov. Ta oblika strukture digitalnega FIR sita omogočil, da krmilni del sita, ki skrbi za pravilne prenose vmesnih rezultatov in za brisanje registrov ostane popolnoma nespremenjen. Struktura digitalnega FIR sita z uporabo celic, je v celoti načrtana z uporabo zaporedne logike za izvajanje aritmetično-logičnih operacij. Ugotovimo lahko, daje digitalno FIR sito, prikazano na sliki 5, sestaviljeno z N celicami. Le za prvo in zadnjo celico smo uporabili drugačno zasnovo. Prvo celico (ce//cao) smo načrtali brez zaporednega seštevalnika, zadnjo celico (ce//caNj) smo načrtali brez pomičnega registra. Najkompleksnejši element celice s slike 4 je zaporedni množilnik, ki opravlja produkt med otipki vhodnega signala u(k) In komponentami hn(k) vektorja koeficientov nerekurzivnega digitalnega sita. Vhodni signal množitelja u(k) digitalnega sita je zapisan v zaporedni obliki z dvojiškim komplimentom. in ga podaja enačba (2). Signal množenca hn(k) koeficienta digitalnega sita je zapisan v vzporedni obliki. Vrednost vmesnega produkta pn(k) se izračuna po enačbi (4) z zaporednim množilnlkom. u(k)z ap U(k) zap ce lica o ho Sh Slika 5: Medsebojna povezava N celic nerekurzivnega digitalnega sita Fig. 5: The celi structure of the digital FIR filter 136 D. Osebik, R. Babič, K. Kovačič: Aritmetična-logična enota z zaporedno logiko za izračun utežne vsote s programirnimi vezji Informacije MIDEM 35(2005)3, str. 133-139 By > .cl.k....... u (k) p ( n rili tj, m h nt.e^ U 11 , p. , I i prf j m l II' j! krmilno vezje za krmiljenje zaporednega množilnika Bh (BH+2)-bitni multiplekser & & Bh Sh+2 D[(BH+1)..0] Q[0] Q[(BH+1)..1] (BH+2)-bitni register Sh A[(Bh+1). .0] (Bn+2)-bitni seštevalnik S[(Bh+2)..0] B[(BH+1)..0] sešt./odšt. Sh+2 ■Bh+2 Bh B[Bh] Q[BH] (Bn+2)-bitni pomični register pn(k) pcn{k) Slika 6: Blokovna shema zaporednega množilnika Fig. 6: Serial multiplier block scheme Takšna izvedba množilnikov z zaporednim izvajanjem množenja dveh spremenljivk hn(k) in u(k) močno zmanjša aparaturno kompleksnost celotnega vezja. Pri iterativnem deljenju z 2 ostane na izhodu Q[0] bitnega registra, dolžine Sh+2, vrednost ostanka p0(k), ki je dolžine Bu bitov. Ta ostanek je v zaporedni obliki, zato ima prikazani zaporedni množilnik na sliki 6 za izhodno vrednost zmnožka pm(k) dva izhoda: izhod utežnega dela besede pn{k) dolžine Sh bitov in izhod najmanj utežnega dela besede pom(k) dolžine Su bitov. Za končno vrednost delnega produkta smo uporabili le zgornjih 16 bitov. Podana oblika zaporednega množilnika potrebuje le en seštevalnik, multiplekser dolžine Sh bitov, ki ga sestavlja polje Sh dvovhodnih IN vrat in zadrževalnik vmesnih vsot. Za krmiljenje zaporednega množilnika digitalnega FIR sita skrbi krmilno vezje. Drugi element celice je zaporedni seštevalnik, ki izračuna vrednost delne vsote vpn{k) po enačbi (5). Blokovno shemo zaporednega seštevalnika prikazuje slika 7. ../In.. ...Bn.. Cl AO BO CO SO Slika 7: Blokovna shema zaporednega seštevalnika Fig. 7: Serial adder block scheme Na sliki 7 je prikazan zaporedni seštevalnik ima dva vhoda. Na vhod An je pripeljemo n-to komponento delnega produkta pn(k) in na vhod Bn pripeljemo n-to komponenta delnega produkta pn+iW, ki se iterativno deli z dve, kot to opisuje izraz (5). Izhod Sn predstavlja novo izračunano vrednost vsote delnega produkta vpn. Tretji sestavni del celice, prikazane na sliki 4, je pomični register (FIFO). Sestavljen je iz D pomnilnih celic velikosti Su-bitov. Poleg treh opisanih enot celice, je za delovanje sita potrebno še uporabiti enoto za sinhronizacijo in enoto za vpis koeficientov. Za znižanje cene končnega izdelka pa je potrebno imeti v mislih čim manjše število uporabljenih priključkov, s tem bo tudi zunanji vmesnik programirnega vezja manjši. Ob inicializaciji programirnega vezja, je vanj potrebno vpisati vektor koeficientov digitalnega FIR sita h. Struktura nerekurzivnega digitalnega sita pa se lahko preuredi tudi tako, da so koeficienti zapisani že v samem čipu, če aplikacija ne zahteva spreminjanja koeficientov. Čas vnosa koeficientov namreč podaljša inicializacijo nerekurzivnega digitalnega sita za 16 period signala ure. Takšna struktura nerekurzivnega sita omogoča prilagajanje sita uporabljeni aplikaciji. Pri uporabi nerekurzivnega digitalnega v adap-tivnem sistemu je možen sproten vnos koeficientov. Načrtovanje sita je potekalo s programskim paketom ISE 6.0 podjetja Xilinx. Na najvišjem nivoju je potekalo načrtovanje na osnovi shematskega vnosa z načrtovalskim orodjem Xilinx ECS (Engineering Capture System). V jeziku VHDL je potekalo načrtovanje zaporednega množilnika, FIFO registrov in zaporednih seštevalnikov. 4. Rezultati Implementacijo digitalnega nerekurzivnega digitalnega sita v programirno vezje smo opravili s pomočjo programskega 137 Informacije MIDEM 35(2005)3, str. 133-139 D. Osebik, R. Bablč, K. Kovačič: Arltmetična-logična enota z zaporedno logiko za Izračun utežne vsote s programirnimi vezji razvojnega orodja ISE 6.1 podjetja Xilinx. Za testno aplikacijo digitalnega FIR sita smo uporabili 16 koeficientov s 16-bltno kvantizacijo. Prav tako smo vhodno-izhodno besedo zapisali s 16-bitno kvantizacijo. Na osnovi simulacijskih rezultatov dobljenih s programom ModelSim smo ugotovili, da znaša največja frekvenca osnovnega signala ure 71 MHz. Za procesiranje enega otipka potrebujemo 16 period osnovnega urinega signala, kar omogoča frekvenco vzorčenja 4.4MHz. Odvisnost linearnega naraščanja strukture digitalnega FIR sita od stopnje sita, smo preverili z implementacijo štirih različnih stopenj digitalnih FIR sit v programirno vezje XC3S-400 firme Xilinx /9/. Vezje je družine Spartan-3 s sistemom 400k vrat kar ustreza 8,064 logičnim celicam. Velikost matrike konfiguracljskih logičnih celic (CLBs Configurable Logic Blocks) je dimenzije 32x28, kar znese 896 konfiguracljskih logičnih celic. Vsaka celica zaseda v strukturi programirnega vezja štiri rezine (Slices). Uporabljeno programirno vezje XC3S-400 s 3584 rezinami je eno manjših v družini Spartan-3. Ta družina vsebuje vezja od 50k vrat do 5M vrat, kar je od 200k do 20M rezin (Slices). Implementacijo smo izvedli za sita z 8, 16, 32 in 64. koeficienti. V tabeli 1 je podana zasedenost programirnega vezja glede na število vhodno izhodnih priključkov (IOB) in število uporabljenih rezin (Slices). Pri vseh digitalnih FIR sitih smo uporabili 16-bitno kvantizacijo vhodno-izhodne besede. Tabela 1: Zasedenost programirnega vezja XC3S-400 pri implementaciji digitalnega FIR sita z 8, 16, 32 in 64. koeficienti Table 1: The programmable FPGA device XC3S-400 utilization for 8, 16, 32 and 64 taps digital FIR filter število koeficientov 8 16 32 64 število vhodno-izhodnih 16 25 39 72 priključkov (lOBs) (7%) (11%) (17%) (32%) (max 221) število rezin (Slices) 349 702 1407 2829 (max 3584) (9%) (19%) (39%) (78%) Na sliki 8 podajamo odvisnost zasedenosti programirnega vezja XC3S-400 glede na število vhodno-izhodnih priključkov in glede na število uporabljenih rezin (Slices) v odvisnosti od stopnje sita. Izbrali smo digitalna FIR sita z 8, 16, 32 in 64. koeficienti. Iz slike 8 vidimo, da zasedenost programirnega vezja narašča praktično linearno s stopnjo digitalnega FIR sita. Zasedenost programirnega vezja XC3S-400 pri implementaciji digitalnega FIR ¿ita s 64. koeficienti In 16-bitno vhodno-izhodno besedo znaša 78% strukture in 72% vhodno-izhodnih priključkov uporabljenega programirnega vezja XC3S-400. V večja programirna vezja družine Spartan 3 pa lahko brez težav implementiramo nerekurzivna digitalna sita z več kot 100 koeficienti. —- lOBs ■ - O- ■ Slices ■ 1 .........:;a " " ......... Slika 8: Odvisnost zasedenost programirnega vezja XC3S-400 od stopnje sita pri implementaciji digitalnega FIR sita z 8, 16, 32 in 64. koeficienti Fig. 8: The programmable FPGA device XC3S-400 utilization for 8, 16, 32 and 64 taps digital FIR filter Takšno izvedbo aritmetične logično enote za izračun utežne vsote in njeno uporabo v digitalnih FIR sitih lahko izvedemo FIR sita s 100 koeficienti le z enim programirnim vezje družine Spartan-3. 5. Zaključek V prispevku smo opisali aritmetično-logično enoto z zaporedno logiko za izračun utežne vsote s programirnimi vezji. Opisano aritmetično-logično enoto smo uporabili pri implementaciji digitalnega FIR sita. Podrobno smo opisali strukturo aritmetične-logične enote, pri katerem smo uporabili zaporedno logiko za izvajanje aritmetičnih operacij. V ta namen smo razvili zaporedni množilnik, kjer je množitelj podan v zaporedni obliki, množenec pa v vzporedni obliki. V nerekurzivnem digitalnem situ z N koeficienti smo uporabili N zaporednih množilnikov. Za implementacijo A/-1 porazdeljenih seštevalnikov, smo uporabili zaporedne sešte-valnike. Postopek načrtovanja je potekal s pomočjo programskega paketa Xilinx ISE 6.1 VVebPack. Na najvišjem nivoju smo uporabili shematskl vnos strukture, na najnižjih nivojih smo opisali posamezne enote v VHDL jeziku. S takšnim pristopom smo zelo dobro izkoristili strukturo programirnega vezja. Uporaba aritmetično logične enote za izračun utežne vsote v digitalnem FIR situ omogoča njegovo implementacijo v le eno programirno vezje družine Spartan-3 firme Xilinx. Takšna izvedba digitalnega FIR sita, ki omogoča vpis vseh koeficientov v času med dvema otip-koma vhodnega signala, je primerna za uporabo v adap-tlvnih sistemih. Opravili smo implementacijo štirih različnih stopenj digitalnega FIR sita v programirno vezje XC3S-400: z 8, 16, 32 In s 64. koeficienti. Pri vseh treh stopnjah smo uporabili 16 bitno kavantizacljo vhodno-izhodne besede. 138 D. Osebik, R. Babič, K. Kovačič: Aritmetična-logična enota z zaporedno logiko za izračun utežne vsote s programirnimi vezji Informacije MIDEM 35(2005)3, str. 133-139 Z ugotavljanjem odvisnosti med zasedenostjo pro-gramirnega vezja in stopnjo nerekurzivnega digitalnega sita smo pokazali, da zasedenost programirnega vezja narašča praktično linearno s številom koeficientov sita. Pokazali smo tudi, da zaseda implementacija digitalnega FIR sita s 64. koeficienti in 16 bitno kavntizacijo vhodno-izhodne besede 72% vhodno-izhodnih priključkov in 78% notranje strukture programirnega vezja XC3S-400. S tem smo tudi pokazali, da uporaba opisane aritmetične logične enote za izračun sprotne utežne vsote v digitalnem FIR situ, omogoča implementacijo digitalnih sit z 100 koeficienti v eno samo programirno vezje. 6. Literatura /1/ Kaluri, K.; Wen Fung Leong; Kah-Howe Tan; Johnson, L.; Sod-erstrand, M.; Implementation of Adaptive Control on an FPGA, Signals, Systems and Computers, 2001, FPGA Hardware Implementation of an RNS digital FIR filter, Conference Record of the Thirty-Fifth Asilomar Conference on , Volume: 2 , 4-7 Nov. 2001 Page(s): 1340-1344 vol.2 /2/ Steve Knapp, FPGAs furnish fast, furious FIR filters, Personal Engineering and Instrumentation News, Vol, 15, No. 12, pp. 52-55, Dec. 1998 /3/ Vails, J.; Sansaloni, T.; Pelro, M.M.; Boemo, E., Fast FPGA-based pipelined digit-serial/parallel multipliers, Circuits and Systems, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on, Volume: 1, 30 May-2 June 1999 Pages: 482-485 vol.1 /4/ Gregory Ray Goslln A guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance, Xilinx 1995, (Version 1.0) /5/ R. S. Grover, W. Shang, Q., A Faster Distributed Arithmetic Architecture for FPGAs, Tenth ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, February 24-26, 2002 /6/ Rolf Enzler, Tobias Jeger, Didier Cottet and Gerhard Troster, High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs, R. W. Hartensteln and H. Grunbacher(Eds.) FPL 2000, pp. 512-534 2000, Springer-Verlag Berlin Heidelberg 2000 /7/ Steve Knapp, FPGAs furnish fast, furious FIR filters, Personal Engineering and Instrumentation News, Vol. 15, No. 12, pp. 52-55, Dec. 1998. /8/ OSEBIK, Davorin, BABIČ, Rudolf, SOLAR, Mitja. Adaptivna struktura s polji programirnih vezij za izvedbo nerekurzivnih digitalnih sit. Inf. MIDEM, september 2003, letn. 33, št. 3(107), str. 170-1771 /9/ Xilinx, Spartan-3 FPGA Family: Introduction and Ordering Information, Preliminary Product Specification, DS099-1 (v1.4) January 17, 2005 /10/ Herman H. Schmit, Srlhari Cadambl, Matthew Moe, Seth C. Goldstein, Pipeline Reoonfigurable FPGAs, Journal of VLSI Signal Processing Systems 24, 129-146, 2000. mag. Davorin Osebik, tei (02) 220-7238, e-mail: davorin. osebik@uni-mb. si izr. prof. dr. Rudolf Babič, tel.: (02) 220-7230, e-mail: rudolf. babic@uni-mb. si Univerza v Mariboru Fakulteta za elektrotehniko, računalništvo in informatiko Smetanova 17, 2000 Maribor Tel.: (02) 220 7000, Fax (02) 251-1178 Kosta Kovačič univ. dipl. inž. e/, tel: (01)281 1183, e-mail: kosta.kovacic@ids.si IDS d. o. o., Sojerjeva 63, 1000 Ljubljana Tel: (01) 281 1183, Fax: (01) 281 1184 Prispelo (Arrived): 29.08.2005 Sprejeto (Accepted): 30.09.2005 139 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)4, Ljubljana INTEGRAL NONLINEARITY DETERMINED BY SELECTION ORDER OF CURRENT ARRAY UNITS IN DA CONVERTERS Roman Benkovič1, Kosta Kovačič1 and Anton Pleteršek2 11DS, Ljubljana, Slovenia 2Faculty of Electrical Engineering - University of Ljubljana, Ljubljana, Slovenia. Key words: CMOS D/A converter, current array, bits-selection-order, thermometric converter Abstract: This paper analyses characteristic of switching-scheme for the curent source array that was used in 14-bit CMOS DA Converter It presents 8-bit thermometric bits-selection-order (BSO) analysis results, where the single bit current source is constructed as a group of two equal cell-units. The BSO order algorithm varies position of the group, while the current-cells inside the group are always placed simetrically over the center of the layout area. Bit-selection-order value is a decimal code value of the position selection. The final solution is compared with straight horizontal and straight vertical BSO with different error distributions from which posible integral nonlinearity (INL) of the final product, can be estimated. The analysis of error distribution influence on INL further demonstrates that with bits mixed selection-order INL error is always below 0.05 LSB when average current error is below 1%. Integralna nelinearnost določena z zaporedjem izbire tokovih virov v DA pretvornikih Kjučne besede: CMOS D/A pretvornik, polje tokovnih virov, zaporedje preklapljanja bitov, termometričen pretvornik Izvleček: Ta članek obravnava karakteristiko preklopne sheme za polje tokovnih virov, ki je bilo uporabljeno v 14-bitnem CMOS digitalno - analognem pretvorniku. Predstavljeni so rezultati analize 8-bitnega termometiičnega zaporedja izbire (BSO), kjer je bitni tokovni vir zgrajen kot enota dveh enakovrednih osnovnih tokovnih celic. BSO algoritem spreminja mesto bitnega tokovnega vira, medtem ko sta osnovi tokovni celici vedno postavljeni simetrično, glede na center geometrije polja tokovnih virov. BSO vrednost predstavlja decimalno kodo izbire mesta bitnega tokovnega vira. Integralna nelinearnost (INL) končnega izdelka je ovrednotna z različnimi porazdelitvami napake (Slika 3), glede na vodoraven (Slika 1) in navpičen (Slika 2) BSO algoritem. Analiza vpliva porazdelitve napake na INL kaže, daje INL napaka pri mešanem BSO (Slika 4) vedno pod 0,05 LSB, če je povprečna tokovna napaka pod 1%. 1. Introduction Low integral nonlinearity (INL) in high-bit-count DA Converters is dificult to accomplish with resistor-strings, R2R converters, or binary-weighted current sources /6, 1, 3, 5, 2/. Studies and measurenments indicate that there are non-constant process parameters and region gradient over silicon wafer. In our research we used aproach of two current arrays where each of the array was controlled with thermometer coders. It is therefore our goal to search for the most suitable organisation of an array, number of current units in one step group and, on the most suitable switching-scheme for 8-bit current array. As already explained in /4/, to suppress the linear error, the current step must be split into more than one current units per-step. To minimize the silicon area, only two current units per one unit group were used and placed symet-rically over center of the array. Considering last statement we have 2 x 256 current units. Because of technology isues, seperated functional blocks (sources, switches an selectors) would result In an increased circuit area. In our research our goal Is to combine all functions in one cell - current logic block (CLB) cell /8/. CLB cells are composed of: current source with cascode devices, switches to one of two current outputs and digital selection circuit, which determines the state of the switches from horizontal and vertical control signals. Proportion of CLB dimensions is set to 1:10, so the shape of current array was chosen to be 8 x (32 x 2) with additional columns for biasing circuit. 2. First accession Two reference selection-orders of the BSO were used in analysis: horizontal selection-order (Figure 1) and vertical selection-order (Figure 2). For both reference principles, unit group consists of two CLB cells, placed symmetrically to center. To find proper solution, we have to cosider which effects have influence on the resulting INL error and how does the gradient of the process parameters effect the INL error (Figure 3 /7/). 140 R. Benkovic, K. Kovacic, A. Pletersek: Integral Nonlinearity Determined by Selection Order of Current Array Units In Da Converters Informacije MIDEM 35(2005)3, str. 140-143 All the results are found in Figure 5. It is evident that all even order distributions yield zero INL error, as we already assumed when splitting step units in two current cells (CLB's). As can be seen in Figures 3.c and 3.g for 1-D parabolic error distribution INL error results (Figures 5.c and 5.g) are resembling. The main difference is that in Figure 5.g, vertical 1-D error distribution, the ratio between horizontal an vertical BSO is four times higher than in horizontal 1-D distribution (Figure 5.c) which corresponds to CLB array shape 8 x (32 x 2). Superior results are achieved for vertical selection-order. Selected step order goes more frequently from one edge to the other vertically (8 steps) than horizontally (32 steps) which means that final solution will include best results if selections are distributed through all array area as frequently as possible. Simmilar results are presented in Figure 5.e. 3. Proposed solution - mixed selection-order To build more flexible BSO algorithm, it is possible to cover more complex parameters gradient over silicon as well as taking into account any CLB array shape. The BSO anal- Figure 3: Error distribution through array area. 141 P os ition x [urn] . 200 ___ 300 400=400 400 . 300 . 200 100 '1 00 P os ition y [um] Figure 1: Horizontal selection-order. 100 Position y [um] Position x [um] 400400 Figure 2: Vertical selection-order. Unit Mismatch Unit Mismatch !%1 R. Benkovič, K. Kovačič, A. Pleteršek: Integral Nonllnearlty Informacije MIDEM 35(2005)3, str. 140-143 Determined by Selection Order of Current Array Units In Da Converters ysis indicates that the most encauraging results can be achieved by mixing horizontal and vertical bits order. In our research, we proposed bits mixed selection-order (BMSO), as shown in Figure 4. Figure4: Mixed selection-order. Using this approach, it is therefore evident that the random parameter distributions are covered much better, even with only two unit cells building the MSB group.The results of INL errors from Figure 5 show that for most common errors (Figure 5c, 5g and 5i), INL error is always below 0.05 LSB when average current error does not exceed 1% thermometric active area (Figure 3). 4. Conclusions Theoretical analysis supported by the predicted and realistic distribution of the process parameters over the silicon area was implemented on integrated digital to analog converter, costructed by the thermometric 8-bit subblock. After the measuring, results will determine resolution for the overall high resolution D/A. Through we can conclude that the complete converter can be covered only by thermometric subblocks, probably including a less complicated autocallibration block. 50 ¡00 1 so (a) f - 0 250 300 (b) f = X horizontal order ------ A / \ - ./'\ X\ A ,.,A. A,.. V' V \J \ 'v/ \y \J (c) f = X iso 200 250 300 2 honzontal order---- \ ; \J 150 200 250 300 SO 100 200 250 300 so 100 iso 200 250 300 (d) f = y (e) f = xy (f)f = x2 y horizontal order----- \ mixed order ■ / \ \ \ ' / \ /' \ / vA - horizontal order vertical oriJsr 50 100 150 200 250 300 Code (g) f = y2 0 so 100 150 200 2s0 300 Code (h)f = xy2 Figure5: INL vs. selection-order. tio.izo ,. .:. ... ..__ "m ■ i1 \\ ■ :v 1 f>J w V v, V, .-:* | (i rvJ - if : so 100 150 200 250 300 (i)f - x2 y2 142 R. Benkovic, K. Kovacic, A. Pletersek: Integral Nonlinearity Determined by Selection Order of Current Array Units In Da Converters Informacije MIDEM 35(2005)3, str. 140-143 5. Acknowledgments Authors would like to thank the staff members of IDS for the support in the project. References: /1/ Jose Bastos and Michel S. J. Steyaert. A 12-bit intrinsic accuracy high-speed CMOS DAC. IEEE Jurnal of Solid-State Circuits, 33(12): 1959—1969, December 1998. /2/ Jose Bastos, Michel S. J. Steyaert, Benny Graindourze, and Willy Sansen. Matching of MOS transistors with different layout styles. Proc. IEEE Int. Conference on Microelectronic Test Structures, number 12, pages 17-18. IEEE, March 1996. /3/ Jose Bastos, Michel S. J. Steyaert, and Willy Sansen. A high yield 12-bit 250-ms/s CMOS D/A converter. In Proceedings IEEE 1996 CICC, pages 431-434. IEEE, May 1996. /4/ Geert A. M. Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, and Georges G. E. Gielen. A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Jurnal of Solid-State Circuits, 34( 12>: 1708—1718, December 1999. /5/ Kadabar R. Lakshniikumar, Robert A. Hadaway, and Miles A. Copeland. Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE Jurnal of Solid-State Circuits, 21(61:1057-1066, December 1986. /6/ Chi-Hung Lin and Klaas Bult. A 10-b, 500-ms/s CMOS DAC in 0.6 mm2. IEEE Jurnal of Solid-State Circuits, 33(12): 1948-1958, December 1998. /7/ Marcel J. M. Pelgrom, Aad C. J. Duinmaijer, and Anton P. G. Welbers. Matchinh properties of MOS transistors. IEEE Jurnal of Solid-State Circuits, 24(5): 1433-1440, October 1989. /8/ Louis SY Wong, Chee Y. Kwok, and Graham A. Rigby. A 1-v CMOS D/A converter with multi-input floating-gate MOSFET. IEEE Jurnal of Solid-State Circuits, 34(10):1386-1390, October 1999.Roman Benkovic Roman Benkovic IDS d.o.o. Sojerjeva 63, 1000 Ljubljana roman. benkovic@ids.si Kosta Kovacic IDS d.o.o., Sojerjeva 63, 1000 Ljubljana kosta.kovacic@ids.si doc. dr. Anton Pleteršek Faculty of Electrical Engineering Tržaška 25, 1000 Ljubljana ant on @kalvarija. fe. uni Prispelo (Arrived): 29.08.2005 Sprejeto (Accepted): 30.09.2005 143 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)4, Ljubljana DEVELOPMENT OF USB 2.0 COMPLIANT GPIB CONTROLLER Bostjan Glazar, Marko Jankovec, Marko Topic University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Key words: Automated measurement, Computer interfaces, General Purpose Interface Bus Abstract: This paper describes a development ot a custom designed General Purpose Interface Bus (GPIB) controller which is used as the interface between GPIB and PC. The controller is designed as a Universal Serial Bus (USB) 2.0 compliant external device, which provides plug-and-play operation, high speed of data transfer and is powered fully from the USB. In contrast to conventional GPIB controllers In the form of PC cards, such a design extends its usage to notebooks or other computers with no available I/O slots. The FLASH program memory based AT90S8515 microcontroller which is used for data transfer and protocol handling also enables easy firmware upgrade. For simple controller usage the appropriate driver is developed in a graphical programming language LabVIEW, which we use for instrument control software development. Razvoj GPIB krmilnika združljivega z USB 2.0 Kjučne besede: Avtomatizirane meritve, računalniški vmesniki, GPIB Izvleček: Članek opisuje razvoj krmilnika za GPIB vodilo (General Purpose Interface Bus), ki se uporablja kot vmesnik med GPIB vodilom in osebnim računalnikom. Krmilnik se na računalnik priključi preko univerzalnega serijskega vodila (USB), ki omogoča enostavno uporabo, visoko hitrost prenosa podatkov in nudi napajanje. Za razliko od običajnih GPIB krmilnikov, ki so osnovani kot vtične kartice, je ta krmilnik primeren tudi za prenosnike in računalnike brez prostih razširitvenlh rež. Jedro krmilnika je mlkrokrmilnik AT90S8515, ki je vsebuje FLASH spomin in tako omogoča enostavno nadgradnjo programske opreme. Za enostavno uporabo krmilnika smo izdelali tudi gonilnik za programski jezik LabVIEVV, ki ga tudi uporabljamo za avtomatizacijo meritev 1. Introduction Personal computers became necessary equipment in science laboratories in the last decade /1 / . One of reasons is their usage in measurement automation and documentation which is achieved with computer-controlled instruments. A very popular interface for connection between the PC and instruments is General Purpose Interface Bus (GPIB), which is still the most common interface, although several other types of interfaces (Universal Serial Bus (USB), IEEE 1394, Ethernet, etc.) are on the move /2/, /3/. Reasons forthis include numerous GPIB instruments available and low latency when compared to otherwise faster standards in parentheses above /4/. To connect instruments to a PC a suitable GPIB controller is required which is usually in a form of a computer card. Because of relatively simple design and low-cost components we have decided to develop a GPIB controller ourselves. Since we wanted the controller to be applicable also for notebooks, we have chosen USB, which is the most common built-in interface on contemporary computers. Our concept was accepted as Design idea in EDN Journal /5/. In the following, the development of the USB based GPIB controller will be presented in detail and an example of its usage will be given. 2. Development of USB based GPIB controller GPIB /6/, initially named Hewlett-Packard Interface Bus (HP-IB), later standardized as IEEE-488 and IEC-625, is a parallel bus that uses 24-pin connector to connect devices in a star or a bus configuration. There are three main types of devices on the GPIB bus; controller, talker and one or more listeners. The bus can have only one active controller, which is a bus master and addresses devices to talk or listen by use of GPIB bus commands. A talker transmits data that are received by one or more listeners. The GPIB controller we developed is designed as a USB device controlled by a host PC, where one port of the controller is connected to the USB and other to a GPIB bus. The controller is built on a double-sided PCB that fits into a box of outer dimensions of 123 mm x 30 mm x 70 mm. In order to simplify the usage of the GPIB controller a LabVIEW driver was developed, which communicates with the controller by a custom developed protocol through USB using a virtual COM port (VCP) driver. To simplify adaptation of existing programs in LabVIEW, the driver is compatible to the built-in one. In the following sections the hardware, protocol, firmware and the driver are described in detail. 3. Hardware The controller can be divided into three main parts, where the microcontroller as the central block represents the communication gateway between PC (through USB interface) and GPIB bus (through GPIB line drivers), as shown in Fig. 1. 144 B. Glazar, M. Jankovec, M. Topic: Development of USB 2.0 Compliant GPIB Controller Informacije MIDEM 35(2005)3, str. 144-147 Fig. 1: Block diagram of the USB based GPIB controller USB interface is based on a FTDI FT245BM integrated circuit /7/ that provides an 8-bit parallel interface to the microcontroller and a virtual COM port on the PC side. Built-in buffer (FIFO) greatly simplifies firmware in the microcontroller. The integrated circuit provides USB 2.0 compatibility and allows data transfer under USB 1.1 specification, i.e. 12 Mb/s. It also provides an output line that goes low when it is enumerated and USB is not in suspend state. External memory chip provides storage for information such as product description and maximum current consumption and can be programmed directly from a host PC. At GPIB side of the controller appropriate line drivers are required to meet GPIB standard specifications of 48 mA sink current and high impedance state when no power is applied. Standard integrated circuits, 75160 /8/ and 75161 /9/ developed especially for GPIB are used, while sequence control is completely implemented in controller's firmware. The most important control signals for operation for data transfer are Attention (ATN), Data Valid (DAV), Not Ready For Data (NRFD), Not Data Accepted (NDAC) and End Or Identity (EOI). Direction of signals is controlled by TE (Talk Enable) input for data and handshake lines and by DC (Direction Control) for management lines. Both signals are controlled by the firmware. An AVR microcontroller Atmel AT90S8515 /10/ is used to control all circuitry. It is a 44 pin RISC device with in-circuit programmable FL<\SH memory and many peripheral units, which are not all utilized in our case, since besides input / output (I/O) ports the only peripheral unit used is timer. In-circuit programming through a 6-pln connector simplifies firmware design and its upgrades. The microcontroller runs at its maximum frequency of 8 MHz to allow the fastest data transfer possible. Both external interrupts are used in conjunction with the USB interface. One triggers when USB goes to suspend state, while the other wakes up the microcontroller on the first received byte. USB provides power supply of +5 V / 500 mA and thus allows low power devices to be used without additional power supply. In our design USB interface with memory IC and microcontroller are powered directly from USB, while GPIB buffers are powered from USB through a transistor switch. Overall maximum current consumption ofthe controller is 320 mA during normal operation and is minimized during USB suspend state, by disconnecting the GPIB buffers from the power supply and setting the microcontroller to low-power mode. Fig. 2 shows the PCB ofthe controller, while Fig. 3 shows the controller with connected USB and GPIB cables. The PCB was made using milling machine and partially assembled on the manual SMD placerthatwe use for research & development prototypes and educational purposes. Predominant use of SMD components in the controller makes its fabrication easily automated and lowers the cost of components. ¡■lip -Ö Fig. 2: Top view of printed circuit board of the controller Fig. 3: The controller with connected cables 4. Protocol The controller communicates with the PC through a logical serial interface which does not provide control signals and registers like plug-in boards and therefore a certain protocol is necessary to distinguish between data and control bytes. We have developed a protocol, which is based on the AT protocol for modems; commands begin with letters IB, which are followed by a one character command code and an optional binary or character parameter. Bus commands are sent as binary values, which enables each of 256 possible values to be transferred. The problem of transferring binary data or a problem of data transparency was solved by a protocol similar to Binary Synchronous Communication (BSC) protocol /11 / in which three control characters are used to transfer a binary data block. These are Data Link Escape (DLE), Start Of Text (STX) and End Of Text (ETX). A data block always begins with the pair DLE/STX and ends with DLE/ETX. If a DLE is to be transferred anywhere in the data stream, it is followed by another DLE, 145 Informacije MIDEM 35(2005)3, str. 144-147 B. Glazar, M. Jankovec, M. Topic: Development of USB 2.0 Compliant GPIB Controller denoting it as a part of the data as can be seen in Fig. 4. Bus addressing when sending or receiving data is not implemented in firmware and has to be done by sending bus commands, which is implemented In the driver. The controller commands are listed in Table 1. All responses of the controller are one byte long to allow simple interpretation and include success code or error specific code. DLE STX data DLE DLE data DLE ETX Fig 4: BSC protocol 5. Firmware The AVR microcontroller is used to control all lines of the GPIB Interface and to communicate with the PC through the USB interface. Main loop of firmware program contains two major successive operations: (a) waiting for IB delimiter and receiving a command and (b) executing the command. If the command is in error (i.e. too long or an invalid command code) it is rejected and a Negative Acknowledge (NAK) Is returned to the PC. Data and bus command transfer have a time limit for each transferred byte. If time-out occurs the microcontroller's program sends an error code to the PC and the loop repeats. When USB goes into suspend state the transfer is also interrupted and is followed by powering off the GPIB drivers and putting the microcontroller into low-power mode. The microcontroller wakes up again when another byte is received. The program was written In C language, compiled by CodeVision AVR and is approximately 1500 words (3.0 KB) long. The execution speed of the microcontroller mainly determines the maximum data transfer rate which is in our case theoretically limited to 225 KB/s. Actual measured transfer rates using HP54522A digital oscilloscope were 190 and 174 KB/s for talking and listening, respectively. 6. PC driver We designed a driver in LabVIEW /12/ environment as a collection of Vis, since LabVIEW is widely Implemented at our faculty and at the same time it is one of the most popular programs for measurement control and automation. LabVIEW allows fast development of complex and easy-to-use programs. The driver is compatible with the Lab-VIEW's built-in GPIB driver simplifying adaptation of existing programs to the new interface. Only one additional input is required, I.e. serial port number. Vis are described below. USB GPIB Initialization opens serial port, powers on the controller and initializes It according to specified parameters (re-addressing required, REN state). USB GPIB Write transfers data to a device. It also addresses the device if an address is given and the device is not already addressed. After data exchange, the function de-addresses the device if specified at initialization. This addressing logic is the same for all functions. USB GPIB Read reads data from a device. The VI will stop reading when EOS is detected or specified number of bytes received. This is additional option to the EOI Implemented in firmware. Data transfer mode for write and read (EOI, End Of String character (EOS)) can be adjusted with a parameter. Command Function IB Powers on and initializes the controller. IBCx, IBcx Sends byte x (binary) as a bus command. ATN line can be released after transfer or not, which enables multi-byte commands to be sent. IBclata Sends binary data to GPIB bus. Returns error if there is no listener. IB? Receives binary data till EOI is detected, timeout or cancelled. IBB Receives one byte (ignores EOI). IBIx Sends identification string to the PC. IBZ Conducts interface clear. IBO Powers off the controller. IBe Sets EOI mode for sending data. IBt, IBT Sets timeout for handshake and total timeout. IBm Controls state of REN line. IBDEXAA, IBDTx, IBDCx, IBDMx, IB D ?x Debug commands enables each line of the GPIB bus to be independently controlled. They are useful when developing new protocol and for hardware debugging. Table 1: Controller commands 146 B. Glažar, M. Jankovec, M. Topič: Development of USB 2.0 Compliant GPIB Controller Informacije MIDEM 35(2005)3, str. 144-147 USB GPIB Clear resets a device or all devices using Selected Device Clear (SDC) or Device Clear (DCL). Which command is send depends on whether an address is given. USB GPIB Read STB reads status byte using serial poll. USB GPIB Wait RQS calls USB GPIB Read STB in regular interval waiting for request bit to be set. This bit is an indicator that a device needs attention (ex. measurement is finished). USB GPIB Close powers off the controller and closes serial port. The microcontroller performs only simple tasks while higher level operations are implemented in the driver. For example: the controller cannot address a device, send data to it and de-address using a single command from the PC. This must be implemented in three steps, i.e. with three controller commands. This separation enables many features to be implemented or updated without changing the controller's firmware and enables faster and simpler updates since the reprogramming of the microcontroller is not required. Since many other programs (Visual Designer, FieldPoint and HPVee and other programs like MATL7\B, C++ or Visual Basic) support virtual serial port, our USB based GPIB controller needs no hardware or firmware changes, but only specific drivers to be implemented in these programs. 7. Discussion and conclusions The USB GPIB controller was developed as a compact plug-and-play device with maximum transfer rate of 225 KB/s. Predominant use of SMD components in the controller makes its fabrication easily automated and lowers the cost of components. Firmware of the microcontroller can be upgraded to support other GPIB features like operation as a device. Upgrading can be very simplified by using newer version of microcontroller, ATmega8515, which features self-programming that enables firmware to be upgraded directly from a PC (without opening the controller). This would enable users to download new firmware from the Internet and install it themselves. At the same time, ATmega8515 with its 16 MHz clock frequency would double maximum transfer rate, since the microcontroller is the limiting factor. The speed can be further increased by using special GPIB circuits. Many features can be added in the driver and therefore performed in the field, without using a microcontroller programmer. Nevertheless, drivers can be upgraded easily in LabVIEW programming environment as well as easily adapted to other programming environments that support serial port. VISA drivers would also be beneficial and would additionally ease conversion of existing programs. Nonetheless, USB interface enables the controller to be used with both, desktop computers and notebooks. In this way, re- searchers may use their notebooks to run self-built virtual instruments with the USB GPIB controller in a laboratory. Furthermore, non-standard features can be also implemented. GPIB printer emulation was already successfully applied and used for digital oscilloscope's (HP 54600B) waveform printout. The controller is comparable (concerning speed and dimensions) to commercial controllers like National Instruments' GPIB USB B. Acknowledgments Franc Smole and Janko Drnovšek are acknowledged for helpful discussions. References /1/ W. Winiecki, Methodology for teaching measuring systems, Measurement, Vol. 18(4), 1996, pp. 237-244 /2/ B. Murovec, S. Kocijancic, A USB-based Data Acquisition System Designed for Educational Purposes, The International Journal of Engineering Education, Vol. 20, 2004, pp. 24-30 /3/ M. Smith, Bridging the future of GPIB, R&D Magazine, Vol. 43, 2001, p. 10, Available: http://www.rdmag.com/features/ 0112gpib.asp /4/ Choosing the Right Bus Technology: LAN, USB, GPIB, PCI/PXI, Automated test summit 2005, National Instruments' seminar, 2005 /5/ B. Glažar, M. Jankovec, M. Topič, USB based GPIB controller, EDN (Electronic Design News), 2005, in-print /6/ M. Colloms, Computer controlled testing and instrumentation: an introduction to the IEC-625: IEEE-488 bus, Pentech Press, 1983 /7/ FT245BM USB FIFO (USB-Parallel) I.C., /FTDI datasheet/, Available: http://www.ftdi.co.uk, 2003 /8/ SN75160B, Octal General-Purpose Interface Bus Transceiver, /Texas Instruments datasheet/, 1995 /9/ SN75161 B, SN75162B, Octal General-Purpose Interface Bus Transceivers, /Texas Instruments datasheet/, 1995 /10/ AT90S8515, 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash, /ATMELdatasheet/, /Online/, Available: http://www.atmel.com, 2001 /11/ B. A. Forouzan, Introduction to data communications and networking, WCB/McGraw-Hill, 1998 /12/ R. H. Bishop, LabVIEW student edition 6i, Prentice Hall, Upper Saddle River, 2001 Boštjan Glažar, unlv. dipl. ing. el. Dr. Marko Jankovec, unlv. dipl. ing. el. Prof. dr. Marko Topič, univ. dipl. ing. el. University of Ljubljana, Faculty of Electrical Engineering Laboratory of Semiconductor Devices Tržaška cesta 25, SI-1000 Ljubljana, Slovenia Tel.: +386 (0)1 4768 723, Fax: +386 (0)1 4264 630 E-mail: bostjan.glazar@fe.uni Ij.sl Prispelo (Arrived): 01.06.2005 Sprejeto (Accepted): 30.09.2005 147 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 35(2005)4, Ljubljana AFFINITY OF CONTACT MATERIALS TO FORM THE ELECTRIC DRAWN ARCS 1 France Pavlovčič, 2Janez Nastran 1 Ministry for environment and spatial planning, Environmental Agency of the Republic of Slovenia 2University of Ljubljana, Faculty of electrical engineering, Ljubljana, Slovenia Key words: drawn electric arc, arc formation, sliding contact, commutator, arc ignition voltage, contact material. Abstract: Electro mechanic contacts are widely used In several appliances, because they are cheap, but also very robust, capable to withstand overvolt-age and overcurrent surges, and when used in electric relays they enable galvanic separation of electric circuits. Especially they are necessary with commutators of universal electric motors for they are enabling commutation. These motors achieve high power per a unit of volume due to their high shaft speed, and they are produced at relatively low costs for a unit of power. So, they are economically very Important for their numerous production, and they use sliding contacts for their operation. The sliding contacts are mechanical contacts, as switching contacts are, and so electric arcs ignite between their contact members during commutation. Therefore it is very important to determine contact materials with a small tendency to form the electric arcs. The arcs between electrodes of the sliding contacts are usually drawn arcs, so that affinity of the contact material to form the drawn arcs is very significant attribute of determining the right contact mate-rials. Conclusions made for the sliding contacts are also useful for the switching contacts. Težnja kontaktnih materialov k tvorjenju električnih potegnjenih oblokov Kjučne besede: potegnjeni električni oblok, nastanek obloka, drsni kontakt, komutator, nape-tost vžiga obloka, kontaktni material. Izvleček: Elektromehanskl kontakti so množično uporabljeni v številnih napravah, ker so poceni, vendar robustni, zmožni vzdržati prenapetostne in preto-kovne preobremenitve In kadar so uporabljeni v električnih relejih omogočajo galvansko ločitev tokokrogov. Posebno so nepogrešljivi pri komutatorjih univerzalnih električnih motorjev, kajti omogočajo komutacijo. Ti motorji razvijejo veliko moč na enoto volumna zaradi velike hitrosti vrtenja in njihovi proizvodni stroški na enoto moči so relativno majhni. Zaradi njihove velikoserijske proizvodnje so ekonomsko zelo pomembni. Za svoje obratovanje pa uporabljajo drsne kontakte. Drsni kontakti so mehanski kontakti, kakor so tudi stikalni kontakti In zato se med njihovimi kontakti pri komutaciji vžgejo električni obloki. Zato je zelo pomembno določiti kontaktne materiale z majhno tendenco tvorjenja električnih oblokov. Oblokl med drsnimi kontakti so ponavadi potegnjeni oblokl, tako da je težnja kontaktnih materialov k tvorjenju potegnjenih oblokov zelo pomembna lastnost pri določanju pravega kontaktnega materiala. Zaključki, narejeni za drsne kontakte, so uporabni tudi za stikalne kontakte. 1. Introduction Talking about affinity of the contact materials to form the electric drawn arcs, we must have In mind that it is not a physical quantity, but rather a conception, which is numerically estimated by one or more physical quantities. To begin with, we consider the voltage - current (Ul) stationary electric arc characteristics, for instance of the copper contacts, shown in Fig. 1 as hyperbolae, in relation to the pure resistive load, shown In the same figure - the line marked with the label "break" /1/. This line illustrates the load characteristic of the electric arc at the breaking of an electric resistive circuit by the axial switching contacts. This drawn arc ignites at the voltage of 13.1 V, which is slightly over the voltage of the asymptote of the hyperbolae, and at the current of 1.95 A. The voltage of the asymptote Is defined as the minimal arc voltage Um by Holm /1/ and it is the property of the material. But we name it as the inflmum arc voltage because It is the greatest lower limit voltage. The arc burns until Its length Is 0.8 mm and is extinguished at the voltage of 48.7 V and at the current of 0.73 A. load. Fig. 1: The Ul stationay and load arc characteristics. Legend: arc stationary arc characteristics, comm load arc characteristic at resistance commutation, break load arc characteristic at breaking resistive 148 F. Pavlovcic, J. Nastran: Affinity of Contact Materials to Form the Electric Drawn Arcs Informacije MIDEM 35(2005)3, str. 148-157 If another contact material is taken into consideration then the hyperbolic characteristics are the same curves, but voltage (Um) and the current (lm) the asymptotes have different values. The current asymptote is defined as the infi-mum arc current and is also the property of the material. If the value of the Um - asymptote is higher than the one of copper the arc ignites at a lower current, and of course, at a higher voltage, and its length is shorter at the point of the extinction. The values of the arc voltage and the arc current at its extinction are also changed. Because the ignition and the length of the arc are depended on the Um -asymptote, we decide that the infimum arc voltage is just the proper quantity to define affinity of the contact material to form the electric drawn arc. It seems very simple to define affinity of the contact materials to form the drawn arcs between the axial switching contacts, but in the case of the sliding contacts, such as they are in the commutators, is a much more difficult task. Namely, the drawn arc ignites and burns at a macroscopic geometrical separation of the axial switching contacts, but researching the arc phenomenon with the sliding contacts it must be taken into account, that the drawn arc ignites and burns between the overlapping electrodes with no macroscopic geometrical separation ofthem /2/,/3/. Ifwe consider only the Ul stationary arc characteristics and the load characteristic of the arc during the resistance commutation, shown in Fig. 1 - the diagram marked with the label "comm", it is not selfevident that the infimum arc voltage Is the measure of this kind of affinity. The arc ignites at the infimum value of the arc voltage and at the full value of the current through the contact. It burns at the voltage, which slightly rises from the infimum arc volt-age of 13 V up to 15.2 V for copper, and is extinguished at the latter value of the voltage and at the current of 0.59 A. Its length is in the range of some nanometres throughout its burning, so it is a short arc. It Is exactly the same with another contact material: the ignition occurs at the infimum arc voltage and at the full current, the burning is at its length of some nanometres and at the corresponding voltage, and extinction is nearly at the current asymptote, which value is the infimum arc current. Therefore we have to establish the mathematical model of electric current conduction through the gap of some nanometres between the commutator bar and the brush during the commutation to make a clear definition of affinity of the contact materials to form the drawn arcs. When the commutator bar moves over the brush, the thickness of the gap between them varies, and so the way of the current conduction alters from tunnel effect to arc conducting mode - Fig. 2, If the thickness of the gap is so large, that its corresponding voltage drop equals to or is greater than the infimum arc voltage Um, the arc ignites. With the same thickness of the gap, some contact materials form the drawn arcs, but some not, depending on their infimum arc voltage. As this voltage is the property of the contact material, it fully determines affinity of the contact material to form the electric drawn arc. Fig. 2: The formation of the electric drawn arc during the commutation. There are many physical constants and variables in this paper that are not explained in the text, so their definitions are present in the chapter of used symbols at the end of the paper. We also deal with many chemical elements, although they could not be used as pure materials in contact technique. The direct current case is considered by this model. 2. The mathematical model of the drawn arc formation With the sliding contacts of the commutator, a very thin insulating film arises on the contact surface /1 /,/4/. This film is the collector film. Beside it, there is also the gap between the contacts. The gap is filled with atoms and molecules of an external medium, and also with the atoms of the contact materials. The gap and the film thickness are up to a few nanometres, so that no ionization occurred. The electric current flows due to tunnel effect. One contact member is a cathode, the other one is an anode. The charge carriers are free electrons in the electric field of the gap, so they are accelerated when moving along the path through the gap. They are emitted from the cathode by three ways: by the field emission, called also the cold emission; by the thermionic emission including also the Schottky effect, which is depended on the electric field, but its contribution is not included in the cold emission; by the emission due to the different work functions of the cathode and anode materials. Considering the cathode is still cold, only the field emission is taken into account, and the current density is defined by the Fowler - Nordheim equation /5/,/6/ and /7/, which is equal to Eq. (1) for the electron emission from the smooth and unstained metal cathode in vacuum: 2 .2 S-n-^2-m)-e V^1 y/i-m'.-e3' . -1/2 i - e h ~ 3 A ' + 3-A-Eo 4* Experiments show that the electric field /8/, the work function /8/,/9/, which is defined as the voltage Vm , and the 149 Informacije MIDEM 35(2005)3, str. 148-157 F. Pavlovcic, J. Nastran: Affinity of Contact Materials to Form the Electric Drawn Arcs effective electron mass /10/,/11 / changed due to a contamination of the cathode, but the roughness of the cathode surface effects only the electric field intensity. So the following substitutions must take place to descride exploat-ation condition of the contacts: E* = fi - E <= (3 > 1 v: m„ 4>K V UK (I -o >1 <= \i> 1 (2), (3), (4). The collector film and the moleculas of the air gases in the very thin gap are considered as the contanimation over the cathode surface. Therefore the equation, describing the current density due to the cold emission from the cathode, overlayed with the collector film and being in the air, is: Jlm,-e3 nr , , , 1 V___ • _ e 'i-1 - 3-/.-ÏÏ 'M'U1 ■terfi'i^ Je ~ „ , t, 'e 8-71 -h v.: (t)K The current density is known in the most cases, so that the electric field intensity is calculated from Eq. (5) by some iterative method. The commutator bar moves over the brush, so the thickness of the gap increases, as it is demonstrated in Fig. 2. Presuming the electric field is homogeneous the acceleration of the electrons in the gap is constant. The kinetic energy of the electron is /11/: and the rootmeansquare value or, as it is also called, the effective value is: m„ ■ c W N, 1 + m V m„ + m-c (9). a y The motion of the electron is accelerated, so there is a constant force on the electron. This is the force of the electric field on the electron, and the vectors of the force and of the electric field are colinear: F = e-E (10). This force is also the function of the electron mass and his acceleration /11/, and the vectors of the force and of the acceleration are colinear: F = ■ m„ \3 J civ cit (11). A path the electron must move over to get the sufficient velocity for the ionization of the atom is derived from Eqs (10) and (11). This path is: m„ ■ c e-E 1 + 2 m, i Na me ■ c 1 + — m, V " 7 (12). w ek m„ ■ c - - m„ ■ c (6). When the electron achieves such a velocity, that his kinetic energy is: f \ W na 1 + m„ 777. (7), the ionization of the atoms in the gap begins. The energy Wn is the first ionization energy of one mole of the gaseous element in the gap. Two values of the electron velocity are derived from Eqs (6) and (7). The first one is the average value of the linear motion of the electron /2/, and the second one is the rootmeansquare value needed for the ionization when collision between the electron and the atom is not centric. The average value of the electron velocity is: m„ En N„ 1 + m„ m„ + m„ (8), Because the electric field is homogeneous, the voltage over this path is equal to: U = m„ ■ c \ V N A me ■ c 1 + - m, m„ (13). These two equations (12) and (13) are simplified according to the following rule of small numbers: Vl + 2-8"«1 + 8 8 «1. So, the path and the corresponding voltage are: Wn s = ■ e-E ■ N A W U= n e-NA (14), (15). These are the basic equations that determine the path of the electron flow and the voltage over this path, which is sufficient for the ionization. If the gap is shorter than this path the current flows due to tunnel effect. The ionization means the end of tunnel effect, and it is also the beginning of the formation of the drawn arc. Comparing the drawn and the discharging arc, the ionization is present at the formation of them both, but for the latter one, the overvolt- 150 F. Pavlovcic, J. Nastran: Affinity of Contact Materials to Form the Electric Drawn Arcs Informacije MIDEM 35(2005)3, str. 148-157 age between the contact members and the breakdown of the gap medium are the cause of the ignition. In the case of the drawn arc, the current conduction smoothly turns from tunnel effect to arc conducting mode, when the ionization begins. While the tunnel conduction has only one kind of the charge carriers, which are the electrons emitted from the cathode, the drawn arc conduction has the following charge carriers: the electrons passed from the cathode by the field emission; the electrons passed from the cathode by the thermionic emission at the higher value of the cathode temperature as with tunnel effect; the cathode and the anode ions, which resulted from the ionization of the free atoms of the cathode and the anode materials in the conducting volume of the gap. When the thickness of the gap sufficiently increases the ionization begins, but not the ionization of the cathode and the anode atoms at the same time. If the first Ionization energy of the cathode material Is lower as the first ionization energy of the anode material the ionization of the cathode atoms takes place, while the anode atoms are still not ionized. Further increase in the gap thickness - Fig. 2, causes that the electrons get the higher kinetic energy, sufficient to ionize the free anode atoms. So, there are three layers within the arc illustrated in Fig. 3: the first one, where the kinetic energy of the electrons is not sufficient to Ionize any free atoms in this layer; the free cathode and anode atoms only are present there, therefore this one is named the free atoms layer; the second one, where, in the discussed case, the cathode atoms are ionized, but the anode atoms are still neutral; this layer is the partly ionized layer; the third one, where all atoms are ionized is called the fully ionized layer. The free atoms layer is in literature /1 /,/4/ defined as a cathode layer, but only the cathode atoms and ions are taken into account with Its definition. To distinguish between our arc model, which considers the cathode and the anode atoms and ions, and the other arc model from the literature, we define the arc layers in this special way. The difference between the free atoms layer and the cathode layer, as defined in the literature, occurs when the first ionization energy of the cathode material Is higher than that of the anode material. When the fully ionized layer is established the drawn arc ignites. The question arises about the length of the path through the fully ionized layer. It must be so large that the ions, while moving along this path, get the sufficient kinetic energy to heat the cathode to such amount that the cathode atoms pass from the cathode to the gap by vaporization or by sublimation, and that the thermionic emission of «MD«-© free atoms layer partly ionized layer fully ionized layer © <- © <4® e-> ¿s® &•*■ i e-> p Vs I free cathode and anode atoms recombined cathode and anode atoms with constant velocity cathode and anode ions and electrons accelerated by E Fig. 3: The arc layers. the electrons is established. Further on, travelling toward the cathode, they are recombined, and their collisions against the cathode are nonperpendlcular. There must also be equilibrium of the charge carriers, so that the arc is neutral to the external medium. The mathematical model of the drawn arc formation has the following presumptions: there is only the field emission with tunnel effect; the electric field intensity is constant while the current conduction passes from tunnel effect to arc conducting mode; the electric field is also homogeneous; the contact current Is constant while the current conduction passes from tunnel effect to arc conducting mode; the motion of the electrons In the gap between the cathode and the anode Is linear; the collisions of the particles are not centric, northey are perpendicular; the ions are recombined before they collide against the cathode; the arc is externally neutral; the arc temperature is equal to the cathode temperature at the instant of the arc formation; the ratio between the number of the free cathode atoms and ions and the number of all free atoms and Ions in the conducting volume is calculated as the cathode and the anode temperatures are equal; the external medium is air under the normal pressure, or is optionally vacuum; the total pressure of gases In the conducting volume between the cathode and the anode Is equal to the pressure of the external medium, unless It is determined by the thermionic emission to be higher. There are the cathode and the anode atoms in the gap, which are Ionized by the collisions with the electrons. The 151 Informacije MIDEM 35(2005)3, str. 148-157 F. Pavlovcic, J. Nastran: Affinity of Contact Materials to Form the Electric Drawn Arcs first ionization energy of the cathode atoms is not equal to the one of the anode atoms. Therefore the electrons that ionize the cathode atoms have the different average and effective values of the velocity than the electrons that ionize the anode atoms. The ratio between the number of the free cathode atoms and ions and the number of all free atoms and ions in the conducting volume must be determined to calculate the overall average velocity of the electrons. This ratio is according to the ideal gas law: tIk PVK(TK) PvATK) + Pva(Ta) PVK(TK) pvAtk)+Pv «(A) T -T (16). Presuming the current density is known, the density of the electrons is calculated: J e ■ 6K • V6K„avg + (l -TIk )■ Vea.avg ) ^ where the vek_avg and vea^avg are the average values of the velocities of the electrons that are to ionize the cathode and the anode atoms respectively. According to the ideal gas law we get the following equation: PVK(TK) + Pm(TK) = maX- \ a-N. ■R'TK,Pe. (24). In Eq. (16), there are the saturated vapour pressures of the cathode and the anode atoms and ions. They are determined according to the Clapeyron - Clausius equations /11/: dpVK(TK) LVK(TK}PVK(TK) d T r-T: v. = 0 [l/K V, Hl'K (17), dpM Lva (Tk )• pva (Tk ) d T ( R-T:- V, H/a V, ¡.tva (18). J The LVk and Lva are the values of the latent heat of vaporization of the cathode and the anode materials depended on the cathode temperature. Their functions are presented as the linear interpolated equations between the boiling and the critical temperatures: - Z "VAk A.(A)=A, T -T A>a (A ) A, Tr b k A ■ba T -T X ,-rs Ur (19), (20). ' ca ba The ratios between the volume of one mole of the material in liquid state and the one in gaseous state are neglected V in Eqs (17) and (18) as —^ y ■ 0 A —- v,„.„ ■ 0. So, the satu- rated vapour pressures for the cathode and the anode materials are: Pv (T) = : V K / P vb ■ > T„ j;K rK frfc-7;,) I r,. rbK Tb T T T 'ca 1c/ " K A f' : Vs • c? * r* ^ ...sS^ o. ^ ^ * 2+)the first ionization energy of oxygen molecules, WfO —* 0+) the first ionization energy of oxygen atoms, Wf02 20) dissociation energy of oxygen molecules. The ionization coefficient a is less than 1 with the whole conducting volume of the gap. The cathode temperature is calculated from this Eq. (24) by some iterative method. The pressure of the external medium is pexl =101.325 [kPa] when it is air, but zero with vacuum. The question is, why the external medium is so important. The external medium is air, so it contains the nitrogen molecules (78%) and the oxygen molecules (21 %). If the saturated vapour pressure of the catode and the anode atoms 152 F. Pavlovcic, J. Nastran: Affinity of Contact Materials to Form the Electric Drawn Arcs Informacije MIDEM 35(2005)3, str. 148-157 and ions together is less than the pressure of external medium the molecules of the external gas are also present in the gap, but their partial pressure is less than the external pressure. There are also the collisions between the electrons and the nitrogen and the oxygen molecules. This collisions are elastic, unless the kinetic energy of the elec-tons is sufficient to ionize the nitrogen and the oxygen moléculas, orto dissociate them and further on, to ionize the gaseous atoms. Though the collisions are elastic, the velocity vector of the electrons changes by impacts, and cosequently the final kinetic energy of the elecrons changes. The sufficient kinetic energy of the electrons for full ionization is gained after they have moved along the path through some layer, so we define this energy to be the layer energy. According to Eq. (14) the layer energy is not depended on the particles, which are either the electrons or the ions. The layer energy of the free atoms layer and the partly ionized layer together and the layer energy of the fully ionized layer for several cathode materials, while the anode is carbon, are compared with the first ionization energy of the molecules, the dissociation energy and the first ionization energy of the atoms of nitrogen and of oxygen. The results are shown in Fig. 4. The dissociation energy of the nitrogen and the oxygen molecules is achieved with some cathode materials in the first two layers of the arc. But no ionization energy of the nitrogen and the oxygen particles is ever achieved. The elastic collisions and the dissociation of the nitrogen and the oxygen molecules waste the kinetic energy of the electrons, so that the total ionization of the cathode and the anode atoms is not attained in the fully ionized layer. To establish the arc, the cathode temperature is increasing, so that the total saturated vapour pressure of the cathode and the anode atoms and ions forces the nitrogen and the oxygen particles out of the conducting volume of the gap. Then the conditions for the arc formation exist. The current density due to the thermionic emission is defined by the Richardson - Dushman equation /5/: JT=- 4-tc -m, ■e-k2 h ■T k-Tr \l 4-Jt -e0 (25). The presumptions have the following effects on the total current density and on the crosssection of the conducting path between the cathode and the anode, that is the cross-section of the arc: E = const J = Je+JT I - const A. A Je sel (26), (27). Je + JT The current density increases, but the cross-section constricts. A narrow ionized conducting channel, something similar as a pilot streamer at discharges /12/, arises. It is a hot flow of the electrons, the cathode and the anode ions and atoms. The absence of the ions of the air gases of the external medium is the main difference between the drawn and the discharge arcs. There is a loop in this procedure: Eq. (26) effects Eq. (23), but the algorithm converges. The results of the temperature calculations for the electrodes, both of the same metal, are presented in Fig. 5. The comparison is carried out between the air medium and the vaccum, and further on, the cathode temperatures toward the melting and the boiling temperatures. The cathode temperatures are somehow between the melting and the boiling points, but there are some exceptions. Fig. 5: f ' ' * i/ V S V ->J < " The cathode temperatures, melting and boiling temperatures. Legend: Tm melting temperature, Tb boiling temperature, Tk-air cathode temperature in air, Tk-vac cathode temperature in vacuum. So far we presume that both, the cathode and the anode atoms and ions are present in the conducting volume of the gap. The number of the cathode atoms and ions Na+ik and the number of the anode atoms and ions Na+ia are natural numbers unequal to zero. But it could happen, especially with refractory materials, that either one of them Is zero. It means, that it is possible with the great mathematical confidence, that the atoms and ions of one material are absent in the tiny conducting volume of the gap. The Dirac and Heaviside functions are introduced to include such cases into the mathematical model. The used Dirac function is symmetrical, but the Heaviside function is asymmetrical: V+ (x < 0)= 0 1/+(x>0)=l (28). While the electron moves along the sufficient path, it achieves the energy to ionize the cathode atom, which has the corresponding voltage drop, derived from Eq. (15), and equals to: U,. e ■ N (29). A The corresponding voltage for the ionization of the anode atoms is: 153 F. Pavlovcic, J. Nastran: Informacije MIDEM 35(2005)3, str. 148-157 Affinity of Contact Materials to Form the Electric Drawn Arcs U„ ¡la e- N. (30). The voltage drop of the free atoms layer is: Ua„„=rnrn(UK,Ua) = _ min(j■ (5 (Na+nc )+1) Wna ■ (5 (Na+ia )+1)) (31 ). e- N, The voltage of the partly ionized layer is: i/0+,=max(t/,,i7j-min(i/K,C/a) = _ max(WÜK ■ (/V,H,_ } Wna • (Na,,a )) ^ (32). e-N, All atoms are ionized at the far end of the partly ionized layer, looking from the cathode. Then the full ionized layer begins. In this layer, the ions are accelerated toward the cathode by the electric field. But, when they leave this layer, they are recombined, because they are not immune to the collisions from the electrons. From this point on, the recombined atoms move toward the cathode uniformly with the constant velocity, hence there is no force on them due to the electric field, for they are neutral. The velocity of the ions is gained in the fully ionized layer, and the corresponding kinetic energy must be sufficient to heat the cathode to cause the vaporization or the sublimation of the cathode material, and to cause also the thermionic emission of the electrons. The average kinetic energy of the ion, either it is of the cathode or of anode material, is: There is one parameter in the calculation of the cathode temperature - Eq. (24), which has not been fully defined. It is the ionization coefficient of the whole conducting volume. The volume occupied only by the ions is the volume of the fully ionized layer. There are some ions also in the partly ionized layer, but we neglect them when estimating the ionization coefficient. The density of the ions and atoms together is constant throughout the whole conducting volume, so the coefficient is the ratio of the volume of the fully ionized layer and the whole conducting volume. Presuming the crosssection area is uniform the coefficient is the ratio of the thickness of the fully ionized layer and the arc path. Because the electric field is homogeneous the ionization coefficient becomes: a _ ion U„ (37). So, this equation leads to another loop in the mathematical model - Eq. (24), but the convergence still exists. The results of this mathematical model are shown in Fig. 6. The infimum arc voltage directly depends on the energy of the first ionization of the cathode and the anode material, on the latent heat of vaporization of the cathode material, and on the energy of the work function of the cathode. These quantities are the properties of the contact materials. But, this voltage also depends on the cathode temperature indirectly through the ratio between the number of the free cathode atoms and ions and the number of all free atoms and ions. The whole model is recalculated at the contact current I = 1 A, at the crosssection of the conducting path Asd = 5x10 6 m2, and the coefficients b, u and /J being unit. ionk ~ t,t NA v Because the energy of the work function is: (33), (34) the voltage drop of the full ionized layer, derived from Eq. (15), is: ."Hk -V+A e ■ Na e-v (35). The infitnum arc voltage is the sum of the layers voltages ■ Eqs (31), (32) and (35), and it is: u„,=ualm + ua+,+uhn = __ max(WilK ■ V+ (Na+iK ) Wna ■ V+ (Na+ia )) e-N.t e-NA e-v (36). Fig. 6: The infimum arc voltage with its influential quantities depended on the cathode material against the anode of the same material. Legend: Wi1 k energy of 1s' ionization of cathode material, Lvk latent heat of vaporization of cathode material, (|)k energy of work function, Um infimum arc voltage. 154 F. Pavlovcic, J. Nastran: Affinity of Contact Materials to Form the Electric Drawn Arcs Informacije MIDEM 35(2005)3, str. 148-157 It has to be emphasized that the cathode temperature depends mainly on the latent heat of vaporization of the cathode and the anode material, their boiling and critical temperatures, and the external pressure. 3. The comparison of the results The infimum arc voltage is determined not only by the cathode material, but also by the anode material. The diagrams in Fig. 7 show the infimum arc voltage depended on the cathode material when facing the anode made by the same material, and the one of tungsten and of carbon. The next diagrams in Fig. 8 present the comparison of the infimum arc voltage achieved by our model and the values of the minimal arc voltages according to Holm, Fink and Gaulrapp /1/, which are considered as experimental values. But, as stated in the literature /1 / and presented in Fig. 8, several researchers got very different results of their experimental determination of the minimal arc voltage, although they are determined by the contact electrodes of the same material. These authors considered that minimal arc voltage is essentially determined only by the cathode material, nevertheless the contact electrodes are made of the different material. That is the significant difference from our model. s | ; ■3 .< I ; ; '1 i I ti 2835 K by the model and up to 2273 K by their estimation of the experiment /2/. The comparison between the model results and the experimental results by several researchers/1/ is illustrated in Fig. 8. Having in mind uncertainties of the experimental results, and the fact that the results of the model are presented without any contamination of the electrodes and with no roughness of the contact surfaces, the results are estimated as very good and useful. 4. Conclusions The evaluation of affinity of the contact materials to form the drawn electric arc carried out by defining the infimum arc voltage for several combination of the contact materials is only one aspect of determining the proper contact materials. The second parameter to be taken into account is the cathode temperature, which is also obtainable by this model, especially, when reducing it under the calculated value by heat transfer to the external medium, and so avoiding the arc. c t,» # * -»VV*-* k work function energy in vacuum £o dielectric constant in vacuum ¡J factor between rest and effective electron mass Aarc cross-section of arc Asci cross-section of path of current conducting by t unnel effect c light velocity in vacuum e elementary charge £ electric field intensity £* enhanced electric field intensity ex exponential function F force h Planck constant I contact current j contact current density /e current density due to cold emission /V current density due to thermionic emission k Boltzmann constant LVk molar latent heat of vaporization of cathode material Lva molar latent heat of vaporization of anode material LVbk molar latent heat of vaporization of cathode material at boiling temperature Lvba molar latent heat of vaporization of anode material at boiling temperature /Tla rest atom mass me rest electron mass me* effektive electron mass Na Avogadro number Na+ik number of free cathode atoms and ions Na+ia number of free anode atoms and ions ne electron density Pvk saturated vapour pressure of cathode atoms and ions Pva saturated vapour pressure of anode atoms and ions Pvb saturated vapour pressure of boiling point R general gaseous constant s path through layer Tk cathode temperatrure Tbk cathode boiling temperature Tba anode boiling temperature TCk cathode critical temperature Tea anode critical temperature u layer voltage Ua+I partly ionized layer voltage Uatm free atoms layer voltage Uion fully ionized layer voltage um infimum arc voltage v+ asymmetrical Heaviside unit function V particle velocity Ve_avg average electron velocity vefc_avg average electron velocity up to ionization of cathode atom ve«_ai/gaverage electron velocity up to ionization of anode atom ve_ms effective (root-mean-squere) electron velocity V Belo perilo > START". Uporabnik, ki nima veliko znanja o pranju bo na primer uporabil naslednje zaporedje ukazov: Čarovnik pranja > Belo perilo >..... Napredni uporabnik pa bo uporabil, Moji programi, Dodatni programi, Orodja, ali nekatere druge, hkrati pa bo poizkusil uporabiti dodatne nastavitve glede na svoje želje in potrebe. Vmesnik, zgrajen na osnovi ikon Slika 7 prikazuje še drugi tip grafičnega vmesnika, ki je zasnovan na principu ikon. Ta vmesnik prikazuje v glavnem ikone. Polje z ikono je hkrati tudi ukazna tipka. S pritiskom na določeno polje Izberemo ustrezno funkcijo. Dodatni teksti so seveda lahko v različnih jezikih, na tej sliki je to sedaj slovenski jezik. Uporabnik lahko izbere seveda njemu domači jezik. Figure 8: Mešani tip grafičnega vmesnika. Z opisanimi pristopi lahko dejansko načrtujemo inteligentne in prilagodljive grafične vmesnike z vsemi modernimi grafičnimi strukturami, ki jih na primer najdemo v okolju PC oken. V fazi načrtovanja uporabniškega grafičnega vmesnika lahko torej uporabimo različne pristope pri oblikovanju upravljalnih struktur. Povezljivost in ergonomija Povezljivost v beli tehniki postaja vse bolj atraktivna za trg. Bodoči aparati bodo postali terminali svetovnega sistema storitev, ki bodo postale neposredno dostopne preko globalnega storitvenega omrežja. Aparati, ki bodo delovali kot terminali takšnega svetovnega omrežja, bodo postajali bolj in bolj zapleteni s številnimi dodatnimi funkcijami. Takšni aparati bodo običajno postali del svetovnega spleta - Interneta. Uporaba takšnih aparatov bo postala kompleksna in bo zahtevala primerno izučenega ali pa zelo dovzetnega uporabnika. Za modernega uporabnika takšna naprava ne bo predstavljala ovire pri uporabi. Čedalje bolj pomemben bo postajal uporabniško prijazen grafični vmesnik za upravljanje, ki bo na primeren način predstavil nove funkcionalnosti aparatov. Za takšne cilje je zelo primerna opisana vhodno-izhodna naprava, saj bomo za povezani hišni sistem vsekakor potrebovali uporabniško prijazne grafične vmesnike za upravljanje. Uporabnik bo lahko dosegal te naprave tudi preko drugih vhodno-lzhodnlh naprav grafičnega tipa. Zaključek LCD z vgrajeno enoto, občutljivo na dotik vsekakor ni nova Figure 7; Grafični vmesnik z ikonami. naprava na trgu. Uporablja se že v različnih napravah: me- 163 Informacije MIDEM 35(2005)3, Ljubljana rilni opremi, dlančnikih, prenosnih telefonih, itd. Opisana implementacija za področje bele tehnike pa je vsekakor nova na svetovnem trgu. Menimo, da bodo imele opisane lastnosti našega LCD zaslona z vgrajeno enoto občutljivo na dotik pomemben vpliv na ergonomske lastnosti aparatov bele tehnike in bodo vplivale na bodoče pristope pri oblikovanju bele tehnike. Vsekakor pa smo prepričani, da se tudi pri razvoju platforme strojne in programske opreme grafičnih LCD uporabniških vmesnikov nismo ustavili, am- pak bomo nadaljevali razvoj takšnih in podobnih modernih elektronskih naprav za uporabo v naših aparatih. Konrad Steblovnik Razvoj Inteligentni dom Vodja razvoja GORENJE POINT Partizanska 12a, Velenje, Slovenija 164 Informacije MIDEM 35(2005)3, Ljubljana PREDSTAVLJAMO PODJETJE Z NASLOVNICE WE PRESENT COMPANY FROM FRONT PAGE HIPOT-R&D d.o.o., Šentjernej, Slovenia The HIPOT-R&D Research and Development in Technologies and Systems Company is established in 1996 to act as a research organisation for local electronic elements companies. Current research and development activities are organised in the HIPOT-R&D Company through research and development group. This group is responsible for research, development and technology transfer in the fields of thick-film hybrid microelectronics, sensors (mostly pressure sensors), electronics, electronics technologies, and electromechanical devices and systems. In the field of research and development, as well as in system upgrading the company works in close relationship with scientific institutions and technical associations both in Slovenia and worldwide. The co-operation with research partner "Jožef Stefan" Institute in Ljubljana is traditional and goes back to the 1970s. One part of the HIPOT-R&D Company is located in Ljubljana at the "Jožef Stefan" Institute and other part is in Šentjernej at the same location as industrial partner HYB d.o.o.. This distribution enables a very good co-operation between partners. Company address HIPOT-RR d.o.o. Address: Trubarjeva 7, 8310 Šentjernej, Slovenia Phone: ++386 7 39 34 933 Fax: ++386 7 39 34 934 HUB HYB d.o.o., Šentjernej, Slovenia The HYB Hybrid Circuits and Sensors Company (it is in the category of SME) has experience in the production of custom thick-film hybrid circuits from 1972 and experience in the production of pressure sensors for medical applications from 1986 and for industrial applications from 1994. A thick-film hybrid circuit can be described as a small, self-contained electronic circuit (module) made up of a ceramic substrate with a thick-film technology and a variety of different component types mounted on it with different assembling techniques. The markets for these products are mainly where reliability, space, weight are at a premium. Moreover in most cases the customer provides these and some other special performance requirements. This is known as a custom-designed hybrid circuit. The HYB has a complete technical staff to handle all aspects of the design and manufacture process. HYB is renowned European designer and producer of pressure sensors for medical and industrial applications. The company is capable to design, construct, develop and manufacture pressure sensors with silicon or ceramic sensor elements and required signal conditioning electronic circuit. Company address HYB d.o.o. Address: Trubarjeva 7, 8310 Šentjernej, Slovenia Phone: ++386 7 39 34 800 Fax: ++386 7 39 34 849 site: www.hyb.sl g . «a-- i®«*5™ The example of custom designed thick-film hybrid circuit with SMD components. 165 Informacije MIDEM 35(2005)3, Ljubljana 'I Pressure sensor with thick-film hybrid circuits for signal conditioning was designed for industrial applications. Ceramic pressure sensor (with ASIC for signal conditioning) is using especially in harsh environment. warn - * f ' > - 4T- -if l i- .«iti»! Production plant of the HYB Company in Šentjernej, Slovenia 166 Informacije MIDEM 35(2005)3, Ljubljana I ^ > -'iëiÂ^Oj^^^gï^i^liÉ^ Nlfäri- "Afïiii Tâ'sûïs Top y-'-;';; :: ; - !f eriiië ; ■ -i ■. ;: • • c ; v . ■ ' ' č'ï ; r ç .. ; ^, il it p ■ "..'■■-t;/; .'■■'■' ' . A&stiact ctescllô^ ; ■ The Technical Programme Committee invites authors tu submit abstracts of original work describing recent developments in the field ut microelectronic packaging and interconnection. The topics of the EMPS 2006 follow the motto "Everything in cicciionic, between the chip Interconnection technologies & substrates > Semiconductor structures and circuits Passive components, active devices iksystems Electrical., thermal,, mechanical and multi-physics simulations > Microelectronic applications: p- Quality & reliability Please submit yout 300-vvoid obsttoct with n title cjnd auHior-contaci, iniormaUon before Octob«r 31r ?!)U5 via the conference website: www.EMPS200G.com "Hie Technical Programme Committee wiil evaluate alt abstracts and authors will be informed about Hie acceptance of their abstract by December 31, 2005, Eveiy two years the International MiCKU'lectroffics And Fackaqinrj Society, IMAFSs, fcusype organises the European Microelectronics and Packaging Symposium, C-MPS, in a different European country. The EMPS brings together specialists from Industry and acidemia, and fs a great opportunity for presenting and discussing on the ,ubw_ct or mfcificlertrvjtr < ', ¡;! be 'l':i, Vv<„' : -,iu>< en -, .. ~ ' !, .-'Up;-, Organised im MIDEM ~ Society for Microelectronics, Electronic Components and Materials - ¡MAPS Slovenia Chapter Dunajska 10, SI-1Q0G Ljubljana, Slovenia http://www,midem-